1402

FEATURES s s s s s s s s s s s s s LTC1402 Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown DESCRIPTIO The LTC®1402 is a 12-bit, 2.2Msps sampling A/D converter. This high performance device includes a high dynamic range sample-and-hold and a precision reference. It operates from a single 5V supply or dual ± 5V supplies and draws only 90mW from 5V. The versatile differential input offers a unipolar range of 4.096V and a bipolar range of ± 2.048V for dual supply systems where high performance op amps perform best, eliminating the need for special translation circuitry. The high common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. Outstanding AC performance includes 72dB S/(N + D) and –93dB SFDR at the Nyquist input frequency of 1.1MHz with dual ±5V supplies and –84dB SFDR with a single 5V supply. The LTC1402 has two power saving modes: Nap and Sleep. Nap mode consumes only 15mW of power and can wake up and convert immediately. In Sleep mode, it typically consumes 10µW of power. Upon power-up from Sleep mode, a reference ready (REFRDY) signal is available in the serial data word to indicate that the reference has settled and the chip is ready to convert. The 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcontrollers and DSPs. A digital output driver power supply pin allows direct connection to 3V or lower logic. Sample Rate: 2.2Msps 72dB S/(N + D) and –89dB THD at Nyquist Power Dissipation: 90mW (Typ) 80MHz Full Power Bandwidth Sampling No Missing Codes over Temperature Available in 16-Pin Narrow SSOP Package Single Supply 5V or ± 5V Operation Nap Mode with Instant Wake-Up: 15mW Sleep Mode: 10µW True Differential Inputs Reject Common Mode Noise Input Range (1mV/LSB): 0V to 4.096V or ± 2.048V Internal Reference Can Be Overdriven Externally 3-Wire Interface to DSPs and Processors (SPI and MICROWIRETM Compatible) APPLICATIO S s s s s s s s s Telecommunications High Speed Data and Signal Acquisition Digitally Multiplexed Data Acquisition Systems Digital Radio Receivers Spectrum Analysis Low Power and Battery-Operated Systems Handheld or Portable Instruments Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corp. BLOCK DIAGRA 10µF AIN+ AIN– VREF 3 SAMPLEAND-HOLD 5V 1 AVDD 12 DVDD 3V OR 5V 11 OVDD 5 Harmonic THD, 2nd, 3rd and SFDR vs Input Frequency (Unipolar) 0 –10 –20 THD, SFDR, 2ND 3RD (dB) 12-BIT ADC 4 5 10µF OUTPUT BUFFER 10 DOUT –30 –40 –50 –60 –70 –80 –90 –100 –110 4.096V 64k – 8 2.048 REFERENCE 2 AGND1 6 AGND2 TIMING LOGIC 13 DGND 9 OGND 16 15 1402 TA01 GAIN 7 64k LTC1402 14 + BIP/UNI CONV SCK VSS 10µF –5V OR 0V –120 104 U W U THD SFDR 2ND 3RD fSAMPLE = 2.22MHz 105 106 INPUT FREQUENCY (Hz) 107 1401 G05 1 LTC1402 ABSOLUTE MAXIMUM RATINGS AVDD = DVDD = OVDD = VDD (Notes 1, 2) PACKAGE/ORDER INFORMATION TOP VIEW AVDD 1 AGND1 2 AIN+ 3 AIN– 4 VREF 5 AGND2 6 GAIN 7 BIP/UNI 8 16 CONV 15 SCK 14 VSS 13 DGND 12 DVDD 11 0VDD 10 DOUT 9 OGND Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) .......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) .......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Output Voltage ......... (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 250mW Operation Temperature Range LTC1402C ............................................... 0°C to 70°C LTC1402I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1402CGN LTC1402IGN GN PART MARKING 1402 1402I GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 125°C, θJA = 150°C/ W Consult factory for Military grade parts. CONVERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Offset Error Full-Scale Error Full-Scale Tempco The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference (Note 5). CONDITIONS q MIN 12 q q q q TYP ± 0.35 ± 0.25 ±2 ± 10 ± 15 ±1 MAX ±1 ±1 ± 10 ± 15 UNITS Bits LSB LSB LSB LSB ppm/°C ppm/°C (Note 6) (Note 6) (Note 6) (Note 6) Internal Reference (Note 6) External Reference A ALOG I PUT SYMBOL VIN PARAMETER The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS Bipolar Mode with BIP/UNI High 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V Unipolar Mode with BIP/UNI Low 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ 0V VCM IIN CIN tACQ tAP tJITTER CMRR Analog Common Mode + Differential Input Range (Note 12) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 2V to – 2V fIN = 100MHz, VIN = 2V to – 2V (Note 9) q q MIN TYP ± 2.048 MAX UNITS V Analog Differential Input Range (Notes 3, 11) q 0 to 4.096 Dual ± 5V Supply Single 5V Supply q –2.5 to 5 0 to 5 1 10 57 2.6 1 – 62 – 24 2 U W U U WW W U U U V V V µA pF ns ns ps dB dB LTC1402 DYNAMIC ACCURACY SYMBOL S/(N + D) THD PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Bipolar mode with ± 5V supplies and unipolar mode with 5V supply. (Note 5) CONDITIONS 100kHz Input Signal 1.1MHz Input Signal 100kHz First 5 Harmonics, Bipolar Mode 1.1MHz First 5 Harmonics, Bipolar Mode 100kHz First 5 Harmonics, Unipolar Mode 1.1MHz First 5 Harmonics, Unipolar Mode 100kHz Input Signal, Bipolar Mode 1.1MHz Input Signal, Bipolar Mode 100kHz Input Signal, Unipolar Mode 1.1MHz Input Signal, Unipolar Mode ±1V 1.25MHz into AIN+ , 1.2MHz into AIN– Bipolar Mode 1.5V to 3.5V 1.25MHz into AIN+ , 1.2MHz into AIN– Unipolar Mode VREF = 4.096V, 1LSB = 1mV VIN = 4VP-P, DOUT = 2828LSBP-P (Note 18) S/(N + D) ≥ 68dB Bipolar Mode Unipolar Mode q q SFDR IMD INTERNAL REFERENCE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time CONDITIONS IOUT = 0 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN TYP 4.096 15 AVDD = 4.75V to 5.25V, VREF = 4.096V Load Current = 0.5mA 1 2 2 MAX UNITS V ppm/°C LSB/V Ω ms DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN q q q VOL IOZ COZ ISOURCE ISINK Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current U U U WU U MIN 69 TYP 72.5 72.0 –89 –89 –87 –82 –93 –93 –93 –84 –84 –84 0.18 82 5.0 3.5 MAX UNITS dB dB –74.5 dB dB dB dB dB dB dB dB dB dB LSBRMS MHz MHz MHz Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth U TYP MAX 0.8 ± 10 UNITS V V µA pF V V V 2.4 5 OVDD = 4.75V, IOUT = – 10µA OVDD = 4.75V, IOUT = – 200µA OVDD = 3V, IOUT = – 200µA VDD = 4.75V, IOUT = 160µA VDD = 4.75V, IOUT = 1.6mA VOUT = 0V to VDD VOUT = 0V, OVDD = 5V VOUT = 0V, OVDD = 3V VOUT = OVDD = 5V 4.7 q q q q 4 2.5 2.9 0.05 0.10 15 – 40 – 15 40 0.4 ± 10 V V µA pF mA mA mA 3 LTC1402 POWER REQUIRE E TS SYMBOL VDD VSS IDD PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Active Mode Nap Mode Sleep Mode Active, Sleep or Nap Modes with SCK Off Active Mode with SCK in Fixed State (Hi or Lo) q q q The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN 4.75 – 5.25 18 3 2 90 TYP MAX 5.25 0 30 5 10 2 150 UNITS V V mA mA µA µA mW ISS PD Negative Supply Current Power Dissipation The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t0 t1 t2 t3 t4 t5 t6 t7 t8 t8a t9 t10 t11 t12 PARAMETER Maximum Sampling Frequency (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Minimum Clock Period Conversion Time 14th SCLK↑ to CONV↑ Interval Minimum Positive or Negative SCK Pulse Width CONV to SCK Setup Time SCK After CONV Minimum Positive or Negative CONV Pulse Width SCK to Sample Mode CONV to Hold Mode Minimum Delay Between Conversions Minimum Delay from SCK to Valid Bits 0 Through 11 Minimum Delay from SCK to Valid REFREADY SCK to Hi-Z at DOUT Previous DOUT Bit Remains Valid After SCK REFREADY Bit Delay After Sleep-to-Wake Transition VREF Settling Time After Sleep-to-Wake Transition (Note 9) (Notes 9, 10, 16) (Note 9) (Notes 9, 13) (Note 9) (Note 9) (Note 9) (Notes 9, 14) (Note 9) (Notes 9, 15) (Notes 9, 15) (Notes 9, 15) (Notes 9, 15) (Notes 9, 17) (Notes 9, 17) q q q q q q q q q q q q q q TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together. Note 3: When these pins are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or greater than VDD without latchup. Note 4: When these pins are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or greater than VDD. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 2.2MHz, VSS = 0V for unipolar mode specifications and VSS = – 5V for bipolar specifications. 4 UW UW CONDITIONS q q q MIN 2.2 TYP MAX 455 UNITS MHz ns ns SCK cycles ns 28 14 57 3.8 7.3 0 3.5 9 3.4 48 9 15 11.4 4 7 10 2 10000 6 12 5 14 5 12 20 16 ns ns ns ns ns ns ns ns ns ns ns ms ms Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded and using the internal reference in bipolar mode with ± 5V supplies. Note 7: Integral linearity is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 8: Bipolar offset is the offset measured from – 0.5LSB when the input flickers between 1000 0000 0000 and 0111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The analog input range is defined as the voltage difference between AIN+ and AIN–. The bipolar ± 2.048V input range could be used with a single 5V supply if the absolute voltages of the inputs remain within the single 5V supply voltage. LTC1402 ELECTRICAL CHARACTERISTICS Note 12: The absolute voltage at AIN+ and AIN– must be within this range. Note 13: If less than 7.3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns) because the 0.8ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 15: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 16: The time period for acquiring the input signal is started by the 14th rising clock and it is ended by the rising edge of convert. Note 17: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. The Sleep mode resets the REFREADY bit in the DOUT sequence. The REFREADY bit goes high again 10ms after the VREF has stopped slewing in wake up. This ensures valid REFREADY bit operation even with higher load capacitances at VREF. Note 18: The full power bandwidth is the frequency where the output code swing drops to 2828LSBs with a 4VP-P input sine wave. (Bipolar Mode Plots Run with Dual ± 5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C. 5 Harmonic THD, 2nd, 3rd and SFDR vs Input Frequency (Bipolar) 74 68 62 56 50 44 38 32 26 20 14 8 2 107 1401 G01 TYPICAL PERFOR A CE CHARACTERISTICS ENOBs and SINAD vs Input Frequency (Bipolar) 12 11 10 9 8 7 6 5 4 3 2 1 fSAMPLE = 2.22MHz 0 4 105 106 10 INPUT FREQUENCY (Hz) 0 –10 –20 EFFECTIVE NUMBER OF BITS THD, SFDR, 2ND 3RD (dB) –60 –70 –80 –90 –100 –110 –120 104 105 106 INPUT FREQUENCY (Hz) 107 1401 G02 SNR (dB) ENOBs and SINAD vs Input Frequency (Unipolar) 12 11 10 9 8 7 6 5 4 3 2 1f SAMPLE = 2.22MHz 0 4 105 106 10 INPUT FREQUENCY (Hz) 74 68 62 56 50 44 38 32 26 20 14 8 2 107 1401 G04 EFFECTIVE NUMBER OF BITS THD, SFDR, 2ND 3RD (dB) SNR (dB) UW SNR vs Input Frequency (Bipolar) –2 –8 –14 –20 –26 –32 –38 –44 –50 –56 –62 –68 –74 104 105 106 INPUT FREQUENCY (Hz) 107 1401 G03 –30 –40 –50 THD SFDR 2ND 3RD fSAMPLE = 2.22MHz fSAMPLE = 2.22MHz SIGNAL-TO-NOISE + DISTORTION (dB) SIGNAL-TO-NOISE + DISTORTION (dB) 5 Harmonic THD, 2nd, 3rd and SFDR vs Input Frequency (Unipolar) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 104 105 106 INPUT FREQUENCY (Hz) 107 1401 G05 SNR vs Input Frequency (Unipolar) –2 –8 –14 –20 –26 –32 –38 –44 –50 –56 –62 –68 –74 104 105 106 INPUT FREQUENCY (Hz) 107 1401 G06 THD SFDR 2ND 3RD fSAMPLE = 2.22MHz fSAMPLE = 2.22MHz 5 LTC1402 TYPICAL PERFOR A CE CHARACTERISTICS Sine Wave Spectrum Plot (Bipolar) ± 5V Supply 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fSAMPLE = 2222222.22Hz fSINE = 109592.01Hz 2048 SAMPLES 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 (Bipolar Mode Plots Run with Dual ± 5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C. Sine Wave Spectrum Plot (Bipolar) Dual ±5V Supply fSAMPLE = 2222222.22Hz fSINE = 1131727.43Hz 2048 SAMPLES AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 2ND 3RD 4TH 5TH 6TH 0.55 FREQUENCY (MHz) Sine Wave Spectrum Plot (Unipolar) 5V Supply 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fSAMPLE = 2222222.22Hz fSINE = 109592.01Hz 2048 SAMPLES 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 2ND 3RD 4TH 5TH 6TH 0.55 FREQUENCY (MHz) 4VP-P Power Bandwidth and 100mVP-P Small-Signal Bandwidth 5 0 AMPLITUDE (dB) –10 INTERNAL REFERENCE VOLTAGE (V) REJECTION (dB) –3 –5 4VP-P –10 –15 – 20 – 25 0.1 1 10 100 FREQUENCY (MHz) 6 UW 1402 G09 1402 G12 IMD Spectrum Plot (Bipolar) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fSAMPLE = 2352941.18Hz fSINEA = 1250000Hz ± 1V INTO AIN+ fSINEB = 1199449Hz ±1V INTO AIN– IMD = 83.9dB 2048 SAMPLES 2ND 4TH 6TH 3RD 5TH fA – fB 2fB fA – fB 2fA fA – 2fB 3fB fA + 2fB 3fA 1.11 0.55 FREQUENCY (MHz) 1.11 1402 G11 0.59 FREQUENCY (MHz) 2fA – fB 2fA + fB 1.18 1402 G10 Sine Wave Spectrum Plot (Unipolar) 5V Supply fSAMPLE = 2222222.22Hz fSINE = 1131727.43Hz 2048 SAMPLES IMD Spectrum Plot (Unipolar) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fSAMPLE = 2352941.18Hz fSINEA = 1250000Hz INTO AIN+, 1.5V TO 3.5V fSINEB = 1199449Hz INTO AIN–, 1.5V TO 3.5V IMD = – 84.1dB 2048 SAMPLES f A – fB 2fB fA + fB 2fA 3fB 2ND 4TH 6TH 3RD 5TH 2fA – fB, fA + 2fB 2fA + fB 3fA fA – 2fB 0.59 FREQUENCY (MHz) 1.18 1402 G13 1.11 0 0.55 FREQUENCY (MHz) 1.11 1402 G08 PSRR vs Frequency 0 4.100 Load Regulation for VREF 4.090 4.080 4070 100mVP-P – 20 – 30 – 40 – 50 – 60 –70 VCC VSS VDD DGND .4.060 4.050 4.040 1000 1402 F07 – 80 0.1 1 10 100 FREQUENCY (MHz) 1000 1402 G18 0 0.4 0.8 1.2 1.6 LOAD CURRENT (mA) 2.0 1402 G20 LTC1402 TYPICAL PERFOR A CE CHARACTERISTICS Positive Power Supply Rejection for VREF 4.095 1.00 fSAMPLE = 2.2MHz 0.75 0.50 (Bipolar Mode Plots Run with Dual ± 5V Supplies. Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C. Differential Nonlinearity vs Output Code (Bipolar) 1.00 fSAMPLE = 2.2MHz 0.75 0.50 INTERNAL REFERENCE VOLTAGE (mV) 4.090 4.085 DNL (LSB) 4.080 4.075 4.070 0 INL (LSB) 512 1024 1536 2048 2560 3072 3584 4096 CODE 1402 G15 4.065 4.5 4.75 5.0 5.25 VDD (V) 5.5 5.75 6.0 Negative Power Supply Rejection for VREF 4.095 1.00 INTERNAL REFERENCE VOLTAGE (mV) 4.090 4.085 DNL (LSB) 4.080 4.075 4.070 4.065 –5 –4 –3 –2 VSS (V) –1 0 1402 G19 0 INL (LSB) PIN FUNCTIONS AVDD (Pin 1): 5V Analog Power Supply. Bypass to AGND1 and solid analog ground plane with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic). AGND1 (Pin 2): Analog Ground. Tie to solid analog ground plane. The analog ground plane should be solid and have no cuts near the LTC1402. AIN+ (Pin 3): Positive Analog Signal Input. 0V to 4.096V in unipolar mode and ± 2.048V in bipolar mode when AIN– is grounded. Both of these ranges operate fully differentially with respect to AIN– . (Note 3) AIN– (Pin 4): Negative Analog Signal Input. Can be grounded or driven differentially with AIN+ . Identical to AIN+ , except that it inverts the input signal. (Note 3) VREF (Pin 5): 4.096V Reference Voltage Output. Bypass to AGND1 and solid analog ground plane with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic). AGND2 (Pin 6): Analog Ground Return for the Reference and Internal CDAC. AGND2 could be overdriven externally above ground. Tie to solid analog ground plane. UW Integral Nonlinearity vs Output Code (Bipolar) 0.25 0.25 0 –0.25 –0.50 –0.75 –1.00 0 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1402 G14 1402 G21 Differential Nonlinearity vs Output Code (Unipolar) 1.00 fSAMPLE = 2.2MHz 0.75 0.50 0.25 0.75 0.50 0.25 0 Integral Nonlinearity vs Output Code (Unipolar) fSAMPLE = 2.2MHz –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1402 G17 –0.25 –0.50 –0.75 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1402 G16 U U U 7 LTC1402 PIN FUNCTIONS GAIN (Pin 7): Tie to AGND2 to set the reference voltage to 4.096V or tie to VREF to set the reference voltage to 2.048V. (Note 4) BIP/UNI (Pin 8): Tie to logic low to set the input range to unipolar mode or tie to logic high to set the input range to bipolar mode. (Note 4) OGND (Pin 9): Output Ground for the Output Driver. This pin can be tied to the digital ground of the system. All other ground pins should be tied to the analog ground plane. DOUT (Pin 10): Three-State Data Output. (Note 3) Each output data word represents the analog input at the start of the previous conversion. OVDD (Pin 11): Output Data Driver Power. Tie to VDD when driving 5V logic. Tie to 3V when driving 3V logic. DVDD (Pin 12): Digital Power for Internal Logic. Bypass to DGND with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic). DGND (Pin 13): Digital Ground for Internal Logic. Tie to solid analog ground plane. VSS (Pin 14): Negative Supply Voltage. Bypass to solid analog ground plane with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic) or tie directly to the solid analog ground plane for single supply use. Must be set more negative than either AIN+ or AIN – . Set to 0V or – 5V. SCK (Pin 15): External Clock. Advances the conversion process and sequences the output data at DOUT on the rising edge. Responds to 5V or 3V CMOS and to TTL levels. (Note 4). One or more pulses wake from Nap or Sleep. CONV (Pin 16): Holds the input analog signal and starts the conversion on the rising edge. Responds to 5V or 3V CMOS and to TTL levels. (Note 4). Two pulses with SCK in fixed high or fixed low state start Nap Mode. Four pulses with SCK in fixed high or fixed low state start Sleep mode. BLOCK DIAGRA AIN+ 3 1 CSAMPLE 12 14 2.048V REF ZEROING SWITCHES AVDD DVDD VSS AIN– 4 GAIN VREF AGND2 AGND1 DGND 7 5 6 2 13 64k 8 W U U U CSAMPLE + REF AMP 12-BIT CAPACITIVE DAC + COMP – 64k – 8 SUCCESSIVE APPROXIMATION REGISTER INTERNAL CLOCK OUTPUT DRIVER 10 11 CONTROL LOGIC 9 BIP/UNI DOUT OVDD OGND 16 CONV 15 SCK 1402 BD LTC1402 TI I G DIAGRA S t2 t3 1 SCK t4 CONV t6 INTERNAL S/H STATUS SAMPLE t8a DOUT Hi-Z REF D11 D10 D9 D8 D7 D6 D5 D4 D3 HOLD t8 DOUT REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D2 D1 D0 Hi-Z REF t0 SAMPLE HOLD t5 2 3 4 5 6 7 8 9 10 11 12 13 14 t7 15 16 1 2 SCK t1 CONV t1 NAP SLEEP t12 VREF t11 REFRDY NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD. 1402 TD02 SCK t8 t10 DOUT W UW REFRDY BIT + 12-BIT DATA WORD tCONV tTHROUGHPUT 1402 TD01 Nap Mode and Sleep Mode Waveforms SCK to DOUT Delay SCK VIH VIH t9 VOH VOL 90% DOUT 1402 TD03 10% 9 LTC1402 APPLICATIONS INFORMATION DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1402 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and AIN– inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1402 inputs can be driven directly. As source impedance increases, so will acquisition time (see Figure 1). For minimum acquisition time with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 50ns for full throughput rate). 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 10 ± 5V ACQUISITION TIME (ns) 5V 100 1k 10k SOURCE RESISTANCE (Ω) 100k 1402 F01 Figure 1. Acquisition Time vs Source Resistance in Bipolar and Unipolar Modes CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The 10 U W U U second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1402 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical, and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1402. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT®1206: 60MHz Current Feedback Amplifier with Shutdown Pin (Amplifier Draws 200µA While in Shutdown). ± 5V to ± 15V supplies. Distortion is – 80dB to 1MHz (2VP-P into 30Ω). Good for AC applications. Dual available with shutdown as LT1207. Output swings to within 2VBE of the supply rails. LT1223: 100MHz Video Current Feedback Amplifier. 6mA supply current. ± 5V to ± 15V supplies. Low distortion at frequencies above 400kHz. Low noise. Good for AC applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current; has shutdown pin (draws 120µA while in shutdown). ± 5V to ± 15V supplies. Lowest distortion (– 92dB) at frequencies above 400kHz. Low noise. Best for AC applications. LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. ± 2V to ± 15V supplies. Low noise. Good AC specifications, 6mA supply current each amplifier. LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. ± 5V to ± 15V supplies. Good AC and DC specifications. 70ns settling to 0.5LSB. LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply current. Good AC and DC specifications. 60ns settling to 0.5LSB. LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op Amps. 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. LinearView is a trademark of Linear Technology Corporation. LTC1402 APPLICATIONS INFORMATION LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies. Very high AVOL, 500µV offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ± 15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are – 93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback Amplifier. 5V to ± 5V supplies. Distortion is – 86dB to 100kHz and – 77dB to 1MHz with ± 5V supplies (2VP-P into 500 Ω ). Excellent part for fast AC applications with ± 5V supplies. INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1402 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 80MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 2 shows a 68pF capacitor from AIN+ to ground and a 51Ω source resistor to limit the input bandwidth to 47MHz. The 68pF capacitor also acts as a charge reservoir for the input sample-andhold and isolates the ADC input from sampling glitchsensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much –5V ANALOG INPUT 51Ω 68pF 3 4 2 5 10µF 6 7 AIN+ AIN– AGND1 LTC1402 VREF AGND2 GAIN 1402 F02 U W U U Figure 2. RC Input Filter less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. Figure 3 shows a simple implementation using an LTC1560-1, a fifth order elliptic continuous-time 1MHz filter. 1 2 3 4 0.1µF LTC1560-1 8 7 6 5 3 4 2 5 5V 0.1µF 10µF 6 7 AIN+ AIN– AGND1 LTC1402 VREF AGND2 GAIN 1402 F03 VIN Figure 3. 1MHz Fifth Order Elliptic Lowpass Filter BIPOLAR AND UNIPOLAR INPUT RANGES The ± 2V bipolar input range of the LTC1402 is optimized for low noise and low distortion. Most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. The inputs of the LTC1402 may also be driven fully differential in bipolar mode with a single supply. Each input should not swing more than 2VP-P individually to get the best performance from single supply amplifiers. The 0V to 4V range is ideal for single ended input use with single supply applications. 11 LTC1402 APPLICATIONS INFORMATION INTERNAL REFERENCE The LTC1402 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.048V. It is connected internally to a reference amplifier, see Figure 4. The reference amplifier amplifies the voltage at the VREF pin by 2 to create the required internal reference voltage of 4.096V. This provides buffering for the high speed capacitive DAC. The reference amplifier output VREF, (Pin 5) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or a 10µF tantalum in parallel with a 0.1µF ceramic is recommended. The VREF pin can be driven with an external reference as shown in Figure 5a. The GAIN pin (Pin 7) is tied to the positive supply to disable the internal reference buffer. A DAC may also be used to drive VREF as shown in Figure 6. This is useful in applications where the peak input signal amplitude may vary. The input span of the LTC1402 4.096V 5 VREF + REFERENCE AMP 2.048V BANGAP REFERENCE – 10µF 7 GAIN 6 AGND2 64k 64k 10µF 6 1402 F04 Figure 4. LTC1402 Reference Circuit 5V ANALOG INPUT 3 AIN+ ANALOG INPUT VIN LT1019-2.5 VOUT 4 AIN– LTC1402 5 10µF 6 VREF AGND2 5V 7 GAIN 1402 F04a Figure 5a. Using the LT1019-2.5 as an External Reference 12 U W U U ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1402 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed after a reference adjustment. DIFFERENTIAL INPUTS The LTC1402 has a unique differential sample-and-hold circuit that allows inputs from –2.5V to 5V. The ADC will always convert the difference of AIN+ – AIN– independent of the common mode voltage. The common mode rejection holds up at extremely high frequencies, see Figure 7. The only requirement is that both inputs not exceed – 2.5V or 5V. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage. However, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Figure 5b shows the use of bipolar mode with single 5V supply. 5V VIN 2.5V ± 2.048V 2.5V 10µF 5 VREF 3 AIN+ AIN– LTC1402 BIP 8 5V VIN LT1019-2.5 4 AGND2 VSS 14 7 GAIN 1402 F04a Figure 5b. Bipolar Mode with Single Supply 3 AIN+ AIN– LTC1402 4 LTC1451 10µF 5 VREF 6 AGND2 5V 7 GAIN 1402 F06 Figure 6. Driving VREF with a 12 Bit, VOUT DAC LTC1402 APPLICATIONS INFORMATION 0 –10 – 20 AMPLITUDE (dB) – 30 – 40 – 50 – 60 –70 0.1 1 10 100 FREQUENCY (MHz) 1000 1402 F07 Figure 7. CMRR vs Input Frequency INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a voltage span that equals the difference between the voltage at the reference buffer output VREF at Pin 5, and the voltage at the reference ground AGND2 at Pin 6. The external reference voltage may have any value between 2V and 5V. The internal ADC is referenced to these two points. If you use an external reference, tie the GAIN (Pin 7) to AVDD (Pin 1) to disable the internal reference, and connect the external reference between VREF (Pin 5) and AGND2 (Pin 6). If you cut the reference voltage in half by halving the gain of the reference buffer with the GAIN (Pin 7) tied to VREF (Pin 5), the input span also cuts in half. In bipolar mode, the differential input range changes from ±2.048V to ±1.024V, when the reference is cut in half. In unipolar mode, the differential input range changes from 0V4.096V to 0V-2.048V, for the same reference cut in half. Note that in both unipolar and bipolar modes, the input range pivots around 0V with changing reference voltage. AGND2 (Pin 6) has no direct effect on the ADC offset voltage, it only affects input voltage span. Any external offsetting voltages must be applied through the AIN+ and AIN– inputs, as shown in Figure 10b. SEVERAL LTC1402 ADCs MAY SHARE ONE EXTERNAL REFERENCE Figure 8 shows how several ADCs can share a single common external reference. The VREF (Pin 5) and AGND2 (Pin 6) of several LTC1402 ADCs can be tied together to share the same external reference in a data acquisition system. Tie GAIN (Pin 7) to AVDD at each ADC to disable U W U U all the internal references. When AGND2 (Pin 6) is tied to the external ground plane, it sources 2.7mA ±30% typically; approximately 2mA are sourced through an internal equivalent 2k resistance tied to the VREF (Pin 5) at 4.096V and the remaining 0.7mA supply the internal reference ground. The VREF (Pin 5) equivalent input resistance is the same 2k tied to AGND2 (Pin 6). When you bus a common reference voltage to several LTC1402 ADCs, you need to keep PC board track resistance low to avoid reference voltage attenuation at each ADC. For example, 0.5Ω of track resistance to Pins 5 or 6 causes 0.025% of reference voltage and input range reduction. Figure 8 shows optional buffer amplifiers at each ADC to eliminate resistive voltage drops from the common external reference to each ADC. Figure 8 shows 10µF bypass capacitors tied to the common analog ground plane, at VREF (Pin 5) and AGND2 (Pin 6), wired closely to each ADC to eliminate crosstalk of internal ADC glitch currents from one ADC to another. The 10µF bypass capacitors are recommended whether you drive Pins 5 and 6 with amplifiers, or with copper traces 3 1/2 LT1368CS8 5V 6 5 – + 8 7 5 VREF ANALOG INPUTS AIN+ AIN– LTC1402 2 10µF 1/2 LT1368CS8 2 3 – + 4 –5V 5V 4.096V 1 10µF 6 AGND2 7 GAIN • • • 3 AIN+ AIN– LTC1402 5 VREF 5V 1/2 LT1368CS8 10k 1k 0.1µF 5V 6 5 – + 8 7 ANALOG INPUTS 2 10µF 1/2 LT1368CS8 2 3 – + 4 –5V 5V 1 10µF 6 AGND2 LT1634AI-4.096 7 GAIN 1402 F08 Figure 8. Several LTC1402 ADCs Can Share a Single External Reference 13 LTC1402 APPLICATIONS INFORMATION more than 0.25 inch long to the common reference. You may also choose to tie AGND2 (Pin 6) directly to a solid analog ground plane and eliminate all the 10µF capacitors at this pin. The external reference source needs to have enough output drive current for the 2kΩ load at each ADC. FULL-SCALE AND OFFSET ADJUSTMENT Figure 9 shows the ideal input/output characteristics for the LTC1402 in bipolar mode and unipolar mode. Figure 10a shows the components required for full-scale error adjustment. Figure 10b includes the components for offset and full-scale adjustment. 011...111 011...110 111...111 111...110 BIPOLAR OUTPUT CODE 011...101 111...101 100...010 100...001 100...000 – (FS – 1LSB) INPUT VOLTAGE (V) 1402 F09 000...010 000...001 000...000 FS – 1LSB Figure 9. LTC1402 Transfer Characteristic Adjustment in Bipolar Mode with Pin 8 Held High The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at DOUT is two’s complement binary with 1LSB = FS – (– FS)/4096 = 4.096V/4096 = 1.0mV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before fullscale error. In Figure 10b, zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset error, apply – 0.5mV (i.e., – 0.5LSB) to AIN+ and adjust the offset at the AIN– input using R8 until the output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment in Figures 10a and 10b, apply an input voltage of 2.0465V (FS – 1.5LSB) to AIN+ and adjust R5 until the output code flickers between 0111 1111 1110 and 0111 1111 1111. 14 U W U U Adjustment in Unipolar Mode with Pin 8 Held Low The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at DOUT is binary with 1LSB = FS/4096 = 4.096V/4096 = 1.0mV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. In Figure 10b, zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset error apply – 0.5mV (i.e., – 0.5LSB) to AIN+ and adjust the offset at the AIN– input using R8 until the output code flickers between R1 51Ω ANALOG INPUT 0V TO 4.096V OR ± 2.048V R3 51Ω 3 AIN+ R2 39k 4 AIN– S/H LTC1402 UNIPOLAR OUTPUT CODE 2.048V 5 VREF R4 470k 10µF R5 500Ω 7 GAIN 6 AGND2 REFERENCE AMP BANGAP REFERENCE 64k 64k 1402 F010a Figure 10a. Full-Scale Adjustment Circuit with ± 10LSB Range 5V R1 51Ω ANALOG INPUT 0V TO 4.096V OR ± 2.048V 5V OFFSET R8 ADJ 10k R3 51Ω R7 7.5k 5 VREF R4 470k 10µF R5 FULL-SCALE ADJ 500Ω 7 GAIN 6 AGND2 1402 F010b R6 24k 3 A + IN R2 24k 4 AIN– S/H LTC1402 2.048V REFERENCE AMP BANGAP REFERENCE 64k 64k Figure 10b. Offset and Full-Scale Adjustment Circuits with ±10LSB Range LTC1402 APPLICATIONS INFORMATION 0000 0000 0000 and 0000 0000 0001. For full-scale adjustment in Figures 10a and 10b, apply an input voltage of 2.0465V (FS – 1.5LSBs) to AIN+ and adjust R5 until the output code flickers between 1111 1111 1110 and 1111 1111 1111. BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1402, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all other analog grounds should be connected directly to an analog ground plane. Pin 9 (OGND) should be connected near Pin13 (DGND), where the analog ground plane ties to the logic system ground. The VREF bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane, see Figure 11. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1402 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– leads will be rejected by the input CMRR. The AIN– input can be used as a ground sense for the AIN+ input; the LTC1402 will hold and convert the difference voltage between AIN+ and AIN– . The leads to AIN+ (Pin 3) and AIN– (Pin 4) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN– traces should be run side-byside to cancel noise coupling. SUPPLY BYPASSING High quality, low series resistance 10µF ceramic bypass capacitors should be used at the VDD and VREF pins. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively, 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. POWER-DOWN MODES Upon power-up, the LTC1402 is initialized to the active state and is ready for conversion. The Nap and Sleep Mode waveforms show the power-down modes for the LTC1402. The SCK and CONV inputs control the power-down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1402 in Nap mode and the power drain drops from 90mW to 3 ANALOG INPUT CIRCUITRY AIN+ AIN– VREF 5 10µF AGND2 6 VSS 4 + – ANALOG GROUND PLANE Figure 11. Power Supply Grounding Practice U W U U OVDD LTC1402 AGND1 2 AVDD DVDD DGND 1 12 10µF 13 DOUT OGND 9 12 10 3V TO 5V DIGITAL SYSTEM SYSTEM GROUND 1402 F11 14 10µF 15 LTC1402 APPLICATIONS INFORMATION 15mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1402 for service very quickly, and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1402 in Sleep mode and the power drain drops from 90mW to 10µW. One or more rising edges at SCK wake up the LTC1402 for operation. The internal reference (VREF) takes 2ms to slew and settle with a 10µF load, and the REFREADY bit in the DOUT stream takes an additional 10ms to go high after the reference output Pin 5 (VREF) has finished slewing. Note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. Figure 12 shows the power consumption versus the conversion rate. Note that, for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. 100 VDD CURRENT DUAL ± 5V VDD CURRENT SINGLE 5V VDD CURRENT NAP MODE VDD CURRENT SLEEP MODE VSS CURRENT SINGLE 5V 10 SUPPLY CURRENT (mA) 1 0.1 0.01 VSS CURRENT DUAL ± 5V 0.001 0.01 0.1 1 SAMPLE RATE (MHz) 10 1402 F12 Figure 12. Power Consumption vs Sample Rate in Normal Mode, Nap Mode and Sleep Mode DIGITAL INTERFACE The LTC1402 has a 3-wire SPI (Serial Protocol Interface) interface. The SCK and CONV inputs and DOUT output implement this interface. The SCK and CONV inputs are TTL compatible and also accept swings from 3V or 5V logic. The amplitude of DOUT can easily produce 5V logic or 3V logic swings by tying the independent output supply OVDD (Pin 11) to the same supply as system logic. A detailed description of the three serial port signals follows. 16 U W U U CONV at Pin 16 The rising edge of CONV starts a conversion but subsequent rising edges at CONV, during the following 14 SCK cycles of conversion, are ignored by the LTC1402. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC1402 and then buffer this signal with the appropriate number of inverters to drive the frame sync input of the processor serial port. It is good practice to drive the LTC1402 CONV input first to avoid digital noise interference during the sample-to-hold transition triggered by CONV at the start of conversion. Another point to consider is the level of jitter in the CONV signal if the input signals have fast transients or sinewaves. Some processors can be programmed to generate a convenient frame sync pulse at their serial port, but often this signal is derived from a jittery processor phase locked loop clock multiplier. This is true even if a low jitter crystal clock is the reference for the processor clock multiplier. SCK at Pin 15 The rising edge of SCK advances the conversion process and also udpates each bit in the DOUT data stream. After CONV rises, the second rising edge of SCK sends out the REFREADY bit. Subsequent edges send out the 12 data bits, with the MSB sent first. A simple approach is to generate SCK to drive the LTC1402 and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. The rising edge of SCK is guaranteed to coincide with stable data at DOUT. It is good practice to drive the LTC1402 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. DOUT at Pin 10 Upon power-up, the DOUT output is automatically reset to the high impedance state. The DOUT output remains in high impedance until a new conversion is started. DOUT sends out 13 bits in the output data stream after the second rising edge of SCK after the start of conversion with the rising LTC1402 APPLICATIONS INFORMATION edge of CONV. Please note the delay specification from SCK to a valid DOUT. DOUT is always guaranteed to be valid by the next rising edge of SCK. DIGITAL JITTER AT CONV (PIN 16) In high speed applications, where high amplitude sinewaves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement easily. The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. As shown in the interface circuit examples, the LTC1402’s SCK and CONV inputs should be driven first with digital buffers used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter, even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low 5V OVDD 11 10 74ACT04 CONV LTC1402 SCK DOUT OGND 16 15 10 9 13 G 12 11 14 SRCLR RCK SRCK SER QA QB QC QE QF QG QH CONV CLK 10 SRCLR 12 11 3-WIRE SERIAL INTERFACE LINK 14 13 RCK SRCK SER G QA QB QC QE QF QG QH QH′ 74HC595 QD 15 1 2 3 4 5 6 7 9 1402 F13 Figure 13. Serial to Parallel Interface U W U U speed crystal (i.e., 10MHz) to generated a fast, but jittery, phase locked loop system clock (i.e., 40MHz). The jitter, in these PLL-generated high speed clocks, can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP’s master clock. SERIAL TO PARALLEL CONVERSION You can take advantage of the serial interface of the LTC1402 in a parallel data system to minimize bus wiring congestion in the PC board layout. Figure 13 shows an example of this interface. It is best to send the SCK and CONV signals to the LTC1402, and then bus them together across the board to avoid excessive time skew among the three signals. It is usually not necessary to buffer DOUT, if the PC track is not too long. Buffering SCK and CONV prevents jitter from corrupting these signals. The relative phase between SCK and CONV affects the position of the parallel word at the output of the 74HC595. The position of the output word in Figure 13 assumes 16 clocks between each CONV rising edge, and the CONV pulse is one clock wide. 15 1 2 3 4 5 6 7 9 D0 D1 D2 D3 D4 D5 D6 74HC595 QD QH′ D7 D8 D9 D10 D11 REFRDY 17 LTC1402 APPLICATIONS INFORMATION HARDWARE INTERFACE TO TMS320C54x The LTC1402 is a serial output ADC whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 14 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC’s serial data can be collected in two alternating 1kB segments, in real time, at the full 2.2Msps conversion rate of the LTC1402. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse, and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1402 may be added to drive long tracks to the DSP to prevent corruption of the signal to LTC1402. This configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs, and termination resistors at the DSP may be needed to match the characteristic impedance of very long transmission lines. If you need to terminate the DOUT transmission line, buffer it first with one or two 74ACxx gates. The TTL threshold inputs of the DSP port respond properly to the 2.5V swing of the terminated transmission lines. The OVDD supply output driver supply voltage can be driven directly from the DSP. OVDD CONV LTC1402 SCK DOUT OGND 11 16 15 10 9 CONV CLK 3-WIRE SERIAL INTERFACELINK REF B11 B10 Figure 14. DSP Serial Interface to TMS320C54x 18 U W U U 5V VCC BFSR TMS320C54x BCLKR BDR 1402 F14 LTC1402 APPLICATIONS INFORMATION ; *************************************************************************** ; Files: BSP2KB.ASM -> ; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402 ; first element at 1024, last element at 1023, two middle elements at 2047 and 0000 ; bipolar mode ; *************************************************************************** .width 160 .length 110 .title “sineb0 BSP in auto buffer mode” .mmregs .setsect “.text”, 0x500,0 ;Set address of executable .setsect “vectors”, 0x180,0 ;Set address of incoming 1402 data .setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing .setsect “result”, 0x1800,0 ;Set address of result for clearing .text ;.text marks start of code start: ;Make sure /PWRDWN is low at J1-9 to turn off AC01 adc tim=#0fh prd=#0fh tcr = #10h ; stop timer tspc = #0h ; stop TDM serial port to AC01 pmst = #01a0h ; set up iptr. Processor Mode STatus register sp = #0700h ; init stack pointer. dp = #0 ; data page ar2 = #1800h ; pointer to computed receive buffer. ar3 = #0800h ; pointer to Buffered Serial Port receive buffer ar4 = #0h ; reset record counter call sineinit ; Double clutch the initialization to insure a proper sinepeek: ; insert debugger break here to view results call sineinit ; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. wait goto wait ; ————————Buffered Receive Interrupt Routine ————————— breceive: ifr = #10h ; clear interrupt flags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h) ; turn on halt for second half (bspce(bit15)) return_enable ; ———————mask and shift input data after 2k buffer is full——bufull: b = *ar3+ 1)|((Format & 2)