LT1024AMD

L T1024 Dual, Matched Picoampere, Microvolt Input, Low Noise Op Amp DESCRIPTIO The LT ®1024 dual, matched internally compensated universal precision operational amplifier can be used in practically all precision applications requiring multiple op amps. The LT1024 combines picoampere bias currents (which are maintained over the full –55°C to 125°C temperature range), microvolt offset voltage (and low drift with time and temperature), low voltage and current noise and low power dissipation. Extremely high common mode and power supply rejection ratios, practically immeasurable warm-up drift, and the ability to deliver 5mA load current with a voltage gain of a million, round out the LT1024’s superb precision specifications. Tight matching is guaranteed on offset voltage, noninverting bias currents and common mode and power supply rejections. The all-around excellence of the LT1024 eliminates the necessity of the time-consuming error analysis procedure of precision system design in many dual applications; the LT1024 can be stocked as the universal dual op amp in the 14-pin DIP configuration. For a single op amp with similar specifications, see the LT1012 data sheet; for a single supply dual precision op amp in the 8-pin configuration, see the LT1013 data sheet. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ Guaranteed Offset Voltage: 50µV Max Guaranteed Bias Current: 25°C: 120pA Max –55°C to 125°C: 700pA Max Guaranteed Drift: 1.5µV/°C Max Low Noise, 0.1Hz to 10Hz: 0.5µVP-P Guaranteed Supply Current: 600µA Max Guaranteed CMRR: 112dB Min Guaranteed PSRR: 112dB Min Guaranteed Voltage Gain with 5mA Load Current Guaranteed Matching Characteristics APPLICATIO S ■ ■ ■ ■ ■ ■ ■ ■ Strain Gauge Signal Conditioner Dual Limit Precision Threshold Detection Charge Integrators Wide Dynamic Range Logarithmic Amplifiers Light Meters Low Frequency Active Filters Standard Cell Buffers Thermocouple Amplifiers , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO R5 2.2k † R1* 100k 3 R2 10k Two Op Amp Instrumentation Amplifier R4 100k Input Bias Current vs Temperature 100 INPUT BIAS CURRENT (pA) 50 UNDERCANCELLED UNIT 0 OVERCANCELLED UNIT –50 – 1/2 LT1024 13 R3 10k 10 – 1/2 LT1024 6 OUTPUT – INPUTS 4 + 11 + GAIN = R4 1 + 1 R3 2 + ( R2 + R3 ) + R2R5R3 R1 R4 + TYPICAL PERFORMANCE: OFFSET VOLTAGE = 20µV BIAS CURRENT = ±30pA OFFSET CURRENT = 30pA –100 ~ 100 –150 –50 –25 * TRIM FOR COMMON-MODE REJECTION † TRIM FOR GAIN LT1024 • TA01 U U U 50 25 0 75 TEMPERATURE (°C) 100 125 LTC1024 • TA02 1024fa 1 LT1024 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW NULL (A) NULL (A) –IN (A) +IN (A) V – (B) OUT (B) V + (B) 1 2 3 4 5 6 7 – +A B 14 V + (A) 13 OUT (A) 12 V – (A) + – 11 +IN (B) 10 –IN (B) 9 8 NULL (B) NULL (B) Supply Voltage ...................................................... ± 20V Differential Input Current (Note 2) ...................... ±10mA Input Voltage ......................................................... ± 20V Output Short Circuit Duration .......................... Indefinite Operating Temperature Range LT1024AM/LT1024M (OBSOLETE).....–55°C to 125°C LT1024AC/LT1024C ................................ 0°C to 70°C Storage Temperature Range ................. –65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LT1024ACN LT1024CN N PACKAGE 14-PIN PDIP TJMAX = 100°C, θJA = 100°C/W, θJC = 60°C/W (N) NOTE: DEVICE MAY BE OPERATED EVEN IF INSERTION IS REVERSED; THIS IS DUE TO INHERENT SYMMETRY OF PIN LOCATIONS OF AMPLIFIERS A AND B (NOTE 3) D PACKAGE 14-PIN SIDE BRAZED (HERMETIC) TJMAX = 150°C, θJA = 100°C/W, θJC = 60°C/W (D) ORDER PART NUMBER LT1024AMD LT1024MD OBSOLETE PACKAGE Consider the N14 Package as an Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS Individual Amplifiers. VS = ± 15V, VCM = 0V, TA = 25°C unless otherwise noted. SYMBOL PARAMETER VOS Input Offset Voltage Long Term Input Offset Voltage Stability IOS IB en en in AVOL CMRR PSRR Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Large-Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range VOUT Output Voltage Swing Slew Rate IS Supply Current per Amplifier RL = 10kΩ 0.1Hz to 10Hz fO = 10Hz (Note 4) fO = 1000Hz (Note 4) fO = 10Hz VOUT = ±12V, RL ≥ 10kΩ VOUT = ±10V, RL ≥ 2kΩ VCM = ±13.5V VS = ± 2V to ±20V 250 150 112 112 ±13.5 ±13 0.1 CONDITIONS LT1O24AM/LT1O24AC MIN TYP MAX 15 0.3 20 ± 25 0.5 17 14 20 2000 1000 132 132 ±14.0 ±14 0.2 380 600 180 100 108 108 ±13.5 ±13 0.1 33 24 100 ±120 50 LT1024M/LT1O24C MIN TYP MAX 20 0.3 25 ± 30 0.5 17 14 20 2000 1000 132 132 ±14.0 ±14 0.2 380 700 33 24 180 ± 200 100 UNITS µV µV/month pA pA µVP-P nV/√Hz nV/√Hz fA/√Hz V/mV V/mV dB dB V V V/µs µA 1024fa 2 U W U U WW W L T1024 ELECTRICAL CHARACTERISTICS Matching Specifications. VS = ± 15V, VCM = 0V, TA = 25°C unless otherwise noted. SYMBOL PARAMETER Input Offset Voltage Match IB + CONDITIONS LT1024AM/LT1024AC MIN TYP MAX 20 ±30 30 75 ±150 150 LT1O24M /LT1O24C MIN TYP MAX 25 ±40 30 106 106 134 132 132 150 150 ±250 300 UNITS µV pA pA dB dB dB Average Noninverting Bias Current Noninverting Offset Current Common Mode Rejection Ratio Match Power Supply Rejection Ratio Match Channel Separation VCM = ±13.5V VS = ±2V to 20V f ≤ 10Hz (Note 4) 110 110 134 IOS+ ∆CMRR ∆PSRR 132 132 150 Individual Amplifiers. The ● denotes the specifications which apply over the full operating temperature range of 0°C ≤ TA = 70°C for the LT1024AC and LT1024C; – 55°C ≤ TA ≤ 125°C for the LT1024AM and LT1024M. VS = ± 15V, VCM = 0V, unless otherwise noted. SYMBOL PARAMETER VOS Input Offset Voltage Average Temperature Coefficient of Input Offset Voltage IOS Input Offset Current Average Temperature Coefficient of Input Offset Current IB Input Bias Current Average Temperature Coefficient of Input Bias Current AVOL CMRR PSRR Large-Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range VOUT IS Output Voltage Swing Supply Current RL = 10kΩ 0°C to 70°C –55°C to 125°C 0°C to 70°C –55°C to 125°C VOUT = ±12V, RL ≥ 10kΩ VOUT = ±10V, RL ≥ 2kΩ VCM = ±13.5V VS = ±2.5V to ±18V 0°C to 70°C –55°C to 125°C CONDITIONS 0°C to 70°C –55°C to 125°C ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● LT1024AM/LT1024AC MIN TYP MAX 30 40 0.25 40 80 0.5 ± 40 ±100 0.4 1 150 100 108 108 ±13.5 ±13 ±14 400 800 1000 600 128 128 120 200 1.5 250 350 2.5 ± 250 ±700 3 6 MIN LT1024M/LT1024C TYP MAX 35 50 0.3 50 100 0.7 ± 50 ± 200 0.5 2 200 300 2.0 300 500 3 ± 400 ±1300 4 12 UNITS µV µV µV/°C pA pA pA/°C pA pA pA/°C pA/°C V/mV V/mV dB dB V 150 100 106 106 ±13.5 ±13 1000 600 128 128 ±14 400 900 V µA 1024fa 3 LT1024 Matching Specifications. The ● denotes the specifications which apply over the temperature range of 0°C ≤ TA = 70°C for the LT1024AC and LT1024C; – 55°C ≤ TA ≤ 125°C for the LT1024AM and LT1024M, VS = ± 15V, VCM = 0V unless otherwise noted. SYMBOL PARAMETER Input Offset Voltage Match Input Offset Voltage Tracking IB + IOS+ ∆CMRR ∆PSRR Average Noninverting Bias Current Noninverting Offset Current 0°C to 70°C –55°C to 125°C 0°C to 70°C –55°C to 125°C CONDITIONS 0°C to 70°C –55°C to 125°C ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS LT1024AM/LT1024AC MIN TYP MAX 35 50 0.3 ± 40 ±100 40 80 106 106 128 128 170 280 2 ± 300 ± 800 300 800 MIN LT1024M/LT1024C TYP MAX 45 70 0.4 ± 50 ± 200 50 150 300 500 3.5 ± 500 ±1400 500 1500 UNITS µV µV µV/°C pA pA pA pA dB dB Common Mode Rejection Ratio Match VCM = ± 13.5V Power Supply Rejection Ratio Match VS = ± 2.5V to ±18V 104 104 128 128 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Differential input voltages greater than 1V will cause excessive current to flow through the input protection diodes unless limiting resistance is used. Note 3: The V + supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). The V – supply terminals are both connected to the common substrate and must be tied to the same voltage. Both V – pins should be used. Note 4: This parameter is tested on a sample basis only. Optional Offset Nulling Circuit V+ 5k TO 100k POT 2 (9) 14 (7) LT1024 13 (6) OUTPUT 1 (8) 3 (10) 4 (11) – 1/2 + 12 (5) V– INPUT OFFSET VOLTAGE CAN BE ADJUSTED OVER A ±800µV RANGE WITH A 5k TO 100k POTENTIOMETER LT1024 • EC01 TYPICAL PERFOR A CE CHARACTERISTICS Offset Voltage vs Source Resistance (Balanced or Unbalanced) 1000 VS = ±15V INPUT OFFSET VOLTAGE (µV) 100 – 55°C TO 125°C 25°C 10 INPUT OFFSET CURRENT (pA) 1 1k 3k 10k 30k 100k 300k 1M SOURCE RESISTANCE (Ω) 3M 10M LT1024 • TPC01 4 UW Input Offset Current vs Temperature 60 50 40 30 20 10 0 – 50 –25 VS = ±15V VCM = 0V 50 25 75 0 TEMPERATURE (°C) 100 125 LT1024 • TPC02 1024fa L T1024 TYPICAL PERFOR A CE CHARACTERISTICS Input Bias Current Over Common Mode Range 60 40 CHANGE IN OFFSET VOLTAGE (µV) VS = ±15V TA = 25°C INPUT BIAS CURRENT (pA) DEVICE WITH POSITIVE INPUT CURRENT RIN CM = 2 x 10 Ω DEVICE WITH NEGATIVE INPUT CURRENT 12 OFFSET VOLTAGE (µV) 20 0 –20 IB –40 VCM – 60 –15 – + 10 –5 0 5 –10 COMMON MODE INPUT VOLTAGE (V) Supply Current vs Supply Voltage per Amplifier 500 NOISE VOLTAGE 400nV/DIVISION VOLTAGE NOISE DENSITY (nV/√Hz) CURRENT NOISE DENSITY (fA/√Hz) SUPPLY CURRENT (µA) 400 25°C 125°C –55°C 300 0 ± 10 ± 15 ±5 SUPPLY VOLTAGE (V) Total Noise vs Source Resistance 10.0 COMMON MODE REJECTION RATIO (dB) TOTAL NOISE DENSITY (µV/√Hz) AT 10Hz AT 1kHz 120 100 80 60 40 20 0 1 VS = ±15V TA = 25°C 10 10k 1k 100 FREQUENCY (Hz) 100k 1M CMRR MATCH (∆CMRR) POWER SUPPLY REJECTION RATIO (dB) TA = 25°C VS = ± 2V TO ± 20V 1.0 R R – + RS = 2R 0.1 AT 10Hz AT 1kHz 0.01 102 RESISTOR NOISE ONLY 108 103 104 105 106 107 SOURCE RESISTANCE (Ω) UW 15 LT1024 • TPC03 LT1024 • TPC06 LT1024 • TPC09 Warm-Up Drift 5 60 VS = ±15V TA = 25°C 40 20 Offset Voltage Drift and Tracking with Temperatures of Representative Units VS = ±15V 2 1 1 0 –20 –40 –60 –50 –25 2 2 1 INDIVIDUAL AMPLIFIERS 2 TRACKING (MATCH DRIFT) 50 25 75 0 TEMPERATURE (°C) 100 125 4 3 2 1 0 0 1 3 4 2 TIME AFTER POWER ON (MINUTES) 5 LT1024 • TPC04 LT1024 • TPC05 0.1Hz to 10Hz Noise TA = 25°C VS ± 2V TO ± 20V Noise Spectrum 1000 TA = 25°C VS ± 2 TO ± 20V 100 CURRENT NOISE VOLTAGE NOISE 10 1/f CORNER 2.5Hz 1/f CORNER 120Hz 1 1 10 100 FREQUENCY (Hz) 1000 LT1024 • TPC08 ± 20 0 2 6 4 TIME (SECONDS) 8 10 LT1024 • TPC07 Common Mode Rejection and CMRR Match vs Frequency 140 140 120 100 80 60 40 Power Supply Rejection vs Frequency VS = ±15V TA = 25°C POSITIVE SUPPLY NEGATIVE SUPPLY 20 0.1 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M LT1024 • TPC10 LT1024 • TPC11 1024fa 5 LT1024 TYPICAL PERFOR A CE CHARACTERISTICS Channel Separation vs Frequency 160 150 CHANNEL SEPARATION (dB) RS = 10Ω 140 130 120 110 RS = 1k 100 90 80 100 1k 10k 100k FREQUENCY (Hz) 1M LT1024 • TPC12 RS = 100Ω VOLTAGE GAIN (dB) Gain, Phase Shift vs Frequency 40 TA = 25°C VS = ±15V 30 PHASE GAIN (dB) VOLTAGE GAIN 20 GAIN 10 PHASE MARGIN = 70°C 0 –10 0.01 0.1 1 FREQUENCY (MHz) Small-Signal Transient Response 20mV/DIVISION 20mV/DIVISION 2V/DIVISION AV = + 1 CLOAD = 100pF 5µs/DIV 6 UW Voltage Gain vs Frequency VS = ±15V TA = 25°C 140 120 100 80 60 40 20 0 –20 0.01 0.1 1 VS = ±15V TA = 25°C 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) LT1024 • TPC13 Voltage Gain vs Load Resistance 100 10M VS = ± 15V V0 = ± 10V – 55°C 25°C 1M 125°C 120 PHASE SHIFT (DEGREES) 3M 140 160 300k 180 200 10 LT1024 • TPC14 100k 1 2 5 10 LOAD RESISTANCE (kΩ) 20 LT1024 • TPC15 Small-Signal Transient Response Large-Signal Transient Response AV = + 1 CLOAD = 1000pF 5µs/DIV AV = + 1 20µs/DIV 1024fa L T1024 APPLICATIO S I FOR ATIO The LT1024 may be inserted directly into OP-10, OP-207 or 0P227 sockets with or without removal of external nulling components. The LT1024 is specified over a wide range of power supply voltages from ± 2V to ±18V. Operation with lower supplies is possible down to ±1.2V (two NiCad batteries). Advantages of Matched Dual Op Amps In many applications, the performance of a system depends on the matching between two operational amplifiers rather than the individual characteristics of the two op amps. Two or three op amp instrumentation amplifiers, tracking voltage references, and low drift active filters are some of the circuits requiring matching between two op amps. The well-known triple op amp configuration illustrates these concepts. Output offset is a function of the difference between the offsets of the two halves of the LT1024. This error cancellation principle holds for a considerable number of input-referred parameters in addition to offset voltage and its drift with temperature. Input bias current will be the average of the two noninverting input currents (IB + ). The difference between Three Op Amp Instrumentation Amplifier 15V –INPUT 4 R4 100Ω 1% R1 10k 1% 15V R3 2.1k 1% R8 200Ω 15V 10 R2 10k 1% 6 R5 100Ω 1% R7 9.76k 1% R9 500Ω C1 100pF R10 100k 2 7 LT1037 3 6 OUTPUT R6 10k 1% 3 A 1/2 LT1024 + – 14 13 12 –15V – + 7 +INPUT 11 B 1/2 LT1024 5 –15V TRIM R8 FOR GAIN TRIM R9 FOR DC COMMON MODE REJECTION TRIM R10 FOR AC COMMON MODE REJECTION U these two currents (IOS +) is the offset current of the instrumentation amplifier. Common mode and power supply rejections will be dependent only on the match between the two amplifiers (assuming perfect resistor matching). The concepts of common mode and power supply rejection ratio match (∆CMRR and ∆PSRR) are best demonstrated with a numerical example: Assume CMRRA = +1.0µV/V or 120dB and CMRRB = + 0.5µV/V or 126dB, then ∆CMRR = 0.5µV/V or 126dB if CMRRB = – 0.5µV/V, which is still 126dB, then ∆CMRR = 1.5µV/V or 116.5dB. Typical performance of the instrumentation amplifier: Input offset voltage = 25µV. Input bias current = 30pA. Input resistance = 1012 Ω. Input offset current = 30pA. Input noise = 0.7µVP-P. Power bandwidth (VO = ±10V) = 80kHz. Clearly, the LT1024, by specifying and guaranteeing all of these matching parameters, can significantly improve the performance of matching dependent circuits. – + 4 –15V GAIN = 1000 LT1024 • AI01 W UU 1024fa 7 LT1024 APPLICATIO S I FOR ATIO Achieving Picoampere/Microvolt Performance In order to realize the picoampere/microvolt level accuracy of the LT1024, proper care must be exercised. For example, leakage currents in circuitry external to the op amp can significantly degrade performance. High quality insulation should be used (e.g., Teflon™, Kel-F); cleaning of all insulating surfaces to remove fluxes and other residues will probably be required. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: in inverting configurations, the guard ring should be tied to ground; in noninverting connections, to the inverting input. Guarding both sides of the printed circuit board is required. Bulk leakage reduction depends on the guard ring width. Nanoampere level leakage into the offset trim terminals can affect offset voltage and drift with temperature. Teflon is a trademark of Dupont. Test Circuit for Offset Voltage and its Drift with Temperature R1 50k* 15V 14 (7) 3 (10) 4 (11) – LT1024 13 (6) V0 R2 100Ω* R3 50k* + 12 (5) –15V 8 U Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects, caused by temperature gradients across dissimilar metals at the contacts to the input terminals, can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short, and the two input leads should be as close together as possible and maintained at the same temperature. * RESISTORS MUST HAVE LOW THERMOELECTRIC POTENTIAL ** THIS CIRCUIT IS ALSO USED AS THE BURN-IN CONFIGURATION FOR THE LT1024. WITH SUPPLY VOLTAGES INCREASED TO ±20V, R1 = R3 = 20k, R2 = 200Ω, AV = 100 VO = 1000V0S LT1024 • AI02 1024fa W UU L T1024 APPLICATIO S I FOR ATIO Direct Pressure Transducer to Digital Output Signal Conditioner 15V 2N3904 330Ω TRANSDUCER ZERO 10k 28k 14k 1N4148 –5V 0.01µF 15V 14 13 LT1024 120k* 0.0047µF OUT B + – 12 –15V 4 50k GAIN TRIM 3 11 10µF –5V 2k ADJ –15V VIN LT137A OUT 620Ω + 10k 10k* *1% METAL FILM RESISTOR GATES = 74C00 **TRANSDUCER = BLH # DHF-100 PSI PRESSURE TRANSDUCER 0 – 100 PSI = 0 – 1000 COUNTS FULL-SCALE AT CIRCUIT OUTPUT U ~ fCLK ~ 10kHz 10k OUT A 15V 226k* 10 OUTPUT = fOUT A/fOUT B 6 10k D PRE 5 –15V 15V CLK 74C74 CLR Q Q W UU – + 7 LT1024 2N2979 100k 100k 2N3904 10k –15V LT1024 • AI03 –5V 1024fa 9 LT1024 SCHE ATIC DIAGRA TRIM 1 (8) 800Ω 800Ω 22k Q7 22k Q8 30pF Q5 Q6 Q16 4k Q13 Q11 Q23 –INPUT 3 (10) Q9 Q12 Q31 Q39 Q17 Q18 Q19 Q35 20k 3.3k 4.3k V– 12 (5) 4.8k 3.3k Q34 3.3k 320Ω 40Ω 330Ω s Q1 Q2 s s Q15 50k 1.5k J1 Q32 Q33 16k Q36 Q40 Q41 Q28 Q26 1.5k Q38 +INPUT 4 (11) Q10 10 W 1/2 LT1024 TRIM 2 (9) V+ 14 1.3k 4.2k Q20 Q29 Q22 Q25 1.5k Q43 Q21 Q27 Q37 s Q4 Q3 3k Q24 40Ω OUTPUT 13 (6) (7) Q14 Q30 100Ω 40Ω Q42 LT1024 * SD01 W 1024fa L T1024 PACKAGE DESCRIPTIO .008 – .015 (0.203 – 0.381) .300 (7.620) REF .125 (3.175) MIN .100 (2.54) BSC .054 (1.372) TYP D14 0801 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U D Package 14-Lead Side Brazed (Hermetic) (Reference LTC DWG # 05-08-1210) .760 (19.304) MAX 14 13 12 11 10 9 8 .005 (0.127) MIN .290 (7.366) TYP PIN NO. 1 IDENT 1 2 3 4 5 6 7 .020 – .060 (0.508 – 1.524) .485 (12.319) MAX .165 (4.191) MAX .015 – .023 (0.381 – 0.584) OBSOLETE PACKAGE 1024fa 11 LT1024 PACKAGE DESCRIPTIO .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) +.035 .325 –.015 .005 (0.125) .100 MIN (2.54) BSC ( +0.889 8.255 –0.381 ) INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) NOTE: 1. DIMENSIONS ARE RELATED PARTS PART NUMBER LT1884 DESCRIPTION Picoamp Input, Precision Op Amp COMMENTS Rail-to-Rail Output 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U N Package 14-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .770* (19.558) MAX 14 13 12 11 10 9 8 .255 ± .015* (6.477 ± 0.381) 1 .130 ± .005 (3.302 ± 0.127) .020 (0.508) MIN 2 3 4 5 6 7 .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .120 (3.048) MIN .018 ± .003 (0.457 ± 0.076) N14 1002 1024fa LW/TP 1002 1K REV A • PRINTED IN USA www.linear.com  LINEAR TECHNOLOGY CORPORATION 1988