LT1161IN

LT1161 Quad Protected High-Side MOSFET Driver FEATURES s s s s s s DESCRIPTION The LT1161 is a quad high-side gate driver allowing the use of low cost N-channel power MOSFETs for high-side switching applications. It has four independent switch channels, each containing a completely self-contained charge pump to fully enhance an N-channel MOSFET switch with no external components. Also included in each switch channel is a drain sense comparator that is used to sense switch current. When a preset current level is exceeded, the switch is turned off. The switch remains off for a period of time set by an external timing capacitor and then automatically attempts to restart. If the fault is still present, this cycle repeats until the fault is removed, thus protecting the MOSFET. The LT1161 has been specifically designed for harsh operating environments such as industrial, avionics, and automotive applications where poor supply regulation and/or transients may be present. The device will not sustain damage from supply voltages of –15V to 60V. s s s s Fully Enhances N-Channel MOSFET Switches 8V to 48V Power Supply Range Protected from – 15V to 60V Supply Transients Individual Short-Circuit Protection Individual Automatic Restart Timers Programmable Current Limit, Delay Time, and Auto-Restart Period Voltage-Limited Gate Drive Defaults to OFF State with Open Input Flowthrough Input to Output Pinout Available in 20-Lead DIP or SOL Package APPLICATIONS s s s s s Industrial Control Avionics Systems Automotive Switches Stepper Motor and DC Motor Control Electronic Circuit Breaker TYPICAL APPLICATION 24V CT 0.1µF 0.1µF 0.1µF 0.1µF RS 0.01Ω IRFZ34 + V+ T1 T2 T3 T4 IN1 IN2 IN3 IN4 GND GND LT1161 V+ DS1 G1 DS2 G2 DS3 G3 DS4 G4 50µF 50V 0.50 0.45 0.40 Switch Drop vs Load Current TOTAL DROP (V) 0.01Ω IRFZ34 0.01Ω IRFZ34 0.01Ω IRFZ34 LOAD #1 0.35 0.30 0.25 0.20 0.15 LOAD #2 INPUTS LOAD #3 0.10 0.05 0 0 1 3 2 LOAD CURRENT (A) 4 5 1161 TA01 LOAD #4 1161 F01 Figure 1. Protected Quad High-Side Switch U U U 1 LT1161 ABSOLUTE MAXIMUM RATINGS Supply Voltages (Pins 11, 20) ................... – 15V to 60V Input Voltages (Pins 3, 5, 7, 9) ...... (GND – 0.3V) to 15V Gate Voltages (Pins 12, 14, 16, 18) ........................ 75V Sense Voltages (Pins 13, 15, 17, 19).................. V + ± 5V Current (Any Pin).................................................. 50mA Operating Temperature Range LT1161C ............................................... 0°C to 70°C LT1161I ............................................ – 40°C to 85°C Junction Temperature Range (Note 1) LT1161C .............................................. 0°C to 125°C LT1161I ......................................... – 40°C to 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C PACKAGE/ORDER INFORMATION TOP VIEW GND TIMER1 INPUT 1 TIMER 2 INPUT 2 TIMER 3 INPUT 3 TIMER 4 INPUT 4 1 2 3 4 5 6 7 8 9 20 V+ ORDER PART NUMBER LT1161CN LT1161CS LT1161IN LT1161IS 19 SENSE 1 18 GATE 1 17 SENSE 2 16 GATE 2 15 SENSE 3 14 GATE 3 13 SENSE 4 12 GATE 4 11 V + S PACKAGE 20-LEAD PLASTIC SOL GND 10 N PACKAGE 20-LEAD PLASTIC DIP θJA = 70°C/ W (N) θJA = 110°C/ W (S) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL IS ∆IS(ON) VINH VINL IIN CIN VT(TH) VT(CL) IT VSEN ISEN VGATE – V + PARAMETER Supply Current Delta Supply Current (ON State) Input High Voltage Input Low Voltage Input Current Input Capacitance Timer Threshold Voltage Timer Clamp Voltage Timer Charge Current Drain Sense Threshold Voltage Temperature Coefficient Drain Sense Input Current Gate Voltage Above Supply TA = 25°C, V + = 12V to 48V each channel, unless otherwise noted. MIN 3 q q CONDITIONS All Channels OFF (Note 2) Measure Increase in IS per Channel TYP 4.5 1 MAX 6.5 1.35 0.8 50 185 3.3 3.8 20 80 1.5 6 10 14 14 400 200 50 2 15 55 2.7 3.2 9 50 30 110 5 3 3.5 14 65 +0.33 0.5 4.5 8.5 12 12 220 75 25 VIN = 2V VIN = 5V VIN = 2V, Adjust V T VIN = 0.8V VIN = V T = 2V q q q tON tOFF tOFF(CL) Turn-ON Time Turn-OFF Time Current Limit Turn-OFF Time V + = 48V, VSEN = 65mV V + = 8V V + = 12V V + = 24V V + = 48V V + = 24V, VGATE > 32V, CGATE = 1000pF V + = 24V, VGATE < 2V, CGATE = 1000pF V + = 24V, (V + – VSENSE ) → 0.1V, CGATE = 1000pF q q q 4 7 10 10 100 UNITS mA mA V V µA µA pF V V µA mV %/°C µA V V V V µs µs µs The q denotes specifications which apply over the full operating temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LT1161CN, LT1161IN: TJ = TA + (PD × 70°C/W) LT1161CS, LT1161IS: TJ = TA + (PD × 110°C/W) Note 2: Both V + pins (11, 20) must be connected together and both ground pins (1, 10) must be connected together. 2 U W U U WW W LT1161 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current 20 18 16 16 14 12 TJ = – 40°C TJ = 85°C GATE DRIVE CURRENT (µA) SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0 0 10 30 20 INPUT VOLTAGE (V) 40 50 1161 G01 VGATE – V + ALL CHANNELS ON ALL CHANNELS OFF Supply Current 20 18 16 V + = 24V INPUT THRESHOLD VOLTAGE (V) DRAIN SENSE THRESHOLD VOLTAGE (mV) SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0 –50 –25 25 50 0 TEMPERATURE (°C) 75 100 1161 G04 ALL CHANNELS ON ALL CHANNELS OFF Turn-ON Time Driving MOSFET 500 450 400 IRFZ34 100 90 80 70 60 50 40 30 20 10 350 300 250 200 150 100 50 0 0 10 30 20 INPUT VOLTAGE (V) 40 50 1161 G07 RESTART PERIOD (ms) TURN-OFF TIME (µs) TURN-ON TIME (µs) UW MOSFET Gate Voltage Above V + 100 MOSFET Gate Drive Current 10 8 6 4 2 0 0 10 V + ≥ 24V V + = 12V V + = 8V TJ = 25°C 1 0.1 10 30 INPUT VOLTAGE (V) 20 40 50 1161 G02 0 2 6 10 12 14 4 8 GATE VOLTAGE ABOVE V + (V) 16 1161 G03 Input Threshold Voltage 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 –50 –25 25 50 0 TEMPERATURE (°C) 75 100 1161 G05 Drain Sense Threshold Voltage 110 100 90 80 70 60 50 40 30 20 10 –50 –25 25 50 0 TEMPERATURE (°C) 75 100 1161 G06 V + = 24V V + = 24V TURN-ON TURN-OFF Turn-OFF Time Driving MOSFET 1000 IRFZ34 Automatic Restart Period V + = 24V CT = 3.3µF CT = 1µF 100 CT = 0.33µF NORMAL CURRENT LIMIT CT = 0.1µF 10 –50 0 0 10 30 20 INPUT VOLTAGE (V) 40 50 1161 G08 –25 0 25 50 TEMPERATURE (°C) 75 100 1161 G09 3 LT1161 PIN FUNCTIONS Supply Pins: The two supply pins are internally connected and must also be externally connected. In addition to providing the operating current for the LT1161, the supply pins also serve as the Kelvin connection for the current sense comparators. The supply pins must be connected to the positive side of the drain sense resistors for proper operation of the current sense. Input Pins: The input pins are active high and each pin activates a separate internal charge pump when switched ON. The input threshold is TTL/CMOS compatible but may be taken as high as 15V with or without the supply powered. Each input has approximately 200mV of hysteresis and an internal 75k pull-down resistor. Gate Pins: The gate pins drive the power MOSFET gates. When an input is ON, the corresponding gate pin is pumped approximately 12V above the supply. These pins have a relatively high impedance when above the rail (the equivalent of a few hundred kilohms). Care should be taken to minimize any loading by parasitic resistance to ground or supply. Sense Pins: Each sense pin connects to the input of a supply-referenced comparator with a 65mV nominal offset. When a sense pin is taken more than 65mV below supply, the MOSFET gate for that channel is driven low and the corresponding timing capacitor discharged. Each current-sense comparator operates completely independently. The 65mV typical threshold has a +0.33%/°C temperature coefficient, which closely matches the TC of drain sense resistors formed from copper PC traces. Some loads require high in-rush currents. An RC time delay can be added between the drain sense resistor and the sense pin to ensure that the current-sense comparator does not false trigger during start-up (see Applications Information). However, a maximum of 10kΩ can be inserted between a drain sense resistor and the sense pin. If current sense is not required in any channel, the sense pin for that channel is tied to supply. Timer Pins: A timing capacitor CT from each timer pin to ground sets the restart time following overcurrent detection. CT is rapidly discharged to less than 1V and then recharged by a 14µA nominal current source back to the timer threshold, whereupon restart is attempted. If current sense is not required in any channel, the timer pin for that channel is left open. Ground Pins: The two ground pins are internally connected and must also be externally connected. FUNCTIONAL DIAGRA 14µA TIMER 3V 1.4V 75k INPUT 75k 4 W U U U U U (Each Channel) V+ + – + – + – + – 1.4V OSCILLATOR AND CHARGE PUMP 65mV SENSE GATE 1161 FD LT1161 OPERATIO The LT1161 gate pin has two states, OFF and ON. In the OFF state it is held low, while in the ON state it is pumped to 12V above supply by a self-contained 750kHz charge pump. The OFF state is activated when either the input pin is below 1.4V or the timer pin is below 3V. Conversely, for the ON state to be activated, both the input and timer pins must be above their thresholds. If left open, the input pin is held low by a 75k resistor, while the timer pin is held a diode drop above 3V by a 14µA pullup current source. Thus the timer pin automatically reverts to the ON state, subject to the input also being high. The input has approximately 200mV of hysteresis. The sense pin normally connects to the drain of the power MOSFET, which returns through a low valued drain sense resistor to supply. When the gate is ON and the MOSFET drain current exceeds the level required to generate a 65mV drop across the drain sense resistor, the sense comparator activates a pull-down NPN which rapidly pulls the timer pin below 3V. This in turn causes the timer comparator to override the input pin and activate the gate pin OFF state, thus protecting the power MOSFET. In order for the sense comparator to accurately sense MOSFET drain current, the LT1161 supply pins must be connected directly to the positive side of the drain sense resistors. APPLICATIONS INFORMATION Input/Supply Sequencing There are no input/supply sequencing requirements for the LT1161. The input may be taken up to 15V with the supply at 0V. When the supply is turned on with an input high, the MOSFET turn-on will be inhibited until the timing capacitor charges to 3V (i.e., for one restart cycle). The two V + pins (11, 20) must always be connected to each other. Isolating the Inputs Operation in harsh environments may require isolation to prevent ground transients from damaging control logic. The LT1161 easily interfaces to low cost opto-isolators. The network shown in Figure 3 ensures that the input will be pulled above 2V, but not exceed the absolute maximum LOGIC GND POWER GROUND U W U U U (Each Channel, Refer to Functional Diagram) When the MOSFET gate voltage is less than 1.4V, the timer pin is released. The 14µA current source then slowly charges the timing capacitor back to 3V where the charge pump again starts to drive the gate pin high. If a fault still exists, such as a short circuit, the sense comparator threshold will again be exceeded and the timer cycle will repeat until the fault is removed (see Figure 2). OFF INPUT NORMAL OVERCURRENT NORMAL 12V V+ GATE 0V 3V TIMER 0V 1161 F02 Figure 2. Timing Diagram rating, for supply voltages of 12V to 48V over the entire temperature range. In order to maintain the OFF state, the opto must have less than 20µA of dark current (leakage) hot. 12V TO 48V 100k LOGIC INPUT 2k 1/4 NEC PS2501-4 IN 51k LT1161 GND GND 1161 F03 Figure 3. Isolating the Inputs 5 LT1161 APPLICATIONS INFORMATION Drain Sense Configuration The LT1161 uses supply-referenced current sensing. One input of each channel’s current-sense comparator is connected to a drain sense pin, while the second input is offset 65mV below the supply bus inside the device. For this reason, pins 11 and 20 of the LT1161 must be treated not only as supply pins, but as the reference inputs for the current-sense comparators. Figure 4 shows the proper drain sense configuration for the LT1161. Note that the sense pin goes to the drain end of the sense resistor, while the two V + pins are tied to each other and connected to supply at the same point as the positive ends of the sense resistors. Local supply decoupling at the LT1161 is important at high input voltages (see Protecting Against Supply Transients). The drain sense threshold voltage has a positive temperature coefficient, allowing PTC sense resistors to be used (see Printed Circuit Board Shunts). The selection of RS should be based on the minimum threshold voltage: 50mV RS = ISET Thus the 0.02Ω drain sense resistor in Figure 4 would yield a minimum trip current of 2.5A. This simple configuration is appropriate for resistive or inductive loads which do not generate large current transients at turn-on. 24V V+ V+ LT1161 DS1 1161 F04 + 10µF RS 0.02Ω (PTC) IRFZ34 T1 CT 1µF G1 GND GND 24V, 2A SOLENOID Figure 4. Drain Sense Configuration 6 U + W U U Automatic Restart Period The timing capacitor CT shown in Figure 4 determines the length of time the power MOSFET is held off following a current limit trip. Curves are given in the Typical Performance Characteristics to show the restart period for various values of CT. For example, CT = 0.33µF yields a 50ms restart period. Defeating Automatic Restart Some applications are required to remain off after a fault occurs. When the LT1161 is being driven from CMOS logic, this can be easily implemented by connecting resistor R1 between the input and timer pins as shown in Figure 5. R1 supplies the sustaining current for an SCR which latches the timer pin low. This prevents the MOSFET gate from turning ON until the input has been recycled. TIMER R1 2k 5V CMOS LOGIC ON = 5V OFF = 0V LT1161 INPUT 1161 F05 Figure 5. Latch-Off Input Network (Auto-Restart Defeated) Inductive vs Capacitive Loads 100µF 50V Turning on an inductive load produces a relatively benign ramp in MOSFET current. However, when an inductive load is turned off, the current stored in the inductor needs somewhere to decay. A clamp diode connected directly across each inductive load normally serves this purpose. If a diode is not employed the LT1161 clamps the MOSFET gate 0.7V below ground. This causes the MOSFET to resume conduction during the current decay with (V + + VGS + 0.7V) across it, resulting in high dissipation peaks. Capacitive loads exhibit the opposite behavior. Any load that includes a decoupling capacitor will generate a current equal to CLOAD × (∂V/∂t) during capacitor in-rush. With large electrolytic capacitors, the resulting current LT1161 APPLICATIONS INFORMATION spike can play havoc with the power supply and false trip the current-sense comparator. Turn-on ∂V/∂ t is controlled by the addition of the simple network shown in Figure 6. This network takes advantage of the fact that the MOSFET acts as a source follower during turn-on. Thus the ∂V/∂ t on the source can be controlled by controlling the ∂V/∂ t on the gate: and CD delay the overcurrent trip for drain currents up to approximately 10 × ISET, above which the diode conducts and provides immediate turn-off (see Figure 7). To ensure proper operation of the timer, CD must be ≤ CT. 10 TRIP DELAY TIME (1 = RDCD) ∂V V + − VTH = ∂ t 105 × C1 where VTH is the MOSFET gate threshold voltage. Multiplying CLOAD times this ∂V/∂ t yields the value of the current spike. For example, if V + = 24V, VTH = 2V, and C1 = 0.1µF, ∂V/∂ t = 2.2V/ms, resulting in a 2.2A turn-on spike into 1000µF. The diode and second resistor in the network ensure fast current limit turn-off. When turning off a capacitive load, the source of the MOSFET can “hang up” if the load resistance does not discharge CLOAD as fast as the gate is being pulled down. If this is the case, a diode may have to be added from source to gate to prevent VGS(MAX) from being exceeded. CURRENT LIMIT DELAY NETWORK V+ V+ DS LT1161 ∂V/ ∂ t CONTROL NETWORK 1N4148 100k G C1 100k 1RFZ24 1N4148 CD RD (≤10k) 24V + CLOAD 1161 F06 Figure 6. ∂V/∂ t Control and Current Limit Delay Adding Current Limit Delay When capacitive loads are being switched or in very noisy environments, it is desirable to add delay in the drain current-sense path to prevent false tripping (inductive loads normally do not need delay). This is accomplished by the current limit delay network shown in Figure 6. RD U W U U 1 0.1 0.01 10 100 1 MOSFET DRAIN CURRENT (1 = SET CURRENT) L1161 F07 Figure 7. Current Limit Delay Time Printed Circuit Board Shunts The sheet resistance of 1oz. copper clad is approximately 5 × 10 –4 Ω /square with a temperature coefficient of +0.39%/°C. Since the LT1161 drain sense threshold has a similar temperature coefficient (+0.33%/°C), this offers the possibility of nearly zero TC current sensing using “free” drain sense resistors made out of PC trace material. A conservative approach is to use 0.02" of width for each 1A of current for 1oz. copper. Combining the LT1161 drain sense threshold with the 1oz. copper sheet resistance results in a simple expression for width and length: Width (1oz. Cu) = 0.02" × ISET Length (1oz. Cu) = 2" The width for 2oz. copper would be halved while the length would remain the same. Bends may be incorporated into the resistor to reduce space; each bend is equivalent to approximately 0.6 × width of straight length. Kelvin connections should be employed by running separate traces from the ends of the resistors back to the LT1161 V + and sense pins. See Application Note 53 for further information on printed circuit board shunts. + 7 LT1161 APPLICATIONS INFORMATION Low Voltage/Wide Supply Range Operation When the supply is