LT1175CT-PBF

FeaTures n n n n n n n n n LT1175 500mA Negative Low Dropout Micropower Regulator DescripTion The LT®1175 is a negative micropower low dropout regulator. It features 45µA quiescent current, dropping to 10µA in shutdown. A new reference amplifier topology gives precision DC characteristics along with the ability to maintain good loop stability with an extremely wide range of output capacitors. Very low dropout voltage and high efficiency are obtained with a unique power transistor anti-saturation design. Adjustable and fixed 5V versions are available. Several new features make the LT1175 very user-friendly. The SHDN pin can interface directly to either positive or negative logic levels. Current limit is user-selectable at 200mA, 400mA, 600mA and 800mA. The output can be forced to reverse voltage without damage or latchup. Unlike some earlier designs, the increase in quiescent current during a dropout condition is actively limited. The LT1175 has complete blowout protection with current limiting, power limiting and thermal shutdown. Special attention was given to the problem of high temperature operation with micropower operating currents, preventing output voltage rise under no-load conditions. The LT1175 is available in 8-pin PDIP and SO packages, 3-lead SOT223 as well as 5-pin surface mount DD and through-hole TO-220 packages. The 8-pin SO package is specially constructed for low thermal resistance. Minimum Input-to-Output Voltage 1.0 INPUT-TO-OUTPUT VOLTAGE (V) TJ = 25°C ILIM2, ILIM4 TIED TO VIN Operating Current: 45µA Adjustable Current Limit Low Voltage Linear Dropout Characteristics Stable with Wide Range of Output Capacitors Shutdown Current: 10µA Positive or Negative Shutdown Logic Fixed 5V and Adjustable Versions Tolerates Reverse Output Voltage Available in 8-pin PDIP and SO Packages, 3-lead SOT-223, 5-Pin Surface Mount DD and Through-Hole TO-220 Packages applicaTions n n n n n n Analog Systems Modems Instrumentation A/D and D/A Converters Interface Drivers Battery-Powered Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion Typical LT1175 Connection + SHDN VIN ILIM2 ILIM4 LT1175-5 OUTPUT GND SENSE 0.8 CIN* –VIN + COUT ≥ 0.1µF –5V UP TO 500mA 0.6 0.4 0.2 *CIN IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION 1175 TA01 SECTION FOR DETAILS 0 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) 0.6 0.7 1175 TA02 1175fe  LT1175 absoluTe MaxiMuM raTings (Note 1) Input Voltage (Transient 1 sec, Note 11) ...................25V Input Voltage (Continuous) .......................................20V Input-to-Output Differential Voltage (Note 12) ..........20V 5V SENSE Pin (with Respect to GND Pin) ......... 2V, –10V ADJ SENSE Pin (with Respect to OUTPUT Pin)...................20V, –0.5V 5V SENSE Pin (with Respect to OUTPUT Pin)......................20V, –7V Output Reverse Voltage ..............................................2V SHDN Pin to GND Pin Voltage (Note 2) ........ 13.5V, –20V SHDN Pin to VIN Pin Voltage .............................30V, –5V Operating Junction Temperature Range LT1175C ................................................. 0°C to 125°C LT1175I .............................................. –40°C to 125°C Ambient Operating Temperature Range LT1175C ................................................... 0°C to 70°C LT1175I ................................................–40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C pin conFiguraTion TOP VIEW VIN 1 ILIM2 2 OUTPUT 3 SENSE 4 8 7 6 5 VIN ILIM4 SHDN GND TAB IS VIN FRONT VIEW 5 4 3 2 1 SHDN GND VIN SENSE OUTPUT TAB IS VIN FRONT VIEW 3 2 1 GND VIN OUTPUT N8 PACKAGE 8-LEAD PDIP θJA = 80°C/W TO 120°C/W DEPENDING ON PC BOARD LAYOUT TOP VIEW VIN 1 ILIM2 2 OUTPUT 3 SENSE 4 8 7 6 5 VIN ILIM4 SHDN GND Q PACKAGE 5-LEAD PLASTIC DD θJA = 27°C/W TO 60°C/W DEPENDING ON PC MOUNTING. SEE DATA SHEET FOR DETAILS ST PACKAGE 3-LEAD PLASTIC SOT-223 θJA = 50°C/W WITH BACKPLANE AND 10cm2 TOPSIDE LAND SOLDERED TO TAB FRONT VIEW 5 4 3 2 1 TAB IS VIN T PACKAGE 5-LEAD PLASTIC TO-220 θJA = 50°C/W, θJC = 5°C/W SHDN GND VIN SENSE OUTPUT S8 PACKAGE 8-LEAD PLASTIC SO θJA = 60°C/W TO 100°C/W DEPENDING ON PC BOARD LAYOUT PINS 1, 8 ARE INTERNALLY CONNECTED TO DIE ATTACH PADDLE FOR HEAT SINKING. ELECTRICAL CONTACT CAN BE MADE TO EITHER PIN. FOR BEST THERMAL RESISTANCE, PINS 1, 8 SHOULD BE CONNECTED TO AN EXPANDED LAND THAT IS OVER AN INTERNAL OR BACKSIDE PLANE. SEE APPLICATIONS INFORMATION 1175fe  LT1175 orDer inForMaTion LEAD FREE FINISH LT1175CN8#PBF LT1175CN8-5#PBF LT1175CS8#PBF LT1175CS8-5#PBF LT1175CST-5#PBF LT1175CQ#PBF LT1175CQ-5#PBF LT1175CT#PBF LT1175CT-5#PBF LT1175IN8#PBF LT1175IN8-5#PBF LT1175IS8#PBF LT1175IS8-5#PBF LT1175IST-5#PBF LT1175IQ#PBF LT1175IQ-5#PBF LT1175IT#PBF LT1175IT-5#PBF LEAD BASED FINISH LT1175CN8 LT1175CN8-5 LT1175CS8 LT1175CS8-5 LT1175CST-5 LT1175CQ LT1175CQ-5 LT1175CT LT1175CT-5 LT1175IN8 LT1175IN8-5 LT1175IS8 LT1175IS8-5 LT1175IST-5 LT1175IQ LT1175IQ-5 LT1175IT LT1175IT-5 TAPE AND REEL LT1175CN8#TRPBF LT1175CN8-5#TRPBF LT1175CS8#TRPBF LT1175CS8-5#TRPBF LT1175CST-5#TRPBF LT1175CQ#TRPBF LT1175CQ-5#TRPBF LT1175CT#TRPBF LT1175CT-5#TRPBF LT1175IN8#TRPBF LT1175IN8-5#TRPBF LT1175IS8#TRPBF LT1175IS8-5#TRPBF LT1175IST-5#TRPBF LT1175IQ#TRPBF LT1175IQ-5#TRPBF LT1175IT#TRPBF LT1175IT-5#TRPBF TAPE AND REEL LT1175CN8#TR LT1175CN8-5#TR LT1175CS8#TR LT1175CS8-5#TR LT1175CST-5#TR LT1175CQ#TR LT1175CQ-5#TR LT1175CT#TR LT1175CT-5#TR LT1175IN8#TR LT1175IN8-5#TR LT1175IS8#TR LT1175IS8-5#TR LT1175IST-5#TR LT1175IQ#TR LT1175IQ-5#TR LT1175IT#TR LT1175IT-5#TR PART MARKING* LT1175CN8 LT1175CN8-5 1175 11755 11755 LT1175CQ LT1175CQ-5 LT1175CT LT1175CT-5 LT1175IN8 LT1175IN8-5 1175I 1175I5 1175I5 LT1175IQ LT1175IQ-5 LT1175IT LT1175IT-5 PART MARKING* LT1175CN8 LT1175CN8-5 1175 11755 11755 LT1175CQ LT1175CQ-5 LT1175CT LT1175CT-5 LT1175IN8 LT1175IN8-5 1175I 1175I5 1175I5 LT1175IQ LT1175IQ-5 LT1175IT LT1175IT-5 PACKAGE DESCRIPTION 8-Lead Plastic Dip 8-Lead Plastic Dip 8-Lead Plastic SO 8-Lead Plastic SO 3-Lead Plastic SOT-223 5-Lead Plastic DD-Pak 5-Lead Plastic DD-Pak 5-Lead Plastic TO-220 5-Lead Plastic TO-220 8-Lead Plastic Dip 8-Lead Plastic Dip 8-Lead Plastic SO 8-Lead Plastic SO 3-Lead Plastic SOT-223 5-Lead Plastic DD-Pak 5-Lead Plastic DD-Pak 5-Lead Plastic TO-220 5-Lead Plastic TO-220 PACKAGE DESCRIPTION 8-Lead Plastic Dip 8-Lead Plastic Dip 8-Lead Plastic SO 8-Lead Plastic SO 3-Lead Plastic SOT-223 5-Lead Plastic DD-Pak 5-Lead Plastic DD-Pak 5-Lead Plastic TO-220 5-Lead Plastic TO-220 8-Lead Plastic Dip 8-Lead Plastic Dip 8-Lead Plastic SO 8-Lead Plastic SO 3-Lead Plastic SOT-223 5-Lead Plastic DD-Pak 5-Lead Plastic DD-Pak 5-Lead Plastic TO-220 5-Lead Plastic TO-220 TEMPERATURE RANGE 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C TEMPERATURE RANGE 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 1175fe  LT1175 elecTrical characTerisTics PARAMETER Feedback Sense Voltage Output Voltage Initial Accuracy Output Voltage Accuracy (All Conditions) Quiescent Input Supply Current GND Pin Current Increase with Load (Note 4) Input Supply Current in Shutdown Shutdown Thresholds (Note 9) SHDN Pin Current (Note 2) Output Bleed Current in Shutdown (Note 6) SENSE Pin Input Current Dropout Voltage (Note 7) VSHDN = 0V l The l denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C. VOUT = 5V, VIN = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to VIN, TJ = 25°C, unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious. CONDITIONS Adjustable Part Fixed 5V Part Adjustable, Measured at 3.8V Sense Fixed 5V VIN – VOUT = 1V to VIN = 20V, IOUT = 0A to 500mA P = 0 to PMAX, TJ = TMIN to TMAX (Note 3) VIN – VOUT ≤ 12V l l l MIN 3.743 4.93 TYP 3.8 5.0 0.5 0.5 1.5 45 10 10 MAX 3.857 5.075 1.5 1.5 2.5 65 80 20 20 25 2.5 8 4 1 5 150 20 0.2 0.26 0.7 0.5 0.45 0.45 1300 975 650 325 0.015 0.35 0.1 0.2 1.25 UNITS V V % % % µA µA µA/mA µA µA V µA µA µA µA nA µA V V V V V V mA mA mA mA %/V % %/W %/W % Either Polarity On SHDN Pin VSHDN = 0V to 10V (Flows Into Pin) VSHDN = –15V to 0V (Flows Into Pin) VOUT = 0V, VIN = 15V l l 0.8 4 1 0.1 1 75 12 0.1 0.18 0.5 0.33 0.3 0.26 520 390 260 130 800 600 400 200 0.003 0.1 0.04 0.1 0.25 l (Adjustable Part Only, Current Flows Out of Pin) (Fixed Voltage Only, Current Flows Out of Pin) IOUT = 25mA IOUT = 100mA IOUT = 500mA ILIM2 Open, IOUT = 300mA ILIM4 Open, IOUT = 200mA ILIM2, ILIM4 Open, IOUT = 100mA VIN – VOUT = 1V to 12V ILIM2 Open ILIM4 Open ILIM2, ILIM4 Open VIN – VOUT = 1V to VIN = 20V IOUT = 0mA to 500mA P = 0 to PMAX (Notes 3, 8) TJ = 25°C to TJMIN, or 25°C to TJMAX 5-Pin Packages 8-Pin Packages l l l l l l l l l l l l l l Current Limit (Note 11) Line Regulation (Note 10) Load Regulation (Note 5, 10) Thermal Regulation Output Voltage Temperature Drift Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: SHDN pin maximum positive voltage is 30V with respect to – VIN and 13.5V with respect to GND. Maximum negative voltage is –20V with respect to GND and –5V with respect to –VIN. Note 3: PMAX = 1.5W for 8-pin packages, and 6W for 5-pin packages. This power level holds only for input-to-output voltages up to 12V, beyond which internal power limiting may reduce power. See Guaranteed Current Limit curve in Typical Performance Characteristics section. Note that all conditions must be met. Note 4: GND pin current increases because of power transistor base drive. At low input-to-output voltages ( 125°C, power transistor leakage could increase higher than the 10µA to 25µA drawn by the output divider or fixed voltage SENSE pin, causing the output to rise above the regulated value. To prevent this condition, an internal active pull-up will automatically turn on, but supply current will increase. Note 6: This is the current required to pull the output voltage to within 1V of ground during shutdown. Note 7: Dropout voltage is measured by setting the input voltage equal to the normal regulated output voltage and measuring the difference between VIN and VOUT. For currents between 100mA and 500mA, with both ILIM pins tied to VIN, maximum dropout can be calculated from VDO = 0.15 + 1.1Ω (IOUT). 1175fe  LT1175 elecTrical characTerisTics Note 8: Thermal regulation is a change in the output voltage caused by die temperature gradients, so it is proportional to chip power dissipation. Temperature gradients reach final value in less than 100ms. Output voltage changes after 100ms are due to absolute die temperature changes and reference voltage temperature coefficient. Note 9: The lower limit of 0.8V is guaranteed to keep the regulator in shutdown. The upper limit of 2.5V is guaranteed to keep the regulator active. Either polarity may be used, referenced to GND pin. Note 10: Load and line regulation are measured on a pulse basis with pulse width of 20ms or less to keep chip temperature constant. DC regulation will be affected by thermal regulation (Note 8) and chip temperature changes. Load regulation specification also holds for currents up to the specified current limit when ILIM2 or ILIM4 are left open. Note 11: Current limit is reduced for input-to-output voltage above 12V. See the graph in Typical Performance Characteristics for guaranteed limits above 12V. Note 12: Operating at very large input-to-output differential voltages (>15V) with load currents less than 5mA requires an output capacitor with an ESR greater than 1Ω to prevent low level output oscillations. Typical perForMance characTerisTics Typical Current Limit Characteristics 1.0 CURRENT LIMIT CHANGES ONLY SLIGHTLY WITH TEMPERATURE SO CURVES ARE REPRESENTATIVE OF ALL TEMPERATURES ILIM2, ILIM4 TIED TO VIN CURRENT (A) 0.4 0.3 0.2 0.1 0 ILIM4 TIED TO VIN ILIM2 TIED TO VIN ILIM2, ILIM4 OPEN 5 15 20 0 25 10 INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V) 1175 G01 Guaranteed Current Limit 0.6 ILIM2, ILIM4 TIED TO VIN 0.5 ILIM4 TIED TO VIN CURVES REPRESENT MINIMUM GUARANTEED LIMITS AT ALL TEMPERATURES VOLTAGE (V) 5.05 Output Voltage Temperature Drift OUTPUT FIXED 5V PART 0.8 CURRENT (A) 5.00 0.6 4.95 ILIM2 TIED TO VIN 0.4 3.84 FEEDBACK VOLTAGE ADJUSTABLE PART 0.2 ILIM2, ILIM4 OPEN 3.80 0 0 25 5 10 15 20 INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V) 1175 G02 3.76 –50 50 25 0 75 100 –25 JUNCTION TEMPERATURE (°C) 125 1175 G03 Minimum Input-to-Output Voltage 1.0 INPUT-TO-OUTPUT VOLTAGE (V) INPUT-TO-OUTPUT VOLTAGE (V) TJ = 25°C VIN REDUCED UNTIL OUTPUT VOLTAGE DROPS 1% ILIM2, ILIM4 OPEN ILIM4 TIED TO VIN ILIM2, ILIM4 TIED TO VIN 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) 0.6 0.7 1.0 Minimum Input-to-Output Voltage VIN REDUCED UNTIL OUTPUT VOLTAGE DROPS 1%. ILIM2, ILIM4 TIED TO VIN CURRENT (nA) 100 SENSE Bias Current (Adjustable Part) 0.8 0.8 80 0.6 ILIM2 TIED TO VIN 0.6 TJ = 125°C 0.4 TJ = 25°C 60 0.4 40 0.2 0.2 TJ = –55°C 20 0 0 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) 0.6 0.7 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1175 G04 1175 G05 1175 G06 1175fe  LT1175 Typical perForMance characTerisTics Shutdown Input Current 25 2.5 POSITIVE THRESHOLD PIN CURRENT (µA) Shutdown Thresholds 15 SHDN Pin Characteristics VIN = 25V CHARACTERISTICS DO NOT CHANGE SIGNIFICANTLY WITH TEMPERATURE, SO A SINGLE CURVE IS SHOWN. POSITIVE CURRENT FLOWS INTO SHDN PIN 20 INPUT CURRENT (µA) THRESHOLD (V) 2.0 10 15 TJ = 125°C TJ = 25°C 1.5 NEGATIVE THRESHOLD 5 10 1.0 0 IF SHDN PIN IS NEGATIVE WITH RESPECT TO INPUT VOLTAGE AND INPUT VOLTAGE IS LESS THAN 15V, NEGATIVE BREAKOVER POINT WILL BE ABOUT 8V BELOW –VIN TJ = –55°C 5 0.5 DEVICE IS OFF BELOW THRESHOLD –25 25 50 0 75 TEMPERATURE (°C) 100 125 –5 0 0 5 15 10 INPUT VOLTAGE (V) 20 25 1175 G07 0 –50 –10 –25 –20 –15 –10 –5 0 5 10 15 20 25 SHUTDOWN TO GROUND VOLTAGE (V) 1175 G09 1175 G08 GND Pin Current 20 100 Ripple Rejection VOUT = 12V (ADJUSTABLE) WITH 0.1µF ACROSS DIVIDER RESISTOR VOUT = 5V (FIXED) VOUT = 12V (ADJUSTABLE) IOUT = 100mA VIN – VOUT = 2V COUT = 1µF TANT 10 100 1k 10k FREQUENCY (Hz) 100k 1M GROUND PIN CURRENT (mA) 16 REJECTION (dB) 0.6 0.7 1175 G10 80 12 POWER TRANSISTOR IN DROPOUT TJ = –55°C TJ = 25°C VIN – VOUT = 2V TJ = 25°C 60 8 40 4 20 VIN – VOUT ≥ 3V TJ = 25°C 0 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) 0 RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN 25mA AND 500mA. LARGER OUTPUT CAPACITORS DO NOT IMPROVE REJECTION FOR FREQUENCIES BELOW 50kHz. AT VERY LIGHT LOADS, REJECTION WILL IMPROVE WITH LARGER OUTPUT CAPACITORS 1175 G11 1175fe  LT1175 pin FuncTions (N8/Q/ST/S8/T) VIN (Pins 1, 8/Pin 3, Tab/Pin 2, Tab/Pins 1, 8/Pin 3, Tab): Power is supplied to the device through this pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main filter capacitor. In general, the impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. A 1µF or larger tantalum capacitor is suggested for all applications, but if low ESR capacitors such as ceramic or film are used for the output and input capacitors, the input capacitor should be three times the value of the output capacitor. ILIM2, ILIM4 (Pins 2, 7/NA/NA/Pins 2, 7/NA): The two current limit pins are emitter sections of the power transistor. When left open, they float several hundred millivolts above the negative input voltage. When shorted to the input voltage, they increase current limit by a minimum of 200mA for ILIM2 and 400mA for ILIM4. These pins must be connected only to the input voltage, either directly or through a resistor. OUTPUT (Pin 3/Pin 1/Pin 1/Pin 3/Pin 1): The OUTPUT pin is the collector of the NPN power transistor. It can be forced to the input voltage, to ground or up to 2V positive with respect to ground without damage or latchup (see Output Voltage Reversal in Applications Information section). The LT1175 has foldback current limit, so maximum current at the OUTPUT pin is a function of input-to-output voltage. See Typical Performance Characteristics. SENSE (Pin 4/Pin 2/NA/Pin 4/Pin 2): The SENSE pin is used in the adjustable version to allow custom selection of output voltage, with an external divider set to generate 3.8V at the SENSE pin. Input bias current is typically 75nA flowing out of the pin. Maximum forced voltage on the SENSE pin is 2V and –10V with respect to GND pin. The fixed 5V version utilizes the SENSE pin to give true Kelvin connections to the load or to drive an external pass transistor for higher output currents. Bias current out of the 5V SENSE pin is approximately 12µA. Separating the SENSE and OUTPUT pins also allows for a new loop compensation technique described in the Applications Information section. GND (Pin 5/Pin 4/Pin 3/Pin 5/Pin 4): The GND pin has a quiescent current of 45µA at zero load current, increasing by approximately 10µA per mA of output current. At 500mA output current, GND pin current is about 5mA. Current flows into the GND pin. SHDN (Pin 6/Pin 5/NA/Pin 6/Pin 5): The SHDN pin is specially configured to allow it to be driven from either positive voltage logic or with negative only logic. Forcing the SHDN pin 2V either above or below the GND pin will turn the regulator on. This makes it simple to connect directly to positive logic signals for active low shutdown. If no positive voltages are available, the SHDN pin can be driven below the GND pin to turn the regulator on. When left open, the SHDN pin will default low to a regulator “on” condition. For all voltages below absolute maximum ratings, the SHDN pin draws only a few microamperes of current (see Typical Performance Characteristics). Maximum voltage on the SHDN pin is 15V, – 20V with respect to the GND pin and 35V, –5V with respect to the negative input pin. 1175fe  LT1175 applicaTions inForMaTion Note to Reader: To avoid confusion when working with negative voltages (is –6V more or less than –5V?), I have decided to treat the LT1175 as if it were a positive regulator and express all voltages as positive values, both in text and in formulas. If you do the same and simply add a negative sign to the eventual answer, confusion should be avoided. Please don’t give me a hard time about “preciseness” or “correctness.” I have to field phone calls from around the world and this is my way of dealing with a multitude of conventions. Thanks for your patience. Setting Output Voltage The LT1175 adjustable version has a feedback sense voltage of 3.8V with a bias current of approximately 75nA flowing out of the SENSE pin. To avoid output voltage errors caused by this current, the output divider string (see Figure 1) should draw about 25µA. Table 1 shows suggested resistor values for a range of output voltages. The second part of the table shows resistor values which draw only 10µA of current. Output voltage error caused by bias current with the lower valued resistors is about 0.4% maximum and with the higher values, about 1% maximum. A formula is also shown for calculating the resistors for any output voltage. Table 1. Suggested Divider Resistors OUTPUT VOLTAGE 5V 6V 8V 10V 12V 15V R1 IDIV = 25µA 150k 150k 150k 150k 150k 150k R2 NEAREST 1% 47.5k 86.6k 165k 243k 324k 442k R1 IDIV = 10µA 383k 383k 383k 383k 383k 383k R2 NEAREST 1% 121k 221k 422k 619k 825k 1.13M The LT1175-5 is a fixed 5V design with the SENSE pin acting as a Kelvin connection to the output. Normally the SENSE pin and the OUTPUT pin are connected directly together, either close to the regulator or at the remote load point. SHUTDOWN LOGIC > 2V OR < –2V TO TURN REGULATOR ON + CIN + SHDN VIN ILIM2 ILIM4 LT1175 OUTPUT GND SENSE R1 383k 1% R2 825k 1% COUT ≥ 0.1µF VOUT –12V 1175 F01 Figure 1. Typical LT1175 Adjustable Connection Setting Current Limit The LT1175 uses two ILIM pins to set current limit (typical) at 200mA, 400mA, 600mA or 800mA. The corresponding minimum guaranteed currents are 130mA, 260mA, 390mA and 520mA. This allows the user to select a current limit tailored to his specific application and prevents the situation where short-circuit current is many times higher than full-load current. Problems with input supply overload or excessive power dissipation in a faulted load are prevented. Power limiting in the form of foldback current limit is built in and reduces current limit as a function of input-to-output voltage differential for differentials exceeding 14V. See the graph in Typical Performance Characteristics. The LT1175 is guaranteed to be blowout-proof regardless of current limit setting. The power limiting combined with thermal shutdown protects the device from destructive junction temperatures under all load conditions. Shutdown In shutdown, the LT1175 draws only about 10µA. Special circuitry is used to minimize increases in shutdown current at high temperatures, but a slight increase is seen above 125°C. One option not taken was to actively pull down on the output during shutdown. This means that the output will fall slowly after shutdown is initiated, at a rate determined by load current plus the 12µA internal load, and the size of the output capacitor. Active pull-down is 1175fe R1 = R2 = IDIV = Desired divider current ) (Simple formula) 3.8V R1( V − 3.8V)  Taking SENSE pin bias R2 =   3.8V + R1(I )  current into account  R1 VOUT − 3.8V OUT FB 3.8V IDIV (  LT1175 applicaTions inForMaTion normally a good thing when the regulator is used by itself, but it prevents the user from shutting down the regulator when a second power source is connected to the LT1175 output. If active output pull-down is needed in shutdown, it can be added externally with a depletion mode PFET as shown in Figure 2. Note that the maximum pinch-off voltage of the PFET must be less than the positive logic high level to ensure that the device is completely off when the regulator is active. The Motorola J177 device has 300Ω on resistance for zero gate source voltage. 3V TO 5V yet allows the power transistor to approach its theoretical saturation limit. Output Capacitor Several new regulator design techniques are used to make the LT1175 extremely tolerant of output capacitor selection. Like most low dropout designs which use a collector or drain of the power transistor to drive the output node, the LT1175 uses the output capacitor as part of the overall loop compensation. Older regulators generally required the output capacitor to have a minimum value of 1µF to 100µF a maximum ESR (Effective Series Resistance) of , 0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to 0.3Ω. These restrictions usually could be met only with good quality solid tantalum capacitors. Aluminum capacitors have problems with high ESR unless much higher values of capacitance are used (physically large). The ESR of ceramic or film capacitors was too low, which made the capacitance/ESR zero frequency too high to maintain phase margin in the regulator. Even with optimum capacitors, loop phase margin was very low in previous designs when output current was low. These problems led to a new design technique for the LT1175 error amplifier and internal frequency compensation as shown in Figure 3. A conventional regulator loop consists of error amplifier A1, driver transistor Q2 and power transistor Q1. Added to this basic loop are secondary loops generated by Q3 and CF. A DC negative feedback current fed into the error amplifier through Q3 and RN causes overall loop current gain to be very low at light load currents. This is not a problem because very little gain is needed at light loads. In addition to low gain, the parasitic pole frequency at Q2 base is extended by the DC feedback. The combination of these two effects dramatically improves loop phase margin at light loads and makes the loop tolerant of large ESR in the output capacitor. With heavy loads, loop phase and gain are not nearly as troublesome and large negative feedback could degrade regulation. The logarithmic behavior of the base emitter voltage of Q1 reduces Q3 negative feedback at heavy loads to prevent poor regulation. In a conventional design, even with the nonlinear feedback, poor loop phase margin would occur at medium to heavy loads if the ESR of the output capacitor fell below 0.3Ω. 1175fe + SHDN –VIN VIN ILIM2 ILIM4 LT1175-5 OUTPUT GND SENSE s Q1* d COUT ≥ 0.1µF * MOTOROLA J177 PINCH-OFF VOLTAGE MUST BE LESS THAN POSITIVE LOGIC HIGH VOLTAGE 1175 F02 Figure 2. Active Output Pull-Down During Shutdown Minimum Dropout Voltage Dropout voltage is the minimum voltage required between input and output to maintain proper output regulation. For older 3-terminal regulator designs, dropout voltage was typically 1.5V to 3V. The LT1175 uses a saturating power transistor design which gives much lower dropout voltage, typically 100mV at light loads and 450mV at full load. Special precautions were taken to ensure that this technique does not cause quiescent supply current to be high under light load conditions. When the regulator input voltage is too low to maintain a regulated output, the pass transistor is driven hard by the error amplifier as it tries to maintain regulation. The current drawn by the driver transistor could be tens of milliamperes even with little or no load on the output. This indeed was the case for older IC designs that did not actively limit driver current when the power transistor saturated. The LT1175 uses a new antisaturation technique that prevents high driver current,  LT1175 applicaTions inForMaTion GND LT1175 + 3.8V R1 COUT ESR R2 Q2 SENSE LOAD A1 AC FEEDFORWARD PATH NEGATIVE DC FEEDBACK AT LIGHT LOADS Q3 RN This condition can occur with ceramic or film capacitors which often have an ESR under 0.1Ω. With previous designs, the user was forced to add a real resistor in series with the capacitor to guarantee loop stability. The LT1175 uses a unique AC feedforward technique to eliminate this problem. CF is a conventional feedforward capacitor often used in regulators to cancel the pole formed by the output capacitor. It would normally be connected from the regulated output node to the feedback node at the R1/R2 junction or to an internal node on the amplifier as shown. In this case, however, the capacitor is connected to the internal structure of the power transistor. RC is the unavoidable parasitic collector resistance of the power transistor. Access to the node at the bottom of RC is available only in monolithic structures where Kelvin connections can be made to the NPN buried collector layer. The loop now responds as if RC were in series with the output capacitor and good loop stability is achieved even with extremely low ESR in the output capacitor. 0 – + CF 20pF VIN OUTPUT OUTPUT RC 0.5 PARASITIC COLLECTOR RESISTANCE POWER TRANSISTOR Q1 RLIM CURRENT LIMIT SENSE RESISTOR 1175 F03 Figure 3 The end result of all this attention to loop stability is that the output capacitor used with the LT1175 can range in value from 0.1µF to hundreds of microfarads, with an ESR from 0Ω to 10Ω. This range allows the use of ceramic, solid tantalum, aluminum and film capacitors over a wide range of values. The optimum output capacitor type for the LT1175 is still solid tantalum, but there is considerable leeway in selecting the exact unit. If large load current transients are expected, larger capacitors with lower ESR may be needed to control worst-case output variation during transients. If transients are not an issue, the capacitor can be chosen for small physical size, low price, etc. Concerns about surge currents in tantalum capacitors are not an issue for the output capacitor because the LT1175 limits inrush current to well below the level which can cause capacitor damage. Surges caused by shorting the regulator output are also not a problem because tantalum 1175fe LT1175 applicaTions inForMaTion capacitors do not fail during a “shorting out” surge, only during a “charge up” surge. The output capacitor should be located within several inches of the regulator. If remote sensing is used, the output capacitor can be located at the remote sense node, but the GND pin of the regulator should also be connected to the remote site. The basic rule is to keep SENSE and GND pins close to the output capacitor, regardless of where it is. Operating at very large input-to-output differential voltages (>15V) with load currents less than 5mA requires an output capacitor with an ESR greater than 1Ω to prevent low level output oscillations. Input Capacitor The LT1175 requires a separate input bypass capacitor only if the regulator is located more than six inches from the raw supply output capacitor. A 1µF or larger tantalum capacitor is suggested for all applications, but if low ESR capacitors such as ceramic or film are used for the output and input capacitors, the input capacitor should be at least three times the value of the output capacitor. If a solid tantalum or aluminum electrolytic output capacitor is used, the input capacitor is very noncritical. High Temperature Operation The LT1175 is a micropower design with only 45µA quiescent current. This could make it perform poorly at high temperatures (>125°C), where power transistor leakage might exceed the output node loading current (5µA to 15µA). To avoid a condition where the output voltage drifts uncontrolled high during a high temperature no-load condition, the LT1175 has an active load which turns on when the output is pulled above the nominal regulated voltage. This load absorbs power transistor leakage and maintains good regulation. There is one downside to this feature, however. If the output is pulled high deliberately, as it might be when the LT1175 is used as a backup to a slightly higher output from a primary regulator, the LT1175 will act as an unwanted load on the primary regulator. Because of this, the active pull-down is deliberately “weak.” It can be modeled as a 2k resistor in series with an internal clamp voltage when the regulator output is being pulled high. If a 4.8V output is pulled to 5V, for instance, the load on the primary regulator would be (5V – 4.8V)/2kΩ = 100µA. This also means that if the internal pass transistor leaks 50µA, the output voltage will be (50µA)(2kΩ) = 100mV high. This condition will not occur under normal operating conditions, but could occur immediately after an output short circuit had overheated the chip. Thermal Considerations The LT1175 is available in a special 8-pin surface mount package which has Pins 1 and 8 connected to the die attach paddle. This reduces thermal resistance when Pins 1 and 8 are connected to expanded copper lands on the PC board. Table 2 shows thermal resistance for various combinations of copper lands and backside or internal planes. Table 2 also shows thermal resistance for the 5-pin DD surface mount package and the 8-pin DIP and package. Table 2. Package Thermal Resistance (°C/W) LAND AREA Minimum Minimum with Backplane 1cm2 Top Plane with Backplane 10cm2 Top Plane with Backplane DIP 140 110 100 80 ST 90 70 64 50 SO 100 80 75 60 Q 60 50 35 27 To calculate die temperature, maximum power dissipation or maximum input voltage, use the following formulas with correct thermal resistance numbers from Table 2. For through-hole TO-220 applications use θJA = 50°C/W without a heat sink and θJA = 5°C/W + heat sink thermal resistance when using a heat sink. Die Temp = TA + θ JA ( VIN − VOUT )(ILOAD ) Maximum Power Dissipation = Maximum Input Voltage for Thermal Considerations = TMAX − TA θ JA TMAX − TA θ JA (ILOAD ) + VOUT 1175fe  LT1175 applicaTions inForMaTion TA = Maximum ambient temperature TMAX = Maximum LT1175 die temperature (125°C for commercial and industrial grades) θJA VIN = LT1175 thermal resistance, junction to ambient = Maximum continuous input voltage at maximum load current between the input and output of the regulator. Reverse voltages between input and output above 1V will damage the regulator if large currents are allowed to flow. Simply disconnecting the input source with the output held up will not cause damage even though the input-to-output voltage will become slightly reversed. High Frequency Ripple Rejection The LT1175 will sometimes be powered from switching regulators that generate the unregulated or quasi-regulated input voltage. This voltage will contain high frequency ripple that must be rejected by the linear regulator. Special care was taken with the LT1175 to maximize high frequency ripple rejection, but as with any micropower design, rejection is strongly affected by ripple frequency. The graph in the Typical Performance Characteristics section shows 60dB rejection at 1kHz, but only 15dB rejection at 100kHz for the 5V part. Photographs in Figures 4a and 4b show actual output ripple waveforms with square wave and triwave input ripple. ILOAD = Maximum load current Example: LT1175S8 with ILOAD = 200mA, VOUT = 5V, VIN = 7V, TA = 60°C. Maximum die temperature for the LT1175S8 is 125°C. Thermal resistance from Table 2 is found to be 80°C/W. Die Temperature = 60 + 80 (0.2A)(8 – 5) = 108°C Maximum Power Dissipation = 125 – 60 = 0.81W 80 Maximum Continuous 125 – 60 + 5 = 9V = Input Voltage 80 0.2 (for Thermal Considerations) () Output Voltage Reversal The LT1175 is designed to tolerate an output voltage reversal of up to 2V. Reversal might occur, for instance, if the output was shorted to a positive 5V supply. This would almost surely destroy IC devices connected to the negative output. Reversal could also occur during startup if the positive supply came up first and loads were connected between the positive and negative supplies. For these reasons, it is always good design practice to add a reverse biased diode from each regulator output to ground to limit output voltage reversal. The diode should be rated to handle full negative load current for start-up situations, or the short-circuit current of the positive supply if supply-to-supply shorts must be tolerated. Input Voltage Lower Than Output Linear Technology’s positive low dropout regulators LT1121 and LT1129, will not draw large currents if the input voltage is less than the output. These devices use a lateral PNP power transistor structure that has 40V emitter base breakdown voltage. The LT1175, however, uses an NPN power transistor structure that has a parasitic diode OUTPUT 20mV/DIV COUT = 4.7µF TANT COUT = 1µF TANT INPUT RIPPLE 100mV/DIV f = 50kHz 5µs/DIV 1175 F04a Figure 4a. OUTPUT 100mV/DIV COUT = 4.7µF TANT COUT = 1µF TANT INPUT RIPPLE 100mV/DIV f = 100kHz 2µs/DIV 1175 F04b Figure 4b. 1175fe  LT1175 applicaTions inForMaTion To estimate regulator output ripple under different conditions, the following general comments should be helpful: 1. Output ripple at high frequency is only weakly affected by load current or output capacitor size for medium to heavy loads. At very light loads (