LT1185

LT1185 Low Dropout Regulator FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low Resistance Pass Transistor: 0.25Ω Dropout Voltage: 0.75V at 3A ±1% Reference Voltage Accurate Programmable Current Limit Shutdown Capability Internal Reference Available Full Remote Sense Low Quiescent Current: 2.5mA Good High Frequency Ripple Rejection Available in 5-Lead TO-220 and DD Packages The LT1185 uses a saturation-limited NPN transistor as the pass element. This device gives the linear dropout characteristics of a FET pass element with significantly less die area. High efficiency is maintained by using special anti-saturation circuitry that adjusts base drive to track load current. The “on resistance” is typically 0.25Ω. Accurate current limit is programmed with a single 1/8W external resistor, with a range of zero to three amperes. A second, fixed internal limit circuit prevents destructive currents if the programming current is accidentally overranged. Shutdown of the regulator output is guaranteed when the program current is less than 1µA, allowing external logic control of output voltage. The LT1185 has all the protection features of previous LTC regulators, including power limiting and thermal shutdown. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. DESCRIPTIO The LT®1185 is a 3A low dropout regulator with adjustable current limit and remote sense capability. It can be used as a positive output regulator with floating input or as a standard negative regulator with grounded input. The output voltage range is 2.5V to 25V, with ± 1% accuracy on the internal reference voltage. TYPICAL APPLICATIO 5V, 3A Regulator with 3.5A Current Limit + + 2µF TANT RLIM* 4.3k REF GND FB 2.37k + 2µF TANT VIN – VOUT (V) VIN 6V TO 16V – VIN LT1185 VOUT *CURRENT LIMIT = 15k/RLIM = 3.5A U U + 2.67k VOUT 5V AT 3A LT1185 • TA01 Dropout Voltage 1.6 1.4 1.2 1.0 TJ = 25°C 0.8 0.6 0.4 0.2 0 0 1 2 LOAD CURRENT (A) LT1185 • TA02 TJ = 125°C – TJ = – 55°C 3 4 1185ff 1 LT1185 ABSOLUTE AXI U RATI GS Input Voltage .......................................................... 35V Input-Output Differential ......................................... 30V FB Voltage ................................................................ 7V REF Voltage .............................................................. 7V Output Voltage ........................................................ 30V Output Reverse Voltage ............................................ 2V Operating Ambient Temperature Range LT1185C ............................................... 0°C to 70°C LT1185I ............................................. – 40°C to 85°C LT1185M (OBSOLETE) .................... – 55°C to 125°C *See Application Section for details on calculating Operation Junction Temperature PACKAGE/ORDER I FOR ATIO BOTTOM VIEW GND 1 FB 2 VIN (CASE) 3 4 VOUT TAB IS VIN REF K PACKAGE 4-LEAD TO-3 METAL CAN θJC MAX = 2.5°C/ W, θJA = 35°C/W TJMAX = 150°C, θJA = 30°C/W OBSOLETE PACKAGE ORDER PART NUMBER LT1185MK ORDER PART NUMBER LT1185CQ LT1185IQ ORDER PART NUMBER LT1185CT LT1185IT Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C. Adjustable version, VIN = 7.4V, VOUT = 5V, IOUT = 1mA, RLIM = 4.02k, unless otherwise noted. PARAMETER Reference Voltage (At FB Pin) Reference Voltage Tolerance (At FB Pin) (Note 2) VIN – VOUT = 5V, VOUT = VREF 1mA ≤ IOUT ≤ 3A VIN – VOUT = 1.2V to VIN = 30V P ≤ 25W (Note 6), VOUT = 5V TMIN ≤ TJ ≤ TMAX (Note 9) Feedback Pin Bias Current Droput Voltage (Note 3) VOUT = VREF IOUT = 0.5A, VOUT = 5V IOUT = 3A, VOUT = 5V ● CONDITIONS 2 U U W WW U W (Note 1) Operating Junction Temperature Range* Control Section LT1185C ............................................. 0°C to 125°C LT1185I .......................................... – 40°C to 125°C LT1185M (OBSOLETE) ................... – 55°C to 150°C Power Transistor Section LT1185C ............................................. 0°C to 150°C LT1185I .......................................... – 40°C to 150°C LT1185M (OBSOLETE) ................... – 55°C to 175°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C FRONT VIEW 5 4 3 2 1 Q PACKAGE 5-LEAD PLASTIC DD REF VOUT VIN FB GND TAB IS VIN FRONT VIEW 5 4 3 2 1 T PACKAGE 5-LEAD PLASTIC TO-220 REF VOUT VIN FB GND θJC MAX = 2.5°C/ W, θJA = 50°C/W MIN TYP 2.37 0.3 1 MAX ±1 ± 2.5 UNITS V % % ● 0.7 0.20 0.67 2 0.37 1.00 µA V V 1185ff LT1185 ELECTRICAL CHARACTERISTICS PARAMETER Load Regulation (Note 7) Line Regulation (Note 7) Minimum Input Voltage Internal Current Limit (See Graph for Guaranteed Curve) (Note 12) The ● denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C. Adjustable version, VIN = 7.4V, VOUT = 5V, IOUT = 1mA, RLIM = 4.02k, unless otherwise noted. CONDITIONS IOUT = 5mA to 3A VIN – VOUT = 1.5V to 10V, VOUT = 5V VIN – VOUT = 1V to 20V, VOUT = 5V IOUT = 1A (Note 4), VOUT = VREF IOUT = 3A 1.5V ≤ VIN – VOUT ≤ 10V VIN – VOUT = 15V VIN – VOUT = 20V VIN – VOUT = 30V ● ● ● ● ● MIN TYP 0.05 0.002 4.0 4.3 MAX 0.3 0.01 UNITS % %/V V V 3.3 3.1 2.0 1.0 0.2 3.6 3.0 1.7 0.4 15k 0.02 ILIM 0.04 ILIM 2.5 25 10 4.2 4.4 4.2 2.6 1.0 A A A A A A•Ω External Current Limit Programming Constant External Current Limit Error Quiescent Supply Current Supply Current Change with Load REF Pin Shutoff Current Thermal Regulation (See Applications Information) Reference Voltage Temperature Coefficient Thermal Resistance Junction to Case 5k ≤ RLIM ≤ 15k, VOUT = 1V (Note 11) 1A ≤ ILIM ≤ 3A RLIM = 15k • A/ILIM IOUT = 5mA, VOUT = VREF 4V ≤ VIN ≤ 25V (Note 5) VIN – VOUT = VSAT (Note 10) VIN – VOUT ≥ 2V VIN – VOUT = 10V IOUT = 5mA to 2A (Note 8) TO-3 Control Area Power Transistor TO-220 Control Area Power Transistor ● ● ● ● ● 0.06 ILIM + 0.03 0.09 ILIM + 0.05 3.5 40 25 7 0.014 0.01 1 3 1 3 A A mA mA/A mA/A µA %/W %/°C °C/W °C/W °C/W °C/W 0.4 2 0.005 0.003 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Reference voltage is guaranteed both at nominal conditions (no load, 25°C) and at worst-case conditions of load, line, power and temperature. An intermediate value can be calculated by adding the effects of these variables in the actual application. See the Applications Information section of this data sheet. Note 3: Dropout voltage is tested by reducing input voltage until the output drops 1% below its nominal value. Tests are done at 0.5A and 3A. The power transistor looks basically like a pure resistance in this range so that minimum differential at any intermediate current can be calculated by interpolation; VDROPOUT = 0.25V + 0.25Ω • IOUT. For load current less than 0.5A, see graph. Note 4: “Minimum input voltage” is limited by base emitter voltage drive of the power transistor section, not saturation as measured in Note 3. For output voltages below 4V, “minimum input voltage” specification may limit dropout voltage before transistor saturation limitation. Note 5: Supply current is measured on the ground pin, and does not include load current, RLIM, or output divider current. Note 6: The 25W power level is guaranteed for an input-output voltage of 8.3V to 17V. At lower voltages the 3A limit applies, and at higher voltages the internal power limiting may restrict regulator power below 25W. See graphs. Note 7: Line and load regulation are measured on a pulse basis with a pulse width of ≈ 2ms, to minimize heating. DC regulation will be affected by thermal regulation and temperature coefficient of the reference. See Applications Information section for details. Note 8: Guaranteed by design and correlation to other tests, but not tested. Note 9: TJMIN = 0°C for the LT1185C, – 40°C for LT1185I, and –55°C for the LT1185M. Power transistor area and control circuit area have different maximum junction temperatures. Control area limits are TJMAX = 125°C for the LT1185C and LT1185I and 150°C for the LT1185M. Power area limits are 150°C for LT1185C and LT1185I and 175°C for LT1185M. Note 10: VSAT is the maximum specified dropout voltage; 0.25V + 0.25 • IOUT. Note 11: Current limit is programmed with a resistor from REF pin to GND pin. The value is 15k/ILIM. Note 12: For VIN – VOUT = 1.5V; VIN = 5V, VOUT = 3.5V. VOUT = 1V for all other current limit tests. 1185ff 3 LT1185 TYPICAL PERFOR A CE CHARACTERISTICS Internal Current Limit 5 12 10 8 6 4 VOUT = 5V 2 0 ILOAD = 0 TJ = 25°C *DOES NOT INCLUDE REF CURRENT OR OUTPUT DIVIDER CURRENT 4 OUTPUT CURRNT (A) GUARANTEED LIMIT 3 TYPICAL GROUND PIN CURRENT (mA) VOLTAGE (V) 2 GUARANTEED LIMIT TEST POINTS 0 1 0 25 5 15 20 10 INPUT-OUTPUT DIFFERENTIAL (V) Ground Pin Current 160 140 TJ = 25°C RATIO VOUT/VIN (dB) 120 CURRENT (mA) 100 80 60 40 20 0 0 1 2 LOAD CURRENT (A) LT1185 • TPC04 REGULATOR JUST AT DROPOUT POINT Load Transient Response 10 COUT = 2.2µF, ESR = 1Ω COUT = 2.2µF, ESR = 2Ω VOUT = 5V IOUT = 1A ∆ILOAD 0.1A tr,f ≤ 100ns IMPEDANCE (Ω) 100mV 0 2 4 4 UW LT1185 • TPC01 Quiescent Ground Pin Current* 2.41 2.40 2.39 2.38 2.37 2.36 2.35 2.34 Feedback Pin Voltage Temperature Drift 30 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35 2.33 –50 –25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) LT1185 • TPC03 LT1185 • TPC02 Ripple Rejection vs Frequency –100 –80 ALL OUTPUT VOLTAGES WITH 0.05µF ACROSS R2 VOUT = 5V VIN – VOUT = 1.5V –60 –40 VIN – VOUT = 5V –20 3 4 0 100 1k 10k 100k FREQUENCY (Hz) 1M LT1185 • TPC05 Output Impedance OUTPUT IMPEDANCE IS SET BY OUTPUT CAPACITOR ESR IN THIS REGION 1 0.1 0.01 VOUT = 5V IOUT = 1A COUT = 2.2µF 0.001 1k 10k 100k FREQUENCY (Hz) 1M LT1183 • TPC07 6 8 10 TIME (µs) 12 14 16 LT1185 • TPC06 1185ff LT1185 APPLICATIO S I FOR ATIO Block Diagram A simplified block diagram of the LT1185 is shown in Figure 1. A 2.37V bandgap reference is used to bias the input of the error amplifier A1, and the reference amplifier A2. A1 feeds a triple NPN pass transistor stage which has the two driver collectors tied to ground so that the main pass transistor can completely saturate. This topology normally has a problem with unlimited current in Q1 and Q2 when the input voltage is less than the minimum required to create a regulated output. The standard “fix” for this problem is to insert a resistor in series with Q1 and Q2 collectors, but this resistor must be low enough in value to supply full base current for Q3 under worst-case VREF 2.37V A2 D2 A5 – + I1 2µA D1 300mV VIN U conditions, resulting in very high supply current when the input voltage is low. To avoid this situation, the LT1185 uses an auxiliary emitter on Q3 to create a drive limiting feedback loop which automatically adjusts the drive to Q1 so that the base drive to Q3 is just enough to saturate Q3, but no more. Under saturation conditions, the auxiliary emitter is acting like a collector to shunt away the output current of A1. When the input voltage is high enough to keep Q3 out of saturation, the auxiliary emitter current drops to zero even when Q3 is conducting full load current. GND RLIM (EXTERNAL) REF FB W + – UU – A1 Q4 + Q1 D4 D3 Q2 Q3 A4 A3 VOUT + R1 350Ω – + – R2 0.055Ω LT1185 • BD 200mV Figure 1. Block Diagram 1185ff 5 LT1185 APPLICATIO S I FOR ATIO Amplifier A2 is used to generate an internal current through Q4 when an external resistor is connected from the REF pin to ground. This current is equal to 2.37V divided by RLIM. It generates a current limit sense voltage across R1. The regulator will current limit via A4 when the voltage across R2 is equal to the voltage across R1. These two resistors essentially form a current “amplifier” with a gain of 350/0.055 = 6,360. Good temperature drift is inherent because R1 and R2 are made from the same diffusions. Their ratio, not absolute value, determines current limit. Initial accuracy is enhanced by trimming R1 slightly at wafer level. Current limit is equal to 15kΩ/RLIM. D1 and I1 are used to guarantee regulator shutdown when REF pin current drops below 2µA. A current less than 2µA through Q4 causes the +input of A5 to go low and shut down the regulator via D2. A3 is an internal current limit amplifier which can override the external current limit. It provides “goof proof” protection for the pass transistor. Although not shown, A3 has a nonlinear foldback characteristic at input-output voltages above 12V to guarantee safe area protection for Q3. See the graph, Internal Current Limit in the Typical Performance Characteristics of this data sheet. Setting Output Voltage The LT1185 output voltage is set by two external resistors (see Figure 2). Internal reference voltage is trimmed to 2.37V so that a standard 1% 2.37k resistor (R1) can be used to set divider current at 1mA. R2 is then selected from: R2 = (VOUT – 2.37) R1 VREF for R1 = 2.37k and VREF = 2.37V, this reduces to: R2 = VOUT – 2.37k suggested values of 1% resistors are shown. VOUT 5V 5.2V 6V 12V 15V R2 WHEN R1 = 2.37k 2.67k 2.87k 3.65k 9.76k 12.7k 6 U Output Capacitor The LT1185 has a collector output NPN pass transistor, which makes the open-loop output impedance much higher than an emitter follower. Open-loop gain is a direct function of load impedance, and causes a main-loop “pole” to be created by the output capacitor, in addition to an internal pole in the error amplifier. To ensure loop stability, the output capacitor must have an ESR (effective series resistance) which has an upper limit of 2Ω, and a lower limit of 0.2 divided by the capacitance in µF. A 2µF output capacitor, for instance, should have a maximum ESR of 2Ω, and a minimum of 0.2/2 = 0.1Ω. These values are easily encompassed by standard solid tantalum capacitors, but occasionally a solid tantalum unit will have abnormally high ESR, especially at very low temperatures. The suggested 2µF value shown in the circuit applications should be increased to 4.7µF for – 40°C and – 55°C designs if the 2µF units cannot be guaranteed to stay below 2Ω at these temperatures. Although solid tantalum capacitors are suggested, other types can be used if they meet the ESR requirements. Standard aluminum electrolytic capacitors need to be upward of 25µF in general to hold 2Ω maximum ESR, especially at low temperatures. Ceramic, plastic film, and monolithic capacitors have a problem with ESR being too low. These types should have a 1Ω carbon resistor in series to guarantee loop stability. The output capacitor should be located close to the regulator (≤ 3") to avoid excessive impedance due to lead inductance. A six inch lead length (2 • 3") will generate an extra 0.8Ω inductive reactance at 1MHz, and unity-gain frequency can be up to that value. For remote sense applications, the capacitor should still be located close to the regulator. Additional capacitance can be added at the remote sense point, but the remote capacitor must be at least 2µF solid tantalum. It cannot be a low ESR type like ceramic or mylar unless a 0.5Ω to 1Ω carbon resistor is added in series with the capacitor. Logic boards with multiple low ESR bypass capacitors should have a solid tantalum unit added in parallel whose value is approximately five times the combined value of low ESR capacitors. 1185ff W UU LT1185 APPLICATIO S I FOR ATIO Large output capacitors (electrolytic or solid tantalum) will not cause the LT1185 to oscillate, but they will cause a damped “ringing” at light load currents where the ESR of the capacitor is several orders of magnitude lower than the load resistance. This ringing only occurs as a result of transient load or line conditions and normally causes no problems because of its low amplitude (≤ 25mV). Heat Sinking The LT1185 will normally be used with a heat sink. The size of the heat sink is determined by load current, input and output voltage, ambient temperature, and the thermal resistance of the regulator, junction-to-case (θJC). The LT1185 has two separate values for θJC: one for the power transistor section, and a second, lower value for the control section. The reason for two values is that the power transistor is capable of operating at higher continuous temperature than the control circuitry. At low power levels, the two areas are at nearly the same temperature, and maximum temperature is limited by the control area. At high power levels, the power transistor will be at a significantly higher temperature than the control area and its maximum operating temperature will be the limiting factor. To calculate heat sink requirements, you must solve a thermal resistance formula twice, one for the power transistor and one for the control area. The lowest value obtained for heat sink thermal resistance must be used. In these equations, two values for maximum junction temperature and junction-to-case thermal resistance are used, as given in Electrical Specifications. (TJMAX – TAMAX) – θJC – θCHS. P θHS = Maximum heat sink thermal resistance θJC = LT1185 junction-to-case thermal resistance θCHS = Case-to-heat sink (interface) thermal resistance, including any insulating washers TJMAX = LT1185 maximum operating junction temperature TAMAX = Maximum ambient temperature in customers application P = Device dissipaton I = (VIN – VOUT) (IOUT) + OUT (VIN) 40 θHS = U Example: A commercial version of the LT1185 in the TO-220 package is to be used with a maximum ambient temperature of 60°C. Output voltage is 5V at 2A. Input voltage can vary from 6V to 10V. Assume an interface resistance of 1°C/W. First solve for control area, where the maximum junction temperature is 125°C for the TO-220 package, and θJC = 1°C/W: P = (10V – 5V) (2A) + 2A (10V) = 10.5W 40 125°C – 60°C – 1°C/W – 1°C/W = 4.2°C/W θHS = 10.5W Next, solve for power transistor limitation, with TJMAX = 150°C, θJC = 3°C/W: θHS = 150 – 60 – 3 – 1 = 4.6°C/W 10.5 W UU The lowest number must be used, so heat sink resistance must be less than 4.2°C/W. Some heat sink data sheets show graphs of heat sink temperature rise vs power dissipation instead of listing a value for thermal resistance. The formula for θHS can be rearranged to solve for maximum heat sink temperature rise: ∆THS = TJMAX – TAMAX – P(θJC + θCHS) Using numbers from the previous example: ∆THS = 125°C – 60 – 10.5(1 + 1) = 44°C control section ∆THS = 150°C – 60 – 10.5(3 + 1) = 48°C power transistor The smallest rise must be used, so heat sink temperature rise must be less than 44°C at a power level of 10.5W. For board level applications, where heat sink size may be critical, one is often tempted to use a heat sink which barely meets the requirements. This is permissible if correct assumptions were made concerning maximum ambient temperature and power levels. One complicating 1185ff 7 LT1185 APPLICATIO S I FOR ATIO factor is that local ambient temperature may be somewhat higher because of the point source of heat. The consequences of excess junction temperature include poor reliability, especially for plastic packages, and the possibility of thermal shutdown or degraded electrical characteristics. The final design should be checked in situ with a thermocouple attached to the regulator case under worstcase conditions of high ambient, high input voltage and full load. What About Overloads? IC regulators with thermal shutdown, like the LT1185, allow heat sink designs which concentrate on worst-case “normal” conditions and ignore “fault” conditions. An output overload or short may force the regulator to exceed its maximum junction temperature rating, but thermal shutdown is designed to prevent regulator failure under these conditions. A word of caution however; thermal shutdown temperatures are typically 175°C in the control portion of the die and 180°C to 225°C in the power transistor section. Extended operation at these temperatures can cause permanent degradation of plastic encapsulation. Designs which may be subjected to extended periods of overload should either use the hermetic TO-3 package or increase heat sink size. Foldback current limiting can be implemented to minimize power levels under fault conditions. External Current Limit The LT1185 requires a resistor to set current limit. The value of this resistor is 15k divided by the desired current limit (in amps). The resistor for 2A current limit would be 15k/2A = 7.5k. Tolerance over temperature is ±10%, so current limit is normally set 15% above maximum load current. Foldback limiting can be employed if short-circuit current must be lower than full load current (see Typical Applications). The LT1185 has internal current limiting which will override external current limit if power in the pass transistor is excessive. The internal limit is ≈ 3.6A with a foldback characteristic which is dependent on input-output voltage, not output voltage per se (see Typical Performace Characteristics). 8 U Ground Pin Current Ground pin current for the LT1185 is approximately 2mA plus IOUT/40. At IOUT = 3A, ground pin current is typically 2mA + 3/40 = 77mA. Worst case guarantees on the ratio of IOUT to ground pin current are contained in the Electrical Specifications. Ground pin current can be important for two reasons. It adds to power dissipation in the regulator and it can affect load/line regulation if a long line is run from the ground pin to load ground. The additional power dissipation is found by multiplying ground pin current by input voltage. In a typical example, with VIN = 8V, VOUT = 5V and IOUT = 2A, the LT1185 will dissipate (8V – 5V)(2A) = 6W in the pass transistor and (2A/40)(8V) = 0.4W in the internal drive circuitry. This is only a 1.5% efficiency loss, and a 6.7% increase in regulator power dissipation, but these values will increase at higher output voltages. Ground pin current can affect regulation as shown in Figure 2. Parasitic resistance in the ground pin lead will create a voltage drop which increases output voltage as load current is increased. Similarly, output voltage can decrease as input voltage increases because the “IOUT/40” component of ground pin current drops significantly at higher input-output differentials. These effects are small enough to be ignored for local regulation applications, but + + PARASITIC LEAD RESISTANCES ra VIN RLIM REF GND FB – rb + IGND R1* 2.37k LOAD VOUT W UU – R2 VIN LT1185 VOUT – LT1185 • F02 *R1 SHOULD BE CONNECTED DIRECTLY TO GROUND LEAD, NOT TO THE LOAD, SO THAT ra ≈ 0Ω. THIS LIMITS THE OUTPUT VOLTAGE ERROR TO (IGND)(rb). ERRORS CREATED BY ra ARE MULTIPLIED BY (1 + R2/R1). NOTE THAT VOUT INCREASES WITH INCREASING GROUND PIN CURRENT. R2 SHOULD BE CONNECTED DIRECTLY TO LOAD FOR REMOTE SENSING Figure 2. Proper Connection of Positive Sense Lead 1185ff LT1185 APPLICATIO S I FOR ATIO for remote sense applications, they may need to be considered. Ground lead resistance of 0.4Ω would cause an output voltage error of up to (3A/40)(0.4Ω) = 30mV, or 0.6% at VOUT = 5V. Note that if the sense leads are connected as shown in Figure 2, with ra ≈ 0Ω, this error is a fixed number of millivolts, and does not increase as a function of DC output voltage. Shutdown Techniques The LT1185 can be shut down by open-circuiting the REF pin. The current flowing into this pin must be less than 0.4µA to guarantee shutdown. Figure 3 details several ways to create the “open” condition, with various logic levels. For variations on these schemes, simply remember that the voltage on the REF pin is 2.4V negative with respect to the ground pin. Output Overshoot Very high input voltage slew rate during start-up may cause the LT1185 output to overshoot. Up to 20% overshoot could occur with input voltage ramp-up rate exceeding 1V/µs. This condition cannot occur with normal 50Hz 5V Logic, Positive Regulated Output + RLIM† 4k REF GND FB LT1185 VOUT VIN R2 R1 + VOUT + R5 300k VIN LT1185 • F3a R7 2.4k† R6 30k – *CMOS LOGIC † FOR HIGHER VALUES OF RLIM, MAKE R7 = (RLIM)(0.6) Figure 3. Shutdown Techniques U to 400Hz rectified AC inputs because parasitic resistance and inductance will limit rate of rise even if the power switch is closed at the peak of the AC line voltage. This assumes that the switch is in the AC portion of the circuit. If instead, a switch is placed directly in the regulator input so that a large filter capacitor is precharged, fast input slew rates will occur on switch closure. The output of the regulator will slew at a rate set by current limit and output capacitor size; dVdt = ILIM/COUT. With ILIM = 3.6A and COUT = 2.2µF, the output will slew at 1.6V/µs and overshoot can occur. This overshoot can be reduced to a few hundred millivolts or less by increasing the output capacitor to 10µF and/or reducing current limit so that output slew rate is held below 0.5V/µs. A second possibility for creating output overshoot is recovery from an output short. Again, the output slews at a rate set by current limit and output capacitance. To avoid overshoot, the ratio ILIM/COUT should be less than 0.5 × 106. Remember that load capacitance can be added to COUT for this calculation. Many loads will have multiple supply bypass capacitors that total more than COUT. 5V Logic, Negative Regulated Output 5V 5V * W UU “HI” = OUTPUT “OFF” 3 EA 1N4148 Q1 2N3906 Q1 2N3906 R4 33k RLIM REF GND FB VIN – VIN LT1185 VOUT LT1185 • F03b 1185ff 9 LT1185 APPLICATIO S I FOR ATIO Thermal Regulation IC regulators have a regulation term not found in discrete designs because the power transistor is thermally coupled to the reference. This creates a shift in the output voltage which is proportional to power dissipation in the regulator. ∆VOUT = P(K1 + K2 θJA) = (IOUT)(VIN – VOUT)(K1 + K2 θJA) K1 and K2 are constants. K1 is a fast time constant effect caused by die temperature gradients which are established within 50ms of a power change. K1 is specified on the data sheet as thermal regulation, in percent per watt. K2 is a long time constant term caused by the temperature drift of the regulator reference voltage. It is also specified, but in percent per degree centigrade. It must be multiplied by overall thermal resistance, junction-to-ambient, θJA. As an example, assume a 5V regulator with an input voltage of 8V, load current of 2A, and a total thermal resistance of 4°C/W, including junction-to-case, (use control area specification), interface, and heat sink resistance. K1 and K2, respectively, from the data sheet are 0.014%/W and 0.01%/°C. ∆VOUT = (2A)(8V – 5V)(0.014 + 0.01 • 4) = 0.32% 10 U This shift in output voltage could be in either direction because K1 and K2 can be either positive or negative. Thermal regulation is already included in the worst case reference specification. Output Voltage Reversal Some IC regulators suffer from a latch-up state when their output is forced to a reverse voltage of as little as one diode drop. The latch-up state can be triggered without a fault condition when the load is connected to an opposite polarity supply instead of to ground. If the second supply is turned on first, it will pull the output of the first supply to a reverse voltage through the load. The first supply may then latch off when turned on. This problem is particularly annoying because the diode clamps which should always be used to protect against polarity reversal do not usually stop the latch-up problem. The LT1185 is designed to allow output reverse polarity of several volts without damage or latch-up, so that a simple diode clamp can be used. 1185ff W UU LT1185 TYPICAL APPLICATIO S Foldback Current Limiting + R3 15k R4 5.36k R1 2.37k VIN 2µF TANT GND VOUT (NORMALIZED) + Q1 2N3906 REF FB – VIN LT1185 VOUT LT1185 • TA03a Auxiliary + 12V Low Dropout Regulator for Switching Supply * RLIM R1 2.37k GND FB VIN LT1185 VOUT R2 9.76k 12V REGULATED AUXILIARY PRIMARY *DIODE CONNECTION INDICATES A FLYBACK SWITCHING TOPOLOGY, BUT FORWARD CONVERTERS MAY ALSO BE USED U + 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 ISHORT-CIRCUIT = 15k R3 IOUT LT1185 • TA03b IFULL LOAD = 15k + 10.8k R4 R3 + 2µF TANT VOUT R2 2.61k – 0 + REF + * 5V MAIN OUTPUT + 5V CONTROL LT1185 • TA04 1185ff 11 LT1185 TYPICAL APPLICATIO S Low Input Voltage Monitor Tracks Dropout Characteristics + + VIN C2 2.2µF TANT R3 360k 4k REF R5* 0.01Ω R4** 1k VIN LT1185 VOUT GND FB R2 2.6k R1 2.37k – R6** 1k OPTIONAL HYSTERESIS ≈2M 3 + LT1006† + V 7 – V– 4 LT1185 • TA05 2 Time Delayed Start-Up + D3 † R3** 15k D2 RLIM*** VIN D1 TIME CONSTANTS (t)* + – Q1** C2 2.2µF C3* VIN REF ALL DIODES 1N4148 *SEE CHART FOR DELAY TIME VERSUS (C3)(R3//RLIM) PRODUCT **FOR LONG DELAY TIMES, REPLACE D2 WITH 2N3906 TRANSISTOR AND USE R3 ONLY FOR CALCULATING DELAY TIME. R3 CAN INCREASE TO 100k ***ILIM IS ≈11k/RLIM, INSTEAD OF 15k, BECAUSE OF VOLTAGE DROP IN D1. TEMPERATURE COEFFICIENT OF ILIM WILL BE ≈ 0.11%/°C, SO ADEQUATE MARGIN MUST BE ALLOWED FOR COLD OPERATION † D3 PROVIDES FAST RESET OF TIMING. INPUT MUST DROP TO A LOW VALUE TO RESET TIMING 12 U + *3" #26 WIRE **R4 DETERMINES TRIP POINT AT IOUT = 0 R6 DETERMINES INCREASE OF TRIP POINT AS IOUT INCREASES TRIP POINT FOR VIN = VOUT 1 + R4 • R7 + IOUT R5 • R7 R6 R3 • R6 FOR VALUES SHOWN, TRIP POINT FOR VIN IS: VOUT + 0.37V AT IOUT = 0 AND VOUT = 1.18V AT IOUT = 3A † DO NOT SUBSTITUTE. OP AMP MUST HAVE COMMON MODE RANGE EQUAL TO NEGATIVE SUPPLY + C1 2.2µF VOUT TANT ( ) – R7 27k “LOW” FOR LOW INPUT OUTPUT SWINGS FROM VIN+ TO VIN– Delay Time + R1 2.37k 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 20 15 INPUT VOLTAGE (V) 25 30 + GND FB LT1185 VOUT C1 2.2µF TANT VOUT R2 – LT1185 • TA06 R3 • RLIM *t = (R3//RLIM)(C3) = (C3) R3 + RLIM ( ) LT1185 • TA07 1185ff REF GND R6 750Ω R15 4k R17 6k R16 1k R7 500Ω R12 2k R13 2k R14 3.2k R18 2k Q18 Q19 R1 5.5k C1 10pF Q6 R8 6.5k Q17 Q9 Q15 Q16 Q7 Q8 SCHE ATIC DIAGRA R2 3k R3 3k Q3 R4 520Ω Q11 Q12 Q5 R9 2.7k Q53 R19 20k D4 Q4 R5 600Ω Q48 Q13 Q14 R53 10k Q46 C2 Q31 Q30 Q45 Q43 Q44 R52 10k Q42 Q52 Q28 Q29 R11 220Ω Q21 FB R54 4k Q22 Q49 Q47 R23 80Ω Q23 R24 6k Q24 VOUT Q41 D1 Q51 R49 700Ω Q36 Q35 Q34 Q32 R42 50k R48 2k R40 1k R43 50k R39 1k Q40 Q37 R46 8k R47 4k Q33 R45 1.3k R50 160Ω C3 30pF R44 5k C4 10pF R35 20k R34 300Ω R26 1k C5 10pF Q27 Q26 Q25 Q39 R36 20k R55 30k R38 20k R31 200Ω R38 400Ω R37 1k R28 0.055Ω VIN LT1185 • SD Q50 LT1185 R56 600Ω 10k W Q20 Q1 Q2 W 500Ω 1185ff 13 LT1185 PACKAGE DESCRIPTIO .320 – .350 (8.13 – 8.89) .760 – .775 (19.30 – 19.69) .060 – .135 (1.524 – 3.429) .420 – .480 (10.67 – 12.19) .390 – .415 (9.906 – 10.541) .147 – .155 (3.734 – 3.937) DIA .230 – .270 (5.842 – 6.858) .460 – .500 (11.684 – 12.700) .330 – .370 (8.382 – 9.398) BSC .067 (1.70) .028 – .038 (0.711 – 0.965) 14 U K Package 4-Lead TO-3 Metal Can (Reference LTC DWG # 05-08-1311) 1.177 – 1.197 (29.90 – 30.40) .655 – .675 (16.64 – 19.05) .151 – .161 (3.84 – 4.09) DIA 2 PLC .167 – .177 (4.24 – 4.49) R .038 – .043 (0.965 – 1.09) 18° 72° .490 – .510 (12.45 – 12.95) R .470 TP P.C.D. K4(TO-3) 0801 OBSOLETE PACKAGE T Package 5-Lead Plastic TO-220 (Standard) (Reference LTC DWG # 05-08-1421) .165 – .180 (4.191 – 4.572) .045 – .055 (1.143 – 1.397) .570 – .620 (14.478 – 15.748) .700 – .728 (17.78 – 18.491) .620 (15.75) TYP SEATING PLANE .152 – .202 .260 – .320 (3.861 – 5.131) (6.60 – 8.13) .095 – .115 (2.413 – 2.921) .155 – .195* (3.937 – 4.953) .013 – .023 (0.330 – 0.584) .135 – .165 (3.429 – 4.191) * MEASURED AT THE SEATING PLANE T5 (TO-220) 0801 1185ff LT1185 PACKAGE DESCRIPTIO .256 (6.502) .060 (1.524) .060 (1.524) TYP .060 (1.524) .183 (4.648) .075 (1.905) .300 (7.620) BOTTOM VIEW OF DD PAK HATCHED AREA IS SOLDER PLATED COPPER HEAT SINK +.012 .143 –.020 +0.305 3.632 –0.508 .067 (1.702) .028 – .038 BSC (0.711 – 0.965) TYP .013 – .023 (0.330 – 0.584) .420 .067 RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN INCH/(MILLIMETER) 2. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. U Q Package 5-Lead Plastic DD Pak (Reference LTC DWG # 05-08-1461) .390 – .415 (9.906 – 10.541) 15° TYP .059 (1.499) TYP .165 – .180 (4.191 – 4.572) .045 – .055 (1.143 – 1.397) .330 – .370 (8.382 – 9.398) ( +.008 .004 –.004 +0.203 0.102 –0.102 ) .095 – .115 (2.413 – 2.921) .050 ± .012 (1.270 ± 0.305) Q(DD5) 0502 ( ) .080 .420 .276 .350 .205 .565 .325 .565 .320 .090 .042 .067 .090 .042 RECOMMENDED SOLDER PAD LAYOUT FOR THICKER SOLDER PASTE APPLICATIONS 1185ff 15 LT1185 TYPICAL APPLICATIO S Logic Controlled 3A Low-Side Switch with Fault Protection 5V + VIN – NOTE: C3 IMPOVES HIGH FREQUENCY RIPPLE REJECTION BY 6dB AT VOUT = 5V, AND BY 14dB AT VOUT = 12V. C1 IS INCREASED TO 4.7µF TO ENSURE GOOD STABILTITY WHEN C3 IS USED RELATED PARTS PART NUMBER LT1085 LT1117 LT1120A LT1129 LT1175 LT1585 LT1964 DESCRIPTION 7.5A Low Dropout Regulator 800mA Low Dropout Regulator with Shutdown Micropower Regulator with Comparator and Shutdown 200mA Micropower Low Dropout Regulator 500mA Negative Low Dropout Micropower Regulator 4.6A Low Dropout Fast Transient Response Regulator 200mA, Low Noise Micropower, Negative LDO COMMENTS 1V Dropout Voltage Reverse Voltage and Reverse Current Protection 20µA Supply Current, 2.5V Reference Output 400mV Dropout Voltage, 50µA Supply Current 45µA Supply Current, Adjustable Current Limit For High Performance Microprocessors VIN: –0.9V to –20V, VOUT(MIN) = –1.21V, VDO = 0.34V, IQ = 30µA, ISD = 3µA, ThinSOT Package 1185ff 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U + RLIM 4k REF GND LOAD 1N4001 ADD FOR INDUCTIVE LOADS FB LT1185 VOUT VIN LT1185 • TA08 Improved High Frequency Ripple Rejection + C2 2.2µF TANT RLIM R1 2.37k GND FB VIN LT1185 VOUT LT1185 • TA09 REF C1 4.7µF TANT R2 C3 0.05µF VOUT – LT/LWI 0906 REV F • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 1994