LT1246

LT1246/LT1247 1MHz Off-Line Current Mode PWM and DC/DC Converter DESCRIPTIO The LT®1246/LT1247 are 8-pin, fixed frequency, current mode, pulse width modulators. These devices are designed to be improved plug compatible versions of the industry standard UC1842 PWM circuit. The LT1246/ LT1247 are optimized for off-line and DC/DC converter applications. They contain a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output stage ideally suited to driving power MOSFETs. Start-up current has been reduced to less than 250µA. Cross-conduction current spikes in the totem pole output stage have been eliminated, making 1MHz operation practical. Several new features have been incorporated. Leading edge blanking has been added to the current sense comparator. This minimizes or eliminates the filter that is normally required. Eliminating this filter allows the current sense loop to operate with minimum delays. Trims have been added to the oscillator circuit for both frequency and sink current, and both of these parameters are tightly specified. The output stage is clamped to a maximum VOUT of 18V in the on state. The output and the reference output are actively pulled low during under-voltage lockout. , LTC and LT are registered trademarks of Linear Technology Corporation. FEATURES s s s s s s s s s s s s Current Mode Operation to 1MHz 30ns Current Sense Delay < 250µA Low Start-Up Current Current Sense Leading Edge Blanking Pin Compatible with UC1842 Undervoltage Lockout with Hysteresis No Cross-Conduction Current Trimmed Bandgap Reference 1A Totem Pole Output Trimmed Oscillator Frequency and Sink Current Active Pull-Down on Reference and Output During Undervoltage Lockout 18V High Level Output Clamp APPLICATI s s S Off-Line Converters DC/DC Converters Start-Up Threshold 16V 8.4V Minimum Operating Voltage 10V 7.6V Maximum Duty Cycle 100% 100% Device LT1246 LT1247 Replaces UC1842 UC1843 BLOCK DIAGRA REFERENCE ENABLE 5V REF MAIN BIAS REFERENCE PULLDOWN OUTPUT PULLDOWN RT/CT COMPENSATION 4 1 1mA 5.6V OSCILLATOR S R 1V 2R R 5 GND 6 OUTPUT FEEDBACK 2 2.5V – + – + BLANKING ISENSE 3 U W UO UV LOCKOUT 8 7 VREF VCC 18V + 1.5V – LT1246 • BD01 1 LT1246/LT1247 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW COMP 1 FB 2 ISENSE 3 RT/CT 4 N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 100°C, θJA = 130°C/W (N8) TJMAX = 100°C, θJA = 150°C/W (S8) Supply Voltage ....................................................... 25V Output Current ...................................................... ± 1A* Output Energy (Capacitive Load per Cycle) ............. 5µJ Analog Inputs (Pins 2, 3) .............................. – 0.3 to 6V Error Amplifier Output Sink Current ..................... 10mA Power Dissipation at TA ≤ 25°C ............................... 1W Operating Junction Temperature Range LT1246C/LT1247C ............................. 0°C to 100°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C *The 1A rating for output current is based on transient switching requirements. ORDER PART NUMBER 8 7 6 5 VREF VCC OUTPUT GND LT1246CN8 LT1246CS8 LT1247CN8 LT1247CS8 S8 PART MARKING 1246 1247 Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS (Notes 1, 2) PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variation Output Noise Voltage Long-Term Stability Output Short-Circuit Current Oscillator Section Initial Accuracy Voltage Stability Temperature Stability Amplitude Clock Ramp Reset Current Error Amplifier Section Feedback Pin Input Voltage Input Bias Current Open-Loop Voltage Gain Unity-Gain Bandwidth Power Supply Rejection Ratio Output Sink Current Output Source Current VPIN 1 = 2.5V VFB = 2.5V 2 < VO < 4V TJ = 25°C 12V < VCC < 25V VPIN 2 = 2.7V, VPIN 1 = 1.1V VPIN 2 = 2.3V, VPIN 1 = 5V q q q q q q CONDITIONS IO = 1mA, TJ = 25°C 12V < VCC < 25V 1mA < IREF < 20mA Line, Load, Temperature 10Hz < F < 10kHz, TJ = 25°C TA = 125°C, 1000 Hrs. q q q MIN 4.925 TYP 5.000 3 –6 0.1 MAX 5.075 20 – 25 5.13 UNITS V mV mV mV/°C V µV mV mA kHz kHz % %/°C V q 4.87 50 5 – 30 47.5 465 – 90 50 500 – 0.05 1.7 7.9 2.42 65 1 60 2 – 0.5 6 – 0.75 8.2 2.50 90 2 25 – 180 52.5 535 1 RT = 10k, CT = 3.3nF, TJ = 25°C RT = 6.2k, CT = 500pF, TJ = 25°C 12V < VCC < 25V, TJ = 25°C TMIN < TJ < TMAX Pin 4 VOSC (Pin 4) = 2V, TJ = 25°C 8.5 2.58 –2 2 U mA V µA dB MHz dB mA mA W U U WW W LT1246/LT1247 ELECTRICAL CHARACTERISTICS PARAMETER Error Amplifier Section Output Voltage High Level Output Voltage Low Level Current Sense Section Gain Maximum Current Sense Input Threshold Power Supply Rejection Ratio Input Bias Current Delay to Output Blanking Time Blanking Override Voltage Output Section Output Low Level Output High Level Rise Time Fall Time Output Clamp Voltage Undervoltage Lockout Start-Up Threshold Minimum Operating Voltage Hysteresis PWM Maximum Duty Cycle Minimum Duty Cycle Total Device Start-Up Current Operating Current The q denotes those specifications which apply over the full operating temperature range. Note 1: Unless otherwise specified, VCC = 15V, RT = 10k, CT = 3.3nF. q q q q (Notes 1, 2) MIN q q CONDITIONS VPIN 2 = 2.3V, RL = 15k to GND VPIN 2 = 2.7V, RL = 15k to Pin 8 TYP 5.6 0.2 MAX UNITS V 5 1.1 3.15 1.10 –10 V V/V V dB µA ns ns V 2.85 0.90 3.00 1.00 70 –1 30 60 1.5 VPIN 3 < 1.1V q IOUT = 20mA IOUT = 200mA IOUT = 20mA IOUT = 200mA CL = 1nF, TJ = 25°C CL = 1nF, TJ = 25°C IO = 1mA LT1246 LT1247 LT1246 LT1247 LT1246 LT1247 TJ = 25°C TJ = 25°C q q q q 0.25 0.75 12.0 11.75 30 20 0.4 2.2 V V V V 70 60 19 17 9.0 11 8.2 ns ns V V V V V V V q 18 15 7.8 9.0 7.0 5.5 0.4 94 0 170 13 16 8.4 10 7.6 6.0 0.8 q q q q q q 100 % % 250 20 µA mA Note 2: Low duty cycle pulse techniques are used during test to maintain junction temperature close to ambient. 3 LT1246/LT1247 TYPICAL PERFOR A CE CHARACTERISTICS LT1246 Undervoltage Lockout 17 START-UP THRESHOLD 11 START-UP CURRENT (µA) 16 VCC (V) VCC (V) 15 11 MINIMUM OPERATING VOLTAGE 10 9 –50 –25 0 25 50 75 TEMPERATURE (°C) LT1246 • TPC01 Start-Up Current 200 START-UP THRESHOLD START-UP CURRENT (µA) 150 FREQUENCY CHANGE (%) ICC (mA) LT1247 100 LT1246 50 TJ = 25°C 0 0 2 4 6 8 10 12 14 16 18 VCC (V) 1246/7 TPC04 Oscillator Sink Current OSCILLATOR SINK CURRENT (mA) 8.6 8.5 8.4 8.3 8.2 8.1 8.0 7.9 7.8 VPIN 4 = 2V REFERENCE SHORT-CIRCUIT CURRENT (mA) 8.7 REFERENCE VOLTAGE (V) 7.7 –50 –25 0 25 50 75 TEMPERATURE (°C) LT1246 • TPC07 4 UW 100 100 LT1247 Undervoltage Lockout 200 180 10 Start-Up Current 160 140 120 100 80 60 40 20 9 START-UP THRESHOLD 8 MINIMUM OPERATING VOLTAGE 7 125 6 –50 –25 0 25 50 75 100 125 0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 1247 TPC02 TEMPERATURE (°C) LT1246 • TPC03 Supply Current 15 Oscillator Frequency 10 8 VCC = 15V 14 6 4 2 0 –2 –4 –6 –8 13 12 VCC = 15V RT = 10k CT = 3300pF 0 25 50 75 100 125 11 10 –50 –25 –10 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) LT1246 • TPC05 TEMPERATURE (°C) LT1246 • TPC06 Reference Short-Circuit Current 140 120 100 80 60 40 20 –50 –25 5.05 5.04 5.03 5.02 5.01 5.00 4.99 4.98 4.97 4.96 0 25 50 75 100 125 Reference Voltage IO = 1mA 125 4.95 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) LT1246 • TPC08 TEMPERATURE (°C) LT1246 • TPC09 LT1246/LT1247 TYPICAL PERFOR A CE CHARACTERISTICS Feedback Pin Input Voltage 2.55 CURRENT SENSE CLAMP VOLTAGE (V) FEEDBACK PIN INPUT VOLTAGE (V) 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 –50 –25 0 25 50 75 100 125 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 –50 –25 0 25 50 75 100 125 OUTPUT SATURATION VOLTAGE (V) 2.54 TEMPERATURE (°C) LT1246 • TPC10 Low Level Output Saturation Voltage 1.0 OUTPUT SATURATION VOLTAGE (V) OUTPUT SATURATION VOLTAGE (V) TJ = 125°C 0.5 2.5 2.0 1.5 1.0 0.5 0 0 TJ = 125°C TJ = – 55°C SUPPLY CURRENT (mA) TJ = 25°C TJ = – 55°C 0 0 100 OUTPUT SINK CURRENT (mA) LT1246 • TPC13 Error Amplifier Open-Loop Gain and Phase 100 225 GAIN 180 1.2 80 60 40 20 0 –20 10 100 1k 10k 100k 1M FREQUENCY (Hz) LT1246 • TPC16 CURRENT SENSE INPUT THRESHOLD (V) AVOL, OPEN LOOP VOLTAGE GAIN (dB) UW 200 Current Sense Clamp Voltage 1.05 1.04 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 High Level Output Saturation Voltage TJ = – 55°C TJ = 25°C TJ = 125°C 0 100 OUTPUT SOURCE CURRENT (mA) 200 LT1246 • TPC12 TEMPERATURE (°C) LT1246 • TPC11 Low Level Output Saturation Voltage During Undervoltage Lockout 4.0 3.5 3.0 13 14 Supply Current vs Oscillator Frequency 12 TJ = 25°C 11 10 5 OUTPUT SINK CURRENT (mA) 10 LT1246 • TPC14 9 10k 100k OSCILLATOR FREQUENCY (Hz) 1M LT1246 • TPC15 Current Sense Input Threshold 1.0 0.8 TJ = – 55°C 0.6 0.4 0.2 0 0 1 2 3 4 5 6 ERROR AMP OUTPUT VOLTAGE (V) LT1246 • TPC17 PHASE (DEGREES) 135 PHASE 90 45 0 –45 10M TJ =125°C TJ = 25°C 5 LT1246/LT1247 TYPICAL PERFOR A CE CHARACTERISTICS Output Deadtime vs Oscillator Frequency 60 50 40 30 500pF 20 10 100pF 0 0 100 OSCILLATOR FREQUENCY (kHz) LT1246 • TPC18* TIMING RESISTOR (kΩ) DEADTIME (%) Output Rise and Fall Time OUTPUT VOLTAGE 5V/DIV OUTPUT VOLTAGE VCC = 15V CL = 1nF TIME 50ns/DIV 1246/7 G20 OUTPUT CROSSCONDUCTION CURRENT 20mA/DIV CURRENT SENSE INPUT 1V/DIV OUTPUT VOLTAGE 5V/DIV PI FU CTI S ISENSE (Pin 3): Current Sense. This is the input to the current sense comparator. The trip point of the comparator is set by, and is proportional to, the output voltage of the Error Amplifier. RT/CT (Pin 4) : The oscillator frequency and the deadtime are set by connecting a resistor (RT) from VREF to RT/CT and a capacitor (CT) from RT/CT to GND. The rise time of the oscillator waveform is set by the RC time constant of RT and CT. The fall time, which is equal to the output deadtime, is set by a combination of the RC time constant and the oscillator sink current (8.2mA typ.). COMP (Pin 1): Compensation Pin. This pin is the output of the Error Amplifier and is made available for loop compensation. It can also be used to adjust the maximum value of the current sense clamp voltage to less than 1V. This pin can source a minimum of 0.5mA (0.8mA typ.) and sink a minimum of 2mA (4mA typ.) FB (Pin 2): Voltage Feedback. This pin is the inverting input of the Error Amplifier. The output voltage is normally fed back to this pin through a resistive divider. The noninverting input of the Error Amplifier is internally committed to a 2.5V reference point. 6 UW Timing Resistor vs Oscillator Frequency 100 100pF 200pF 500pF 5nF 2nF 1nF 1nF 2nF 10 CT =10nF 5nF VCC = 15V TJ = 25°C 1 10k 100k OSCILLATOR FREQUENCY (Hz) LT1246 • TPC19 1000 1M Current Sense Delay Output Cross-Conduction VCC = 15V CL = 1nF TIME 50ns/DIV 1246/7 G21 VCC = 15V CL = 15pF TIME 50ns/DIV 1246/7 G22 UO U U LT1246/LT1247 PI FU CTI GND (Pin 5): Ground. OUTPUT (Pin 6): Current Output. This pin is the output of a high current totem pole output stage. It is capable of driving up to ±1A of current into a capacitive load such as the gate of a MOSFET. VCC (Pin 7): Supply Voltage. This pin is the positive supply of the control IC. APPLICATI Device LT1246 LT1247 S I FOR ATIO Minimum Operating Voltage 10V 7.6V Maximum Duty Cycle 100% 100% Start-Up Threshold 16V 8.4V Replaces UC1842 UC1843 Oscillator The LT1246/LT1247 are fixed frequency current mode pulse width modulators. The oscillator frequency and the oscillator discharge current are both trimmed and tightly specified to minimize the variations in frequency and deadtime. The oscillator frequency is set by choosing a resistor and capacitor combination, RT and CT. This RC combination will determine both the frequency and the maximum duty cycle. The resistor RT is connected from VREF (pin 8) to the RT/CT pin (pin 4). The capacitor CT is connected from the RT/CT pin to ground. The charging current for CT is determined by the value of RT. The discharge current for CT is set by the difference between the current supplied by RT and the discharge current of the LT1246/LT1247. The discharge current of the device is trimmed to 8.2mA. For large values of RT discharge time will be determined by the discharge current of the device and the value of CT. As the value of RT is reduced it will have more effect on the discharge time of CT. During an oscillator cycle capacitor CT is charged to approximately 2.8V and discharged to approximately 1.1V. The output is enabled during the charge time of CT and disabled, in an off state, during the discharge time of CT. The deadtime of the circuit is equal to the discharge time of CT. The maximum duty cycle is limited by controlling the deadtime of the oscillator. There are many combinations of RT and CT that will yield a given oscillator frequency, however there is only one combination that will yield a specific U W U UO UO U U S VREF (Pin 8): Reference. This is the reference output of the IC. The reference output is used to supply charging current to the external timing resistor RT. The reference provides biasing to a large portion of the internal circuitry, and is used to generate several internal reference levels including the VFB level and the current sense clamp voltage. deadtime at that frequency. Curves of oscillator frequency and deadtime for various values of RT and CT appear in the Typical Performance Characteristics section. Frequency and deadtime can also be calculated using the following formulas: Oscillator Rise Time: tr = 0.583 • RC 3.46 • RC Oscillator Discharge Time: td = 0.0164R − 11.73 Oscillator Period: tOSC = tr + td 1 Oscillator Frequency: fOSC = t OSC t t −t Maximum Duty Cycle: DMAX = r = OSC d t OSC t OSC The above formulas will give values that will be accurate to approximately ± 5%, at the oscillator, over the full operating frequency range. This is due to the fact that the oscillator trip levels are constant versus frequency and the discharge current and initial oscillator frequency are trimmed. Some fine adjustment may be required to achieve more accurate results. Once the final RT/CT combination is selected, the oscillator characteristics will be repeatable from device to device. Note that there will be some slight differences between maximum duty cycle at the oscillator and maximum duty cycle at the output due to the finite rise and fall times of the output. Error Amplifier The LT1246/LT1247 contain a fully compensated error amplifier with a DC gain of 90dB and a unity-gain frequency of 2MHz. Phase margin at unity-gain is 80°. The noninverting input is internally committed to a 2.5V reference point derived from the 5V reference of pin 8. The 7 LT1246/LT1247 APPLICATI S I FOR ATIO inverting input (pin 2) and the output (pin 1) are made available to the user. The output voltage in a regulator circuit is normally fed back to the inverting input of the error amplifier through a resistive divider. The output of the error amplifier is made available for external loop compensation. The output current of the error amplifier is limited to approximately 0.8mA sourcing and approximately 6mA sinking. In a current mode PWM the peak switch current is a function of the output voltage of the error amplifier. In the LT1246/LT1247 the output of the error amplifier is offset by two diodes (1.4V at 25°C), divided by a factor of three, and fed to the inverting input of the current sense comparator. For output voltages less than 1.4V the duty cycle of the output stage will be zero. The maximum offset that can appear at the current sense input is limited by a 1V clamp. This occurs when the error amplifier output reaches 4.4V at 25°C. The output of the error amplifier can be clamped below 4.4V in order to reduce the maximum voltage allowed across the current sensing resistor to less than 1V. The supply current will increase by the value of the output source current when the output voltage of the error amplifier is clamped. Current Sense Comparator and PWM Latch LT1246/LT1247 are current mode controllers. Under normal operating conditions the output (pin 6) is turned on at the start of every oscillator cycle, coincident with the rising edge of the oscillator waveform. The output is then turned off when the switch current reaches a threshold level proportional to the error voltage at the output of the error amplifier. Once the output is turned off it is latched off until the start of the next cycle. The peak switch current is thus proportional to the error voltage and is controlled on a cycle by cycle basis. The peak switch current is normally sensed by placing a sense resistor in the source lead of the output MOSFET. This resistor converts the switch current to a voltage that can be fed into the current sense input. For normal operating conditions the peak inductor current, which is equal to the peak switch current, will be equal to: IPK = (V PIN1 − 1.4V (3R ) S ) 8 U During fault conditions the maximum threshold voltage at the input of the current sense comparator is limited by the internal 1V clamp at the inverting input. The peak switch current will be equal to: 1.0V IPK(MAX ) = RS In certain applications such as high power regulators it may be desirable to limit the maximum threshold voltage to less than 1V in order to limit the power dissipated in the sense resistor or to limit the short-circuit current of the regulator circuit. This can be accomplished by clamping the output of the error amplifier. A voltage level of approximately 1.4V at the error amplifier output will give a threshold voltage of 0V. A voltage level of approximately 4.4V at the output of the error amplifier will give a threshold level of 1V. Between 1.4V and 4.4V the threshold voltage will change by a factor of one third of the change in the error amplifier output voltage. The threshold voltage will be 0.333V for an error amplifier voltage of 2.4V. To reduce the maximum current sense threshold to less than 1V the error amplifier output should be clamped to less than 4.4V. Blanking A unique feature of the LT1246/LT1247 is the built-in blanking circuit at the output of the current sense comparator. A common problem with current mode PWM circuits is erratic operation due to noise at the current sense input. The primary cause of noise problems is the leading edge current spike due to transformer interwinding capacitance and diode reverse recovery time. This current spike can prematurely trip the current sense comparator causing an instability in the regulator circuit. A filter at the current sense input is normally required to eliminate this instability. This filter will in turn slow down the current sense loop. A slow current sense loop wil increase the minimum pulse width which will increase the short-circuit current in an overload condition. The LT1246/LT1247 blank (lock out) the signal at the output of the current sense comparator for a fixed amount of time after the switch is turned on. This prevents the PWM latch from tripping due to the leading edge current spike. The blanking time will be a function of the voltage at the feedback pin (pin 2). The blanking time will be 60ns for normal operat- W U UO LT1246/LT1247 APPLICATI S I FOR ATIO ing conditions (VFB = 2.5V). The blanking time goes to zero as the feedback pin is pulled to 0V. This means that the blanking time will be minimized during start-up and also during an output short-circuit fault. This blanking circuit eliminates the need for an input filter at the current sense input except in extreme cases. Eliminating the filter allows the current sense loop to operate with minimum delays, reducing peak currents during fault conditions. Undervoltage Lockout The LT1246/LT1247 incorporate an undervoltage lockout comparator which prevents the internal reference circuitry and the output from starting up until the supply voltage reaches the start-up threshold voltage. The quiescent current, below the start-up threshold, has been reduced to less than 250µA (170µA typ.). This minimizes the power loss due to the start-up resistor used in off-line converters. In undervoltage lockout both VREF (pin 8) and the Output (pin 6) are actively pulled low by Darlington connected PNP transistors. They are designed to sink a few milliamps of current and will pull down to about 1V. The pull-down transistor at the reference pin can be used to reset the external soft start capacitor. The pull-down transistor at the output eliminates the external pull-down resistor required, with earlier devices, to hold the external MOSFET gate low during undervoltage lockout. Output The LT1246/LT1247 incorporate a single high current totem pole output stage. This output stage is capable of driving up to ±1A of output current. Cross-conduction current spikes in the output totem pole have been eliminated. These devices are primarily intended for driving MOSFET switches. Rise time is typically 30ns and fall time is typically 20ns when driving a 1.0nF load. A clamp is built into the device to prevent the output from rising above 18V in order to protect the gate of the MOSFET switch. The output is actively pulled low during undervoltage lockout by a Darlington PNP. This PNP is designed to sink several milliamps and will pull the output down to approximately 1V. This active pull-down eliminates the need for the external resistor which was required in older designs. The output pin of the device connects directly to the emitter of the upper NPN drive transistor and the collector of the lower NPN drive transistor in the totem pole. The U collector of the lower transistor, which is n-type silicon, forms a p-n junction with the substrate of the device. The substate of the device is tied to ground. This junction is reverse biased during normal operation. In some applications the parasitic LC of the external MOSFET gate can ring and pull the output pin below ground. If the output pin is pulled negative by more than a diode drop, the parasitic diode formed by the collector of the output NPN and the substrate will turn on. This can cause erratic operation of the device. In these cases a Schottky clamp diode is recommended from output to ground. Reference The internal reference of the LT1246/LT1247 is a 5V Bandgap reference, trimmed to within ±1% initial tolerance. The reference is used to power the majority of the internal logic and the oscillator circuitry. The oscillator charging current is supplied from the reference. The feedback pin voltage and the clamp level for the current sense comparator are derived from the reference voltage. The reference can supply up to 20mA of current to power external circuitry. Note that using the reference in this manner, as a voltage regulator, will significantly increase the power dissipation in the device, which will reduce the operating ambient temperature range. Design/Layout Considerations LT1246/LT1247 are high speed circuits capable of generating pulsed output drive currents of up to 1A peak. The rise and fall time for the output drive current is in the range of 10ns to 20ns. High Speed circuit layout techniques must be used to insure proper operation of the devices. Do not attempt to use Proto-boards or wire-wrap techniques to breadboard high speed switching regulator circuits. They will not work properly. Printed circuit layouts should include separate ground paths for the voltage feedback network, oscillator capacitor, and switch drive current. These ground paths should be connected together directly at the ground pin (pin 5) of the LT1246/LT1247. This will minimize noise problems due to pulsed ground pin currents. VCC should be bypassed, with a minimum of 0.1µF, as close to the device as possible. High current paths should be kept short and they should be separated from the feedback voltage network with shield traces if possible. W U UO 9 LT1246/LT1247 TYPICAL APPLICATI VREF 8 R COMP 1 FEEDBACK 2 1mA 5V REF C ISENSE 3 VREF 8 RT/CT 4 R2 100k COMP 1 FEEDBACK 2 C R1 1mA – + 2.5V 1.67 VCLAMP ≈ R2 +1 R1 ( 10 UO ( S External Clock Synchronization VREF 8 RT RT/CT 4 OSCILLATOR 5V REF EXTERNAL SYNC INPUT 0.01µF CT 47Ω D1 D1 IS REQUIRED IF THE SYNC AMPLITUDE IS LARGE ENOUGH TO PULL THE BOTTOM OF CT MORE THAN 300mV BELOW GROUND. LT1246 • TA05 Soft Start 5.6V 1V – + 2.5V 2R R – + 1.5V + – LT1246 • TA06 Adjustable Clamp Level with Soft Start REFERENCE ENABLE REFERENCE PULLDOWN OUTPUT PULLDOWN OSCILLATOR 5.6V 1V S R 18V 2R R 5V REF MAIN BIAS UV LOCKOUT VCC 7 VIN OUTPUT 6 GND 5 – + BLANKING + 1.5V – ISENSE 3 RS IPK (MAX) ≈ VCLAMP RS WHERE: O ≤ VCLAMP ≤ 1.0V tSOFT START = – ln 1 – VC 3 • VCLAMP C R1 R2 R1 + R2 LT1246 • TA07 LT1246/LT1247 TYPICAL APPLICATI VREF 8 RT RT/CT 4 COMP CT 1 FEEDBACK 2 1mA – + 2.5V VREF 8 RT TO VOUT RSLOPE CT RT/CT 4 COMP 1 Rf 2 FEEDBACK 1mA Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UO – + S Slope Compensation at ISENSE Pin REFERENCE ENABLE REFERENCE PULLDOWN OUTPUT PULLDOWN OSCILLATOR 5.6V 1V S R 18V 2R R 5V REF MAIN BIAS UV LOCKOUT VCC 7 VIN OUTPUT 6 GND 5 – + BLANKING + 1.5V – ISENSE 3 RS LT1246 • TA08 Slope Compensation at Error Amp REFERENCE ENABLE 5V REF MAIN BIAS REFERENCE PULLDOWN UV LOCKOUT VCC OUTPUT PULLDOWN 7 OSCILLATOR S R 18V 2R R OUTPUT 6 5.6V 1V GND 5 – + BLANKING + 1.5V 2.5V – ISENSE 3 LT1246 • TA09 11 LT1246/LT1247 PACKAGE DESCRIPTIO 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.015 (0.380) MIN ( +0.025 0.325 –0.015 8.255 +0.635 –0.381 ) 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm). 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 0.053 – 0.069 (1.346 – 1.752) 0.016 – 0.050 0.406 – 1.270 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). RELATED PARTS PART NUMBER LT1105 LT1170/LT1171/LT1172 LT1241-5 LT1248/LT1249 LT1372 LT1376 LT1377 LT1431 DESCRIPTION Off-Line Switching Regulator Controller High Efficiency 100kHz Switching Regulators 500kHz Low Power Current Mode Pulse Width Modulator Power Factor Controllers High Efficiency 500kHz Boost Switching Regulator 1.5A, 500kHz Step-Down Switching Regulator 1MHz High Efficiency Boost Switching Regulator Programmable Reference 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 U Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.400* (10.160) MAX 8 7 6 5 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 N8 0694 S8 Package 8-Lead Plastic SOIC 8 0.004 – 0.010 (0.101 – 0.254) 0.228 – 0.244 (5.791 – 6.197) 0.189 – 0.197* (4.801 – 5.004) 7 6 5 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC 0.150 – 0.157* (3.810 – 3.988) 1 2 3 4 SO8 0294 LT/GP 0395 5K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1992