LT1368CN8

LT1366/LT1367 LT1368/LT1369 Dual and Quad Precision Rail-to-Rail Input and Output Op Amps DescripTion The LT®1366/LT1367/LT1368/LT1369 are dual and quad bipolar op amps which combine rail-to-rail input and output operation with precision specifications. These op amps maintain their characteristics over a supply range of 1.8V to 36V. Operation is specified for 3V, 5V and ±15V supplies. Input offset voltage is typically 150µV, with an open-loop gain AVOL of 1 million while driving a 10k load. Common mode rejection is typically 90dB over the full rail-to-rail input range, and supply rejection is 110dB. The LT1366/LT1367 have conventional compensation which assures stability for capacitive loads of 1000pF or less. The LT1368/LT1369 have compensation that requires a 0.1µF output capacitor, which improves the amplifier’s supply rejection and reduces output impedance at high frequencies. The output capacitor’s filtering action reduces high frequency noise, which is beneficial when driving A/D converters. The LT1366/LT1368 are available in plastic 8-pin PDIP and 8-lead SO packages with the standard dual op amp pinout. The LT1367/LT1369 feature the standard quad pinout, which is available in a plastic 14-lead SO package. These devices can be used as plug-in replacements for many standard op amps to improve input/output range and precision. FeaTures n n n n n n n n n n n n Input Common Mode Range Includes Both Rails Output Swings Rail-to-Rail Low Input Offset Voltage: 150µV High Common Mode Rejection Ratio: 90dB High AVOL: >1V/µV Driving 10k Load Low Input Bias Current: 10nA Wide Supply Range: 1.8V to ±15V Low Supply Current: 375µA per Amplifier High Output Drive: 30mA 400kHz Gain-Bandwidth Product Slew Rate: 0.13V/µs Stable for Capacitive Loads Up to 1000pF applicaTions n n n n Rail-to-Rail Buffer Amplifiers Low Voltage Signal Processing Supply Current Sensing at Either Rail Driving A/D Converters L, LT, LTC, LTM, Over-The-Top, Linear Technology and the Linear logo are registered trademarks and C-Load is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion Positive Supply Rail Current Sense VCC R1 200 Output Saturation Voltage vs Load Current 1000 SATURATION VOLTAGE (mV) VOUT – VS 100 POSITIVE RAIL NEGATIVE RAIL Rs 0.2 – 1/2 LT1366 – Q1 TP0610L 1/2 LT1366 + ILOAD LOAD R2 20k + VO = ILOAD • RS = ILOAD • 20 () R2 R1 10 1366 TA01 1 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 1366 TA02 1366fb  LT1366/LT1367 LT1368/LT1369 absoluTe MaxiMuM raTings (Note 1) Total Supply Voltage (V+ to V–) ................................ 36V Input Current....................................................... ±15mA Output Short-Circuit Duration (Note 2) ........ Continuous Operating Temperature Range .............. –40°C to 85°C Specified Temperature Range ...................... 0°C to 70°C Junction Temperature ......................................... 150°C Storage Temperature Range ................. –65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C pin conFiguraTion LT1366/LT1368 TOP VIEW OUT A 1 –IN A 2 +IN A 3 V– 4 A B N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 130°C/W (N8) TJMAX = 150°C, θJA = 190°C/W (S8) 8 V+ 7 OUT B 6 –IN B 5 +IN B OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7 B C A D LT1367/LT1369 TOP VIEW 14 OUT D 13 –IN D 12 +IN D 11 V– 10 +IN C 9 – IN C 8 OUT C S PACKAGE 14-LEAD PLASTIC SO TJMAX = 150°C, θJA = 150°C/W aVailable opTions PRODUCT NUMBER LT1366 LT1367 LT1368 LT1369 NUMBER OF OP AMPS 2 4 2 4 LOAD CAPACITANCE 0pF < CL < 1000pF 0pF < CL < 1000pF CL = 0.1µF CL = 0.1µF MAX VOS (25°C) AT VS = 5V, 0V 475µV 800µV 475µV 800µV ORDER PART NUMBER PLASTIC (N) LT1366CN8 LT1368CN8 SURFACE MOUNT(S) LT1366CS8 LT1367CS LT1368CS8 LT1369CS orDer inForMaTion LEAD FREE FINISH LT1366CN8#PBF LT1366CS8#PBF LT1367CS#PBF LT1368CN8#PBF LT1368CS8#PBF LT1369CS#PBF TAPE AND REEL LT1366CN8#TRPBF LT1366CS8#TRPBF LT1367CS#TRPBF LT1368CN8#TRPBF LT1368CS8#TRPBF LT1369CS#TRPBF PART MARKING 1366 1366 LT1367CS 1368 1368 LT1369CS PACKAGE DESCRIPTION 8-Lead PDIP 8-Lead Plastic S0 14-Lead Plastic S0 8-Lead PDIP 8-Lead Plastic S0 14-Lead Plastic S0 SPECIFIED TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 1366fb  LT1366/LT1367 LT1368/LT1369 elecTrical characTerisTics SYMBOL VOS PARAMETER Input Offset Voltage (LT1366/LT1368) Input Offset Voltage (LT1367/LT1369) ∆VOS Input Offset Voltage Shift (LT1366/LT1368) Input Offset Voltage Match (Channel to Channel) Input Offset Voltage Shift (LT1367/LT1369) Input Offset Voltage Match (Channel to Channel) IB ∆IB IOS ∆IOS Input Bias Current Input Bias Current Shift Input Offset Current Input Offset Current Shift Input Bias Current Match (Channel to Channel) en in CIN AVOL CMRR Input Noise Voltage Density Input Noise Current Density Input Capacitance Large-Signal Voltage Gain VO = 50mV to 4.8V, RL = 10k 250 81 75 77 71 90 84 Common Mode Rejection Ratio (LT1366/LT1368) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Common Mode Rejection Ratio (LT1367/LT1369) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Power Supply Rejection Ratio PSRR Match (Channel to Channel) (Note 4) Output Voltage Swing Low VS = 2.0V to 12V, VCM = VO = 0.5V VS = 2.0V to 12V, VCM = VO = 0.5V No Load ISINK = 0.5mA ISINK = 2.5mA No Load ISINK = 0.5mA ISINK = 2.5mA (Note 2) AV = 1000 AV = 1000 AV = 1, VSTEP = 4V to 0.1% TA = 25°C; VS = 5V, 0V; VCM = 2.5V; VO = 2.5V, unless otherwise noted. MIN TYP 150 150 150 150 150 250 150 250 0 –35 10 –10 20 1 0.3 1 0 0 1 1 29 0.07 12 2000 90 90 90 90 105 100 6 40 110 VCC – 0.012 VCC – 0.004 VCC – 0.100 VCC – 0.050 VCC – 0.250 VCC – 0.150 ±15 ±30 340 0.4 0.16 30 520 12 70 200 MAX 475 475 800 700 400 700 650 1600 35 0 70 12 12 12 12 12 UNITS µV µV µV µV µV µV µV µV nA nA nA nA nA nA nA nA nV/√Hz pA/√Hz pF V/mV dB dB dB dB dB dB mV mV mV V V V mA µA MHz MHz µs CONDITIONS VCM = VCC VCM = VEE VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VEE, VCC (Notes 4, 5) VCM = VEE to VCC VCM = VEE, VCC (Notes 4, 5) VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VCC (Note 4) VCM = VEE (Note 4) f = 1kHz f = 1kHz PSRR VOL VOH ISC IS GBW tS Output Voltage Swing High Short-Circuit Current Supply Current per Amplifier Gain-Bandwidth Product (LT1366/LT1367) Gain-Bandwidth Product (LT1368/LT1369) Settling Time (LT1366/LT1367) 1366fb  LT1366/LT1367 LT1368/LT1369 elecTrical characTerisTics SYMBOL VOS PARAMETER Input Offset Voltage (LT1366/LT1368) The l denotes the specifications which apply over the specified temperature range of 0°C < TA < 70°C. VS = 5V, 0V; VCM = 2.5V, VO = 2.5V, unless otherwise noted. CONDITIONS VCM = VCC VCM = VEE Input Offset Voltage (LT1367/LT1369) VCM = VCC VCM = VEE Input Offset Voltage Drift (Note 3) Input Offset Voltage Shift (LT1366/LT1368) VCM = VEE to VCC Input Offset Voltage Match (Channel to Channel) VCM = VEE, VCC (Notes 4, 5) Input Offset Voltage Shift (LT1367/LT1369) VCM = VEE to VCC Input Offset Voltage Match (Channel to Channel) VCM = VEE, VCC (Notes 4, 5) Input Bias Current VCM = VCC VCM = VEE Input Bias Current Shift VCM = VEE to VCC VCM = VCC VCM = VEE Input Offset Current Shift VCM = VEE to VCC Input Bias Current Match (Channel to Channel) VCM = VCC (Note 4) VCM = VEE (Note 4) Large-Signal Voltage Gain VO = 50mV to 4.8V, RL = 10k Common Mode Rejection Ratio (LT1366/LT1368) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Common Mode Rejection Ratio (LT1367/LT1369) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Power Supply Rejection Ratio VS = 2.3V to 12V, VCM = VO = 0.5V VS = 2.3V to 12V, VCM = VO = 0.5V PSRR Match (Channel to Channel) (Note 4) Output Voltage Swing Low No Load ISINK = 0.5mA ISINK = 2.5mA Output Voltage Swing High No Load ISOURCE = 0.5mA ISOURCE = 2.5mA Short-Circuit Current (Note 2) Supply Current per Amplifier Input Offset Current MIN l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l VOS TC ∆VOS IB ∆IB IOS ∆IOS 0 –45 TYP 200 200 200 200 2 200 250 200 250 15 –10 25 MAX 575 575 950 900 6 425 900 675 1900 45 0 90 15 15 15 15 15 UNITS µV µV µV µV µV/°C µV µV µV µV nA nA nA nA nA nA nA nA V/mV dB dB dB dB dB dB mV mV mV V V V mA µA AVOL CMRR PSRR VOL VOH ISC IS 2 1 2 0 2 0 1 250 2000 80 87 74 87 77 87 71 87 88 105 82 100 9 45 120 VCC – 0.014 VCC – 0.005 VCC – 0.110 VCC – 0.055 VCC – 0.300 VCC – 0.180 ±12.5 385 14 80 230 540 TA = 25°C; VS = 3V, 0V; VCM = 1.5V; VO = 1.5V, unless otherwise noted. SYMBOL VOS PARAMETER Input Offset Voltage (LT1366/LT1368) Input Offset Voltage (LT1367/LT1369) ∆VOS Input Offset Voltage Shift (LT1366/LT1368) Input Offset Voltage Match (Channel to Channel) Input Offset Voltage Shift (LT1367/LT1369) Input Offset Voltage Match (Channel to Channel) Input Bias Current Input Bias Current Shift Input Offset Current CONDITIONS VCM = VCC VCM = VEE VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VEE, VCC (Notes 4, 5) VCM = VEE to VCC VCM = VEE, VCC (Notes 4, 5) VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VCC VCM = VEE MIN TYP 150 150 150 150 150 250 150 250 10 –10 20 1.0 0.3 MAX 475 475 850 750 400 700 650 1700 35 0 70 12 12 UNITS µV µV µV µV µV µV µV µV nA nA nA nA nA IB ∆IB IOS 0 –35 1366fb  LT1366/LT1367 LT1368/LT1369 elecTrical characTerisTics SYMBOL ∆IOS PARAMETER Input Offset Current Shift Input Bias Current Match (Channel to Channel) TA = 25°C; VS = 3V, 0V; VCM = 1.5V; VO = 1.5V, unless otherwise noted. TYP 1 0 1 0 1 250 1500 77 86 71 86 73 86 67 86 6 40 110 VCC – 0.012 VCC – 0.004 VCC – 0.100 VCC – 0.050 VCC – 0.250 VCC – 0.150 ±10 ±20 330 MIN MAX 12 12 12 UNITS nA nA nA V/mV dB dB dB dB mV mV mV V V V mA µA AVOL CMRR VOL VOH ISC IS CONDITIONS VCM = VEE to VCC VCM = VCC (Note 4) VCM = VEE (Note 4) Large-Signal Voltage Gain VO = 50mV to 2.8V, RL = 10k Common Mode Rejection Ratio (LT1366/LT1368) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Common Mode Rejection Ratio (LT1367/LT1369) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Output Voltage Swing Low No Load ISINK = 0.5mA ISINK = 2.5mA Output Voltage Swing High No Load ISINK = 0.5mA ISINK = 2.5mA Short-Circuit Current (Note 2) Supply Current per Amplifier 12 70 200 500 The l denotes the specifications which apply over the specified temperature range of 0°C < TA < 70°C. VS = 3V, 0V; VCM = 1.5V, VO = 1.5V, unless otherwise noted. SYMBOL VOS CONDITIONS VCM = VCC VCM = VEE Input Offset Voltage (LT1367/LT1369) VCM = VCC VCM = VEE Input Offset Voltage Shift (LT1366/LT1368) VCM = VEE to VCC Input Offset Voltage Match (Channel to Channel) VCM = VEE, VCC (Notes 4, 5) Input Offset Voltage Shift (LT1367/LT1369) VCM = VEE to VCC Input Offset Voltage Match (Channel to Channel) VCM = VEE, VCC (Notes 4, 5) Input Offset Voltage Drift (Note 3) Input Bias Current VCM = VCC VCM = VEE Input Bias Current Shift VCM = VEE to VCC VCM = VCC VCM = VEE Input Offset Current Shift VCM = VEE to VCC Input Bias Current Match (Channel to Channel) VCM = VCC (Note 4) VCM = VEE (Note 4) Large-Signal Voltage Gain VO = 50mV to 2.8V, RL = 10k Common Mode Rejection Ratio (LT1366/LT1368) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Common Mode Rejection Ratio (LT1367/LT1369) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Output Voltage Swing Low No Load ISINK = 0.5mA ISINK = 2.5mA Output Voltage Swing High No Load ISOURCE = 0.5mA ISOURCE = 2.5mA Short-Circuit Current (Note 2) Supply Current per Amplifier Input Offset Current PARAMETER Input Offset Voltage (LT1366/LT1368) MIN l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ∆VOS VOS TC IB ∆IB IOS ∆IOS 0 –45 TYP 200 200 200 200 200 250 200 250 2 15 –10 25 MAX 575 575 950 900 425 900 675 1900 6 45 0 90 15 15 15 15 15 UNITS µV µV µV µV µV µV µV µV µV/°C nA nA nA nA nA nA nA nA V/mV dB dB dB dB mV mV mV V V V mA µA 1366fb AVOL CMRR VOL VOH ISC IS 2 1 2 0 2 0 1 150 1500 76 83 70 83 72 83 66 83 9 45 120 VCC – 0.014 VCC – 0.005 VCC – 0.110 VCC – 0.055 VCC – 0.300 VCC – 0.180 ±10 375 14 80 230 520  LT1366/LT1367 LT1368/LT1369 elecTrical characTerisTics SYMBOL VOS PARAMETER Input Offset Voltage (LT1366/LT1368) Input Offset Voltage (LT1367/LT1369) ∆VOS Input Offset Voltage Shift (LT1366/LT1368) Input Offset Voltage Match (Channel to Channel) Input Offset Voltage Shift (LT1367/LT1369) Input Offset Voltage Match (Channel to Channel) IB ∆IB IOS ∆IOS Input Bias Current Input Bias Current Shift Input Offset Current Input Offset Current Shift Input Bias Current Match (Channel to Channel) CIN AVOL Input Capacitance Large-Signal Voltage Gain Channel Separation SR Slew Rate (LT1366/LT1367) Slew Rate (LT1368/LT1369) CMRR VO = –14.7V to 14.7V, RL = 10k VO = –10V to 10V, RL = 2k VO = –10V to 10V, RL = 2k AV = –1, RL = Open, VO = ±10V, Measured at VO = ±5V AV = –1, RL = Open, VO = ±10V, Measured at VO = ±5V 95 89 93 87 90 84 1000 500 120 TA = 25°C, VS = ±15V, VCM = 0V, VO = 0V, unless otherwise noted. MIN TYP 200 200 200 200 150 300 150 300 0 –35 10 –10 20 1.0 0.3 1 0 0 1 1 7.1 10000 10000 135 0.13 0.065 106 106 106 106 110 105 VEE + 0.006 VEE + 0.040 VEE + 0.240 VCC – 0.012 VCC – 0.004 VCC – 0.100 VCC – 0.050 VCC – 0.800 VCC – 0.400 ±30 ±75 370 550 VEE + 0.012 VEE + 0.070 VEE + 0.500 MAX 700 700 1000 900 500 1300 650 2000 35 0 70 12 12 12 12 12 UNITS µV µV µV µV µV µV µV µV nA nA nA nA nA nA nA nA pF V/mV V/mV dB V/µs V/µs dB dB dB dB dB dB V V V V V V mA µA CONDITIONS VCM = VCC VCM = VEE VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VEE, VCC (Notes 4, 5) VCM = VEE to VCC VCM = VEE, VCC (Notes 4, 5) VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VCC VCM = VEE VCM = VEE to VCC VCM = VCC (Note 4) VCM = VEE (Note 4) Common Mode Rejection Ratio (LT1366/LT1368) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Common Mode Rejection Ratio (LT1367/LT1369) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Power Supply Rejection Ratio VS = ±5V to ±15V VS = ±5V to ±15V (Note 4) PSRR Match (Channel to Channel) Output Voltage Swing Low No Load ISINK = 0.5mA ISINK = 10mA No Load ISINK = 0.5mA ISINK = 2.5mA (Note 2) PSRR VOL VOH ISC IS Output Voltage Swing High Short-Circuit Current Supply Current per Amplifier 1366fb  LT1366/LT1367 LT1368/LT1369 elecTrical characTerisTics SYMBOL VOS PARAMETER Input Offset Voltage (LT1366/LT1368) The l denotes the specifications which apply over the specified temperature range of 0°C < TA < 70°C. VS = ±15V, VCM = 0V, VO = 0V, unless otherwise noted. CONDITIONS VCM = VCC VCM = VEE Input Offset Voltage (LT1367/LT1369) VCM = VCC VCM = VEE Input Offset Voltage Shift (LT1366/LT1368) VCM = VEE to VCC Input Offset Voltage Match (Channel to Channel) VCM = VEE, VCC (Notes 4, 5) Input Offset Voltage Shift (LT1367/LT1369) VCM = VEE to VCC Input Offset Voltage Match (Channel to Channel) VCM = VEE, VCC (Notes 4, 5) Input Offset Voltage Drift (Note 3) Input Bias Current VCM = VCC VCM = VEE Input Bias Current Shift VCM = VEE to VCC VCM = VCC VCM = VEE Input Offset Current Shift VCM = VEE to VCC Input Bias Current Match (Channel to Channel) VCM = VCC (Note 4) VCM = VEE (Note 4) Large-Signal Voltage Gain VO = –14.7V to 14.7V, RL = 10k VO = –10V to 10V, RL = 2k Channel Separation VO = –10V to 10V, RL = 2k Common Mode Rejection Ratio (LT1366/LT1368) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Common Mode Rejection Ratio (LT1367/LT1369) VCM = VEE to VCC VCM = VEE to VCC (Note 4) CMRR Match (Channel to Channel) Power Supply Rejection Ratio VS = ±5V to ±15V VS = ±5V to ±15V (Note 4) PSRR Match (Channel to Channel) Output Voltage Swing Low No Load ISINK = 0.5mA ISINK = 10mA Output Voltage Swing High No Load ISOURCE = 0.5mA ISOURCE = 10mA Short-Circuit Current (Note 2) Supply Current per Amplifier Input Offset Current MIN l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ∆VOS VOS TC IB ∆IB IOS ∆IOS 0 –45 TYP 250 250 250 250 200 300 200 300 2 15 –10 25 MAX 850 850 1150 1000 525 1500 750 2300 8 45 0 90 UNITS µV µV µV µV µV µV µV µV µV/°C nA nA nA nA nA nA nA nA V/mV V/mV dB dB dB dB dB dB dB V V V V V V mA µA AVOL CMRR PSRR VOL VOH ISC IS 2 15 1 15 2 15 0 2 15 0 1 15 750 6000 500 6000 110 135 95 103 89 103 92 103 86 103 80 105 75 100 VEE + 0.009 VEE + 0.014 VEE + 0.045 VEE + 0.080 VEE + 0.300 VEE + 0.600 VCC – 0.014 VCC – 0.005 VCC – 0.11 VCC – 0.055 VCC – 0.95 VCC – 0.500 ±30 415 575 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Applies to short circuits to ground for all split supplies and for single supplies less than 20V. Short circuits to either supply for supplies greater than 20V total may permanently damage the part. A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 3: This parameter is not 100% tested. Note 4: Matching parameters are the difference between amplifiers A and D and between B and C on the LT1367/LT1369; between the two amplifiers on the LT1366/LT1368. Note 5: Input offset voltage match is the difference in offset voltage between amplifiers measured at both VCM = VEE and VCM = VCC. 1366fb  LT1366/LT1367 LT1368/LT1369 (The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.) PNP Stage VOS Distribution (LT1366/LT1368) 30 25 PERCENT OF UNITS (%) 20 15 10 5 0 –350 –250 –150 –50 50 150 250 INPUT OFFSET VOLTAGE (µV) N-PACKAGE VS = 5V, 0V VCM = 0V PERCENT OF UNITS (%) 30 25 20 15 10 5 0 –350 –250 –150 –50 50 150 250 INPUT OFFSET VOLTAGE (µV) Typical perForMance characTerisTics NPN Stage VOS Distribution (LT1366/LT1368) N-PACKAGE VS = 5V, 0V VCM = 5V ∆VOS-Shift Between PNP and NPN Stages (LT1366/LT1368) 30 25 PERCENT OF UNITS (%) 20 15 10 5 0 –350 –250 –150 –50 50 150 250 INPUT OFFSET VOLTAGE (µV) N-PACKAGE VS = 5V, 0V VCM = 0V TO 5V 350 350 350 LT1366 TPC03 LT1366 TPC02 LT1366 TPC01 Supply Current vs Temperature 500 SUPPLY CURRENT PER AMPLIFIER (µA) SUPPLY CURRENT PER AMPLIFIER (µA) VS = ±15V VS = 5V, 0V 600 500 400 300 200 100 0 Supply Current vs Supply Voltage 20 15 INPUT BIAS CURRENT (nA) TA = 125°C TA = 25°C TA = –55°C 10 5 0 –5 –10 –15 0 4 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) 36 Input Bias Current vs Common Mode Voltage VS = 5V, 0V TA = –55°C TA = 25°C TA = 125°C 400 300 200 100 0 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) LT1366 TPC04 –20 –2 –1 0 4 3 5 2 1 COMMON MODE VOLTAGE (V) 6 LT1366 TPC05 LT1366 TPC06 Input Bias Current vs Temperature 50 40 SATURATION VOLTAGE (mV) 1000 Output Saturation Voltage vs Load Current (Output High) 1000 Output Saturation Voltage vs Load Current (Output Low) 20 10 0 –10 –20 –30 –40 VS = 5V, 0V, VCM = 5V VS = ±15V, VCM = 15V VS = 5V, 0V, VCM = 0V VS = ±15V, VCM = –15V 100 TA = 85°C SATURATION VOLTAGE (mV) INPUT BIAS CURRENT (nA) 30 100 TA = 85°C TA = 25°C 10 TA = –55°C 10 TA = –55°C TA = 25°C –50 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) LT1366 TPC07 1 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 LT1366 TPC08 1 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 LT1366 TPC09 1366fb  LT1366/LT1367 LT1368/LT1369 Typical perForMance characTerisTics Minimum Supply Voltage 200 CHANGE IN OFFSET VOLTAGE (µV) OUTPUT VOLTAGE (200nV/DIV) (The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.) 0.1Hz to 10Hz Output Voltage Noise VS = ±2.5V VCM = 0V NOISE VOLTAGE nV/√Hz TA = 70°C TA = 85°C 70 60 50 40 30 20 10 0 TIME (1s/DIV) LT1366 TPC11 Noise Voltage Spectrum VS = 5V, 0V 150 100 VCM = 4V VCM = 2.5V 50 TA = 25°C TA = –55°C NONFUNCTIONAL 1 3 2 4 TOTAL SUPPLY VOLTAGE (V) 5 LT1366 TPC10 0 1 10 100 FREQUENCY (Hz) 1000 LT1366 TPC12 Noise Current Spectrum 0.8 0.7 CURRENT NOISE (pA/√Hz) 0.6 VOLTAGE GAIN (dB) 0.5 0.4 0.3 0.2 0.1 0 1 VCM = 4V 10 100 FREQUENCY (Hz) 1000 LT1366 TPC13 Gain and Phase Shift vs Frequency (LT1366/LT1367) 70 60 50 40 30 20 10 0 VS = ±2.5V PHASE GAIN 140 120 100 VOLTAGE GAIN (dB) 80 60 40 20 0 PHASE SHIFT (DEG) 50 40 30 20 10 0 –10 –20 –30 –40 –50 Gain and Phase Shift vs Frequency (LT1368/LT1369) VS = ±2.5V CL = 0.1µF 140 120 100 80 60 PHASE 40 20 GAIN 0 PHASE SHIFT (DEG) VS = 5V, 0V VCM = 2.5V –10 –20 –30 1k 10k 100k 1M FREQUENCY (Hz) –20 –40 –60 10M LT1366 TPC14 –20 –40 1k 10k 100k 1M FREQUENCY (Hz) –60 10M LT1366 TPC15 CMRR vs Frequency (LT1366 and LT1367) 120 COMMON MODE REJECTION RATIO (dB) 110 100 90 80 70 60 50 40 30 20 1k 10k 100k FREQUENCY (Hz) 1M LT1366 TPC16 PSRR vs Frequency (LT1366/LT1367) 120 POWER SUPPLY REJECTION RATIO (dB) 100 80 POSITIVE SUPPLY 60 40 20 0 NEGATIVE SUPPLY 1k 10k 100k FREQUENCY (Hz) 1M LT1366 TPC17 PSRR vs Frequency (LT1368/LT1369) 120 POWER SUPPLY REJECTION RATIO (dB) 100 80 60 40 20 NEGATIVE SUPPLY 0 1k 10k 100k FREQUENCY (Hz) 1M LT1366 TPC18 VS = ±2.5V VS = ±2.5V VS = ±2.5V POSITIVE SUPPLY 1366fb  LT1366/LT1367 LT1368/LT1369 (The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.) Gain-Bandwidth and Phase Margin vs Supply Voltage (LT1366/LT1367) 500 450 400 FREQUENCY (kHz) 350 300 250 200 150 100 50 0 0 5 15 20 10 SUPPLY VOLTAGE (V) 25 PHASE MARGIN GBW 60 54 CHANNEL SEPARATION (dB) 48 PHASE MARGIN (DEG) 42 36 30 24 18 12 6 0 30 LT1366 TPC19 Typical perForMance characTerisTics Channel Separation vs Frequency –50 –60 –70 –80 –90 LT1368/LT1369 VS = ±15V VOUT = ±1VP-P RL = 2k INPUT VOLTAGE (µV) 20 15 10 5 0 –5 –10 –15 10 100 1k FREQUENCY (Hz) 10k LT1366 TPC20 Open-Loop Gain VS = ±15V RL = 2k –100 –110 –120 RL = 10k –130 –140 –150 LT1366/LT1367 –20 5 –20 –15 –10 –5 0 10 OUTPUT VOLTAGE (V) 15 20 LT1366 TPC21 Capacitive Load Handling (LT1366/LT1367) 80 70 60 OVERSHOOT (%) OVERSHOOT (%) 50 40 30 20 10 0 10 AV = 10 100 1k 10k CAPACITIVE LOAD (pF) 100k LT1366 TPC22 Overshoot vs Load Current (LT1368/LT1369) 60 50 40 30 20 10 0 –10 VS = ±2.5V AV = 1 CL = 0.22µF 60 50 OVERSHOOT (%) 40 30 20 10 Overshoot vs Load Current (LT1368/LT1369) VS = ±15V AV = 1 CL = 0.22µF CL = 0.047µF CL = 0.1µF VS = 5V, 0V CL = 0.047µF CL = 0.1µF AV = 1 AV = 5 –5 0 5 LOAD CURRENT (mA) 10 LT1366 TPC23 0 –10 –5 0 5 LOAD CURRENT (mA) 10 LT1366 TPC24 Slew Rate vs Supply Voltage 0.20 AV = –1 CHANGE IN OFFSET VOLTAGE (µV) 80 60 40 20 0 –20 –40 –60 –80 Warm-Up Drift vs Time 10 S8 PACKAGE VS = ±15V THD + NOISE (%) S8 PACKAGE VS = ±2.5V THD + Noise vs Peak-to-Peak Voltage f = 1kHz RL = 10k (ALL CURVES) 0.18 SLEW RATE (V/µs) 1 0.16 0.1 VS = ±1.5V AV = 1 0.01 VS = ±1.5V AV = –1 VS = ±2.5V AV = 1 VS = ±2.5V AV = –1 4 5 LT1366 TPC27 0.14 N8 PACKAGE VS = ±2.5V N8 PACKAGE VS = ±15V 0 15 30 45 60 75 90 105 120 135 150 TIME AFTER POWER-UP (SEC) LT1366 TPC26 0.12 0.10 0 4 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) 36 0.001 0 1 2 3 VIN(P-P) (V) LT1366 TPC25 1366fb 0 LT1366/LT1367 LT1368/LT1369 Typical perForMance characTerisTics THD + Noise vs Frequency 1 VS = ±1.5V VIN = 2VP-P RL = 10k 5mV/DIV VS = ±15V UNITY GAIN 5V/DIV (The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.) Large-Signal Response (LT1366/LT1367) Small-Signal Response (LT1366/LT1367) THD + NOISE (%) 0.1 0V 0.01 AV = 1 AV = –1 VS = ±15V UNITY GAIN 100µs/DIV LT1366 TPC29 2µs/DIV LT1366 TPC30 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 LT1366 TPC28 applicaTions inForMaTion Rail-to-Rail Operation The LT1366 family differs from conventional op amps in the design of both the input and output stages. Figure 1 shows a simplified schematic of the amplifier. The input stage consists of two differential amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4, which are active over different V+ portions of the input common mode range. Lateral devices are used in both input stages, eliminating the need for clamps across the input pins. Each input stage is trimmed for offset voltage. A complementary output configuration (Q23 through Q26) is employed to create an output stage with rail-to-rail swing. The amplifier is fabricated on Linear D4 I1 Q10 Q11 Q5 V– D5 Q17 D6 Q21 D7 Q24 Q23 Q16 V– V– C1 OUT V– IN+ IN– Q12 Q6 D3 V– D1 Q3 Q4 Q1 Q2 D2 Q7 Q8 V+ Q9 Q13 D7 Q14 Q15 V+ CC V+ V+ C2 V+ Q20 Q22 Q18 Q19 Q25 Q26 D8 – 300mV LT1366 FO1 Figure 1. LT1366 Simplified Schematic Diagram 1366fb  LT1366/LT1367 LT1368/LT1369 applicaTions inForMaTion Technology’s proprietary complementary bipolar process, which ensures very similar DC and AC characteristics for the output devices Q24 and Q26. A simple comparator Q5 steers current from current source I1 between the two input stages. When the input common mode voltage VCM is near the negative supply, Q5 is reverse biased, and I1 becomes the tail current for the PNP differential pair Q1/Q2. At the other extreme, when VCM is within about 1.3V from the positive supply, Q5 diverts I1 to the current mirror D3/Q6, which furnishes the tail current for the NPN differential pair Q3/Q4. The collector currents of the two input pairs are combined in the second stage, consisting of Q7 through Q11. Most of the voltage gain in the amplifier is contained in this stage. Differential amplifier Q14/Q15 buffers the output of the second stage, converting the output voltage to differential currents. The differential currents pass through current mirrors D4/Q17 and D5/Q16, and are converted to differential voltages by Q18 and Q19. These voltages are also buffered and applied to the output Darlington pairs Q23/Q24 and Q25/Q26. Capacitors C1 and C2 form local feedback loops around the output devices, lowering the output impedance at high frequencies. Input Offset Voltage Since the amplifier has two input stages, the input offset voltage changes depending upon which stage is active. The input offsets are random, but bounded voltages. When the amplifier switches between stages, offset voltages may go up, down, or remain flat; but will not exceed the guaranteed limits. This behavior is illustrated in three distribution plots of input offset voltage in the Typical Performance Characteristics section. Overdrive Protection Two circuits prevent the output from reversing polarity when the input voltage exceeds the common mode range. When the noninverting input exceeds the positive supply by approximately 300mV, the clamp transistor Q12 (Figure 1) turns on, pulling the output of the second stage low, which forces the output high. For inputs below the negative supply, diodes D1 and D2 turn on, overcoming the saturation of the input pair Q1/Q2. When overdriven, the amplifier draws input current that exceeds the normal input bias current. Figures 2 and 3 show some typical overdrive currents as a function of input voltage. The input current must be less than 1mA of positive overdrive or less than 7mA of negative overdrive, for the phase reversal protection to work properly. When the amplifier is severely overdriven, an external resistor should be used to limit the overdrive current. In addition to overdrive protection, the amplifier is protected against ESD strokes up to 4kV on all pins. 110 100 INPUT BIAS CURRENT (nA) 90 80 70 60 50 40 30 20 10 0 –500 –300 –100 VS 100 300 500 T = 85°C T = 70°C MEASURED AS A FOLLOWER + – T = 25°C T = –55°C COMMON MODE VOLTAGE RELATIVE TO POSITIVE SUPPLY (mV) LT1366 F02 Figure 2. Input Bias Current vs Common Mode Voltage 0 –10 INPUT BIAS CURRENT (nA) –20 –30 –40 –50 –60 –70 –80 –90 MEASURED AS A FOLLOWER + – T = –55°C T = 25°C T = 70°C T = 85°C –100 –110 –800 –200 200 –600 –400 VS COMMON MODE VOLTAGE RELATIVE TO NEGATIVE SUPPLY (mV) LT1366 F03 Figure 3. Input Bias Current vs Common Mode Voltage 1366fb  LT1366/LT1367 LT1368/LT1369 applicaTions inForMaTion Improved Supply Rejection in the LT1368/LT1369 The LT1368/LT1369 are variations of the LT1366/LT1367 offering greater supply rejection and lower high frequency output impedance. The LT1368/LT1369 require a 0.1µF load capacitance for compensation. The output capacitance forms a filter, which reduces pickup from the supply and lowers the output impedance. This additional filtering is helpful in mixed analog/digital systems with common supplies, or systems employing switching supplies. Filtering also reduces high frequency noise, which may be beneficial when driving A/D converters. Figure 4 shows the outputs of the LT1366/LT1368 perturbed by a 200mVP-P 50kHz square wave added to the positive supply. The LT1368’s power supply rejection is about ten times greater than that of the LT1366 at 50kHz. Note the 5-to-1 scale change in the output voltage traces. The tolerance of the external compensation capacitor is not critical. The plots of Overshoot vs Load Current in the Typical Performance Characteristics section illustrate the effect of a capacitive load. V+ (AC) 100mV/DIV V+ (AC) 100mV/DIV VOUT 100mV/DIV VOUT 20mV/DIV 2µs/DIV LT1366 F04a 2µs/DIV LT1366 F04b Figure 4a. LT1366 Power Supply Rejection Test Figure 4b. LT1368 Power Supply Rejection Test Typical applicaTions Buffering A/D Converters Figure 5 shows the LT1368 driving an LTC®1288 2-channel micropower A/D converter (ADC). The LTC1288 can accommodate voltage references and input signals equal to the supply rails. The sampling nature of this ADC eliminates the need for an external sample-and-hold, but may call for a drive amplifier because of the ADC’s 12µs settling requirement. The LT1368’s rail-to-rail operation and low input offset voltage make it well-suited for low power, low frequency A/D applications. Either the LT1366 or LT1368 could be used for this application. However, for low frequencies (f < 1kHz) the LT1368 provides better supply rejection. 0.1µF V0 VCC 1µF + 1/2 LT1368 – 0.1µF CS/SHDN CH0 VCC (REF) CLK TO µP LTC1288 CH1 V1 DOUT DIN LT1366 FO5 + 1/2 LT1368 GND 0.1µF – Figure 5. 2-Channel Low Power A/D Converter 1366fb  LT1366/LT1367 LT1368/LT1369 Typical applicaTions Precision Low Dropout Regulator Microprocessors and complex digital circuits frequently specify tight control of power supply characteristics. The circuit shown in Figure 6 provides a precise 3.6V, 1A output from a minimum 3.8V input voltage. The circuit’s nominal operating voltage is 4.75V ±5%. The voltage reference and resistor ratios determine output voltage accuracy, while the LT1366’s high gain enforces 0.2% line and load regulation. Quiescent current is about 1mA and does not change appreciably with supply or load. All components are available in surface mount packages. The regulator’s main loop consists of A1 and a logic-level FET, Q1. The output is fed back to the op amp’s positive input because of the phase inversion through Q1. The regulator’s frequency response is limited by Q1’s roll-off and the phase lead introduced by the output capacitor’s effective series resistance (ESR). Two pole-zero networks compensate for these effects. The pole formed with R5 and C2 rolls off the gain set with the feedback network, while the pole formed with R7 and C3 rolls off A1’s gain directly, which is the dominant influence on settling time. The zeros formed with R6 and C2, and R8 and C3 provide phase boost near the unity-gain crossover, which increases the regulator’s phase margin. Although not directly part of the compensation, R9 decouples the op amp’s output from Q1’s large gate capacitance. A second loop provides a foldback current limit. A2 compares the sense voltage across R1 with 50mV referenced to the positive rail. When the sense voltage exceeds the reference, A2’s output drives Q1’s gate positive via A1. In current limit, the output voltage collapses and the current limit LED (D1) turns on causing about 30mV to drop across R3. A2 regulates Q1’s drain current so that the deficit between the 50mV reference and the voltage across R3 is made up across the sense resistor. The reduced sense voltage is 20mV, which sets the current limit to about 400mA. As the supply voltage increases, the voltage across R3 increases, and the current limit folds back to a lower level. The current limit loop deactivates when the load current drops below the regulated output current. When the supply turns on rapidly, C1 bypasses the fold back circuit allowing the regulator to start-up into a heavy load. Q1 does not require a heat sink. When mounted on a type FR4 PC board, Q1 has a thermal resistance of 50°C/W. At 1.4W worst-case dissipation, Q1 can operate up to 80°C. VIN = 4.75V ±5% R8 2k R7 13k C3 6.8nF R1 0.05 R3 20 Q1 Si9433DY 1.5k C1 10µF + 50mV – R4 10k D1 R2 2k + C5 47µF 0.1µF 10k + A1 1/2 LT1366 – R9 100 – + + A2 1/2 LT1366 D2 1N4148 5k 38.5k* C2 6.8nF R6 6.2k C4 1µF LT1004-1.2 R5* 20k RMIN** 1k + VOUT 3.6V 1A CLOAD 10µF Q2 2N3904 23.2k 4.75V TO 3.6V LDO AT 1A *1% METAL FILM **SET RMIN BASED ON LOAD CHARACTERISTICS LT1366 F06 Figure 6. Precision 3.6V, 1A Low Dropout Regulator 1366fb  LT1366/LT1367 LT1368/LT1369 Typical applicaTions High Side Current Source The wide compliance current source shown in Figure 7 takes advantage of the LT1366’s ability to measure small signals near the positive supply rail. The LT1366 adjusts Q1’s gate voltage to force the voltage across the sense resistor (RSENSE) to equal the voltage from the supply to the potentiometer’s wiper. A rail-to-rail op amp is needed because the voltage across the sense resistor must drop to zero when the divided reference voltage is set to zero. Q2 acts as a constant current sink to minimize error in the reference voltage when the supply voltage varies. The circuit can operate over a wide supply range (5V < VCC < 30V). At low input voltage, circuit operation is limited by the MOSFET’s gate drive requirements. At VCC RSENSE 0.2 1k LT1004-1.2 RP 10k high input voltage, circuit operation is limited by the LT1366’s absolute maximum ratings and the output power requirements. The circuit delivers 1A at 200mV of sense voltage. With a 5V input supply, the power dissipation is 5W. For operation at 70°C ambient temperature, the MOSFET’s heat sink must have a thermal resistance of: θHS = θJA(SYSTEM) – θJC(FET) = (125°C – 70°C)/5W – 1.25°C/W = 11°C/W –1.25°C/W = 9.75°C/W which is easily achievable with a small heat sink. Input voltages greater than 5V require the use of a larger heat sink or a reduction of the output current. The circuit’s supply regulation is about 0.03%/V. The output impedance is equal to the MOSFET’s output impedance multiplied by the op amp’s open-loop gain. Degradations in current-source compliance occur when the voltage across the MOSFET’s on-resistance and the sense resistor drops below the voltage required to maintain the desired output current. This condition occurs when: [VCC – VOUT] < [ILOAD • (RSENSE + RON)] Single Supply, 1kHz, 4th Order Butterworth Filter An LT1367 is used in Figure 8 to form a 4th order Butterworth filter. The filter is a simplified state variable architecture consisting of two cascaded 2nd order sections. Each section uses the 360 degree phase shift around – 1/2 LT1366 0.0033µF 100 Q1 MTP23P06 ILOAD + 40k 5V < VCC < 30V 0A < ILOAD < 1A AT VCC = 5V 0mA < ILOAD < 160mA AT VCC = 30V Q2 2N4340 LT1366 F07 Figure 7. High Side Current Source C1 10,000pF R1* 29.5k C2 10,000pF R2* 8.6k 10,000pF VIN – + A1 1/4 LT1367 – 10,000pF 11.8k* + 29.5k* 3.3V 10k 10k *1% RESISTORS A2 1/4 LT1367 – A3 1/4 LT1367 21.5k* – + 11.8k* 1µF A4 1/4 LT1367 VOUT + LT1366 F08 Figure 8. 4-Pole 1kHz, 3.3V Single Supply, State Variable Filter Using the LT1367 1366fb  LT1366/LT1367 LT1368/LT1369 Typical applicaTions the 2 op amp loop to create a negative summing junction at A1’s positive input1. The circuit has low sensitivities for center frequency and Q, which are set with the following equations: ω0 2 = 1/(R1 • C1 • R2 • C2) VIN 10k V+ 2 – 1/2 LT1366 1 3 VOUT + SIGNAL AMP where: R1 = 1/(ω0 • Q • C1) and R2 = Q/(ω0 • C2). The DC bias applied to A2 and A4, half supply, is not needed when split supplies are available. The circuit swings railto-rail in the passband making it an excellent anti-aliasing filter for ADCs. The amplitude response is flat to 1kHz then rolls off at 80dB/decade. 1James Hahn, “State Variable Filter Trims Predecessor’s Component Count,” Electronics, April 1M 7 22pF + 1/2 LT1366 5 CANCELLATION AMP – 6 1366 F10 21, 1982. 1M Figure 10. Input Bias Current Cancellation 180 0 GAIN 144 PHASE 108 72 PHASE (DEG) 36 –40 –60 0 –36 –72 –108 –80 100 1k FREQUENCY (Hz) –144 –180 10k 1366 F11 1366 F09 VCC –20 GAIN (dB) RP 10k + 1/2 LT1366 – RL Figure 9. Frequency Response of 4th Order Butterworth Filter Figure 11. Rail-to-Rail Potentiometer Buffer 1366fb  LT1366/LT1367 LT1368/LT1369 package DescripTion N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .300 – .325 (7.620 – 8.255) .045 – .065 (1.143 – 1.651) .130 (3.302 .005 0.127) .400* (10.160) MAX 8 7 6 5 .008 – .015 (0.203 – 0.381) +.035 .325 –.015 8.255 +0.889 –0.381 .065 (1.651) TYP .255 (6.477 .120 (3.048) .020 MIN (0.508) MIN .018 .003 (0.457 0.076) .015* 0.381) 1 2 3 4 N8 1002 .100 (2.54) BSC INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) NOTE: 1. DIMENSIONS ARE S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .050 BSC .045 .005 8 .189 – .197 (4.801 – 5.004) NOTE 3 7 6 5 .245 MIN .160 .005 .228 – .244 (5.791 – 6.197) .150 – .157 (3.810 – 3.988) NOTE 3 .030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 45 (0.254 – 0.508) .008 – .010 (0.203 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 0 – 8 TYP 1 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0303 1366fb  LT1366/LT1367 LT1368/LT1369 package DescripTion S Package 14-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .050 BSC N .245 MIN .045 .005 14 13 .337 – .344 (8.560 – 8.738) NOTE 3 12 11 10 9 8 N .160 .005 .228 – .244 (5.791 – 6.197) 1 2 3 N/2 N/2 .150 – .157 (3.810 – 3.988) NOTE 3 .030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 .010 – .020 45 (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 0 – 8 TYP .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S14 0502 1366fb  LT1366/LT1367 LT1368/LT1369 reVision hisTory REV B DATE 03/10 DESCRIPTION Change to Absolute Maximum Ratings Updated Format of Order Information Section Change to Electrical Characteristics Note (Revision history begins at Rev B) PAGE NUMBER 2 2 3, 4, 5, 6, 7 1366fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LT1366/LT1367 LT1368/LT1369 Typical applicaTion Instrumentation Amplifier V+ 0.1µF + GUARD 10M – 1/4 LT1367 A1A 10k RF 102k RG 11.3k 100k + INPUTS 200 1/4 LT1367 A1B 10M + – – 10M GUARD 22pF RF 102k R GAIN = 10 1 + F = 100 RG BW = 30kHz () – + 1/4 LT1367 A1D relaTeD parTs PART LT1078/LT1079 LTC1152 DESCRIPTION Dual/Quad 55µA Max, Single Supply, Precision Op Amps Rail-to-Rail Input, Rail-to-Rail Output, Zero-Drift Amplifier COMMENTS Input/Output Common Mode Includes Ground, 70µV VOS(MAX) and 2.5µV/°C Drift (Max), 200kHz GBW, 0.07V/µs Slew Rate High DC Accuracy, 10µV VOS(MAX), 100nV/°C Drift, 1MHz GBW, 1V/µs Slew Rate, Supply Current 2.2mA (Max), Single Supply, Can Be Configured for C-Load™ Operation Input/Output Common Mode Includes Ground, 70µV VOS(MAX) and 4µV/°C Drift (Max), 85kHz GBW, 0.04V/µs Slew Rate Input Common Mode Includes Ground, 275µV VOS(MAX) and 6µV/°C Drift (Max), Supply Current 1.8mA per Op Amp (Max) 375µV VOS(MAX), 2µV/°C Drift (Max), Over-The-Top® Input LT1178/LT1179 LT1211/LT1212 LT1495/LT1496 Dual/Quad 17µA Max, Single Supply, Precision Op Amps Dual/Quad 14MHz, 7V/µs, Single Supply, Precision Op Amps 1.5µA, Rail-to-Rail Input/Output Dual/Quad 0 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com – RG 11.3k 10k + 1/4 LT1367 A1C OUTPUT 100k 1366 TA03 1366fb LT 0310 REV B • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 1995