LT1374IT7

LT1374 4.5A, 500kHz Step-Down Switching Regulator FEATURES s s s s s s s s s DESCRIPTIO Constant 500kHz Switching Frequency High Power 16-Pin TSSOP Package Available Uses All Surface Mount Components Inductor Size Reduced to 1.8µH Saturating Switch Design: 0.07Ω Effective Supply Current: 2.5mA Shutdown Current: 20µA Cycle-by-Cycle Current Limiting Easily Synchronizable The LT ®1374 is a 500kHz monolithic buck mode switching regulator. A 4.5A switch is included on the die along with all the necessary oscillator, control and logic circuitry. High switching frequency allows a considerable reduction in the size of external components. The topology is current mode for fast transient response and good loop stability. Both fixed output voltage and adjustable parts are available. A special high speed bipolar process and new design techniques achieve high efficiency at high switching frequency. Efficiency is maintained over a wide output current range by using the output to bias the circuitry and by utilizing a supply boost capacitor to saturate the power switch. The LT1374 is available in standard 7-pin DD, TO-220, fused lead SO-8 and 16-pin exposed pad TSSOP packages. Full cycle-by-cycle short-circuit protection and thermal shutdown are provided. Standard surface mount external parts may be used, including the inductor and capacitors. There is the optional function of shutdown or synchronization. A shutdown signal reduces supply current to 20µA. Synchronization allows an external logic level signal to increase the internal oscillator from 580kHz to 1MHz. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s Portable Computers Battery-Powered Systems Battery Chargers Distributed Power TYPICAL APPLICATIO 5V Buck Converter D2 CMDSH3 OR FMMD914 C2 0.27µF INPUT 6V TO 25V VIN BOOST VSW 100 95 C3* 10µF TO 50µF + DEFAULT = ON OUTPUT** 5V, 4.25A EFFICIENCY (%) L1** 5µH 90 85 80 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A) 3.5 4.0 LT1374-5 BIAS SHDN GND SENSE VC CC 1.5nF D1 MBRS330T3 + C1 100µF, 10V SOLID TANTALUM 1374 TA01 * RIPPLE CURRENT RATING ≥ IOUT/2 ** INCREASE L1 TO 10µH FOR LOAD CURRENTS ABOVE 3.5A AND TO 20µH ABOVE 4A SEE APPLICATIONS INFORMATION U Efficiency vs Load Current VOUT = 5V VIN = 10V L = 10µH 1374 TA02 U U 1374fb 1 LT1374 ABSOLUTE AXI U RATI GS Input Voltage LT1374 ............................................................... 25V LT1374HV .......................................................... 32V BOOST Pin Voltage ................................................. 38V BOOST Pin Above Input Voltage ............................. 15V SHDN Pin Voltage ..................................................... 7V BIAS Pin Voltage ...................................................... 7V FB Pin Voltage (Adjustable Part) ............................ 3.5V PACKAGE/ORDER I FOR ATIO FRONT VIEW 7 6 5 4 3 2 1 R PACKAGE 7-LEAD PLASTIC DD FB OR SENSE* BOOST VIN GND VSW SYNC OR SHDN* VC ORDER PART NUMBER LT1374CR LT1374CR-5 LT1374CR-SYNC LT1374CR-5 SYNC LT1374HVCR LT1374IR LT1374IR-5 LT1374IR-SYNC LT1374IR-5 SYNC LT1374HVIR ORDER PART NUMBER 16 GND 15 VSW 14 VSW 13 SYNC 12 SHDN 11 VC 10 BIAS 9 GND TAB IS GND FRONT VIEW 7 6 5 4 3 2 1 T7 PACKAGE 7-LEAD PLASTIC TO-220 FB OR SENSE* BOOST VIN GND VSW SHDN VC TAB IS GND TJMAX = 125°C, θJA = 30°C/ W WITH PACKAGE SOLDERED TO 0.5 SQUARE INCH COPPER AREA OVER BACKSIDE GROUND PLANE OR INTERNAL POWER PLANE. θJA CAN VARY FROM 20°C/W TO > 40°C/W DEPENDING ON MOUNTING TECHNIQUES TOP VIEW GND NC VIN VIN BOOST FB/SENSE NC GND 1 2 3 4 5 6 7 8 LT1374CFE LT1374IFE FE16 PACKAGE 16-LEAD PLASTIC TSSOP θJA = 40°C/ W EXPOSED PAD SOLDERED TO GROUND PLANE *Default is the adjustable output voltage device with FB pin and shutdown function. Option -5 replaces FB with SENSE pin for fixed 5V output applications. -SYNC replaces SHDN with SYNC pin for applications requiring synchronization. Consult LTC Marketing for parts specified with wider operating temperature ranges. 2 U U W WW U W (Note 1) FB Pin Current (Adjustable Part) ............................ 1mA SENSE Voltage (Fixed 5V Part) ................................. 7V SYNC Pin Voltage ..................................................... 7V Operating Junction Temperature Range LT1374C ............................................... 0°C to 125° C LT1374I ........................................... – 40°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LT1374CS8 LT1374CS8-5 LT1374CS8-SYNC LT1374CS8-5 SYNC LT1374HVCS8 LT1374IS8 LT1374IS8-5 LT1374IS8-SYNC LT1374IS8-5 SYNC LT1374HVIS8 S8 PART MARKING 1374 1374I 13745 1374I5 1374SN 374ISN 3745SN 74I5SN 1374HV 1374HVI ORDER PART NUMBER LT1374CT7 LT1374CT7-5 LT1374IT7 LT1374IT7-5 TOP VIEW VIN 1 BOOST 2 FB OR 3 SENSE* FGND 4 8 VSW SYNC 7 OR SHDN* 6 VC 5 BIAS S8 PACKAGE 8-LEAD PLASTIC SO θJA = 80°C/ W WITH FUSED (FGND) GROUND PIN CONNECTED TO GROUND PLANE OR LARGE LANDS TJMAX = 125°C, θJA = 50°C/ W, θJC = 4°C/ W 1374fb LT1374 ELECTRICAL CHARACTERISTICS PARAMETER Feedback Voltage (Adjustable) Sense Voltage (Fixed 5V) All Conditions SENSE Pin Resistance Reference Voltage Line Regulation Feedback Input Bias Current Error Amplifier Voltage Gain Error Amplifier Transconductance VC Pin to Switch Current Transconductance Error Amplifier Source Current Error Amplifier Sink Current VC Pin Switching Threshold VC Pin High Clamp Switch Current Limit Slope Compensation (Note 9) Switch On Resistance (Note 7) Maximum Switch Duty Cycle Switch Frequency Switch Frequency Line Regulation Frequency Shifting Threshold on FB Pin Minimum Input Voltage (Note 3) Minimum Boost Voltage (Note 4) Boost Current (Note 5) VIN Supply Current (Note 6) BIAS Supply Current (Note 6) Shutdown Supply Current CONDITIONS All Conditions The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted. MIN 2.39 2.36 4.94 4.90 7 TYP 2.42 5.0 10 0.01 0.5 400 2000 5.3 225 225 0.9 2.1 6 0.8 0.07 93 93 500 0 1.0 5.0 2.3 20 90 0.9 3.2 20 30 q q q q q q q 5V ≤ VIN ≤ 25V (5V ≤ VIN ≤ 32V for LT1374HV) q MAX 2.45 2.48 5.06 5.10 14 0.03 2 2700 3100 320 320 UNITS V V V V kΩ %/V µA µMho µMho A/ V µA µA V V A A Ω Ω % % kHz kHz %/ V V V V mA mA mA mA µA µA µA µA V V V V kHz kΩ (Notes 2, 8) ∆I (VC) = ± 10µA (Note 8) q 200 1500 1000 140 140 VFB = 2.1V or VSENSE = 4.4V VFB = 2.7V or VSENSE = 5.6V Duty Cycle = 0 VC Open, VFB = 2.1V or VSENSE = 4.4V, DC ≤ 50% DC = 80% ISW = 4.5A VFB = 2.1V or VSENSE = 4.4V q q q 4.5 8.5 0.1 0.13 q q VC Set to Give 50% Duty Cycle q 90 86 460 440 0.8 5V ≤ VIN ≤ 25V, (5V ≤ VIN ≤ 32V for LT1374HV) ∆f = 10kHz ISW ≤ 4.5A ISW = 1A ISW = 4.5A VBIAS = 5V VBIAS = 5V VSHDN = 0V, VIN ≤ 25V, VSW = 0V, VC Open VSHDN = 0V, VIN ≤ 32V, VSW = 0V, VC Open q q q q q q q q q Lockout Threshold Shutdown Thresholds Synchronization Threshold Synchronizing Range SYNC Pin Input Resistance VC Open VC Open Device Shutting Down Device Starting Up 2.3 0.13 0.25 580 2.38 0.37 0.45 1.5 40 540 560 0.15 1.3 5.5 3.0 35 140 1.4 4.0 50 75 75 100 2.46 0.60 0.7 2.2 1000 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Gain is measured with a VC swing equal to 200mV above the switching threshold level to 200mV below the upper clamp level. Note 3: Minimum input voltage is not measured directly, but is guaranteed by other tests. It is defined as the voltage where internal bias lines are still regulated so that the reference voltage and oscillator frequency remain constant. Actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. See Applications Information. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. 1374fb 3 LT1374 ELECTRICAL CHARACTERISTICS Note 5: Boost current is the current flowing into the boost pin with the pin held 5V above input voltage. It flows only during switch on time. Note 6: VIN supply current is the current drawn when the BIAS pin is held at 5V and switching is disabled. If the BIAS pin is unavailable or open circuit, the sum of VIN and BIAS supply currents will be drawn by the VIN pin. Note 7: Switch on resistance is calculated by dividing VIN to VSW voltage by the forced current (4.5A). See Typical Performance Characteristics for the graph of switch voltage at other currents. Note 8: Transconductance and voltage gain refer to the internal amplifier exclusive of the voltage divider. To calculate gain and transconductance, refer to the SENSE pin on the fixed voltage parts. Divide values shown by the ratio VOUT/2.42. Note 9: Slope compensation is the current subtracted from the switch current limit at 80% duty cycle. See Maximum Output Load Current in the Applications Information section for further details. TYPICAL PERFOR A CE CHARACTERISTICS Switch Voltage Drop 500 450 400 125°C 6.5 6.0 SWITCH PEAK CURRENT (A) SWITCH VOLTAGE (mV) 350 300 250 200 150 100 50 0 0 1 5.5 5.0 MINIMUM 4.5 4.0 3.5 3.0 25°C – 40°C FEEDBACK VOLTAGE (V) 4 3 SWITCH CURRENT (A) 2 Shutdown Pin Bias Current 500 400 300 200 8 4 0 –50 –25 CURRENT REQUIRED TO FORCE SHUTDOWN (FLOWS OUT OF PIN). AFTER SHUTDOWN, CURRENT DROPS TO A FEW µA 2.40 SHUTDOWN PIN VOLTAGE (V) 2.36 INPUT SUPPLY CURRENT (µA) CURRENT (µA) AT 2.38V STANDBY THRESHOLD (CURRENT FLOWS OUT OF PIN) 50 25 75 0 TEMPERATURE (°C) 4 UW 5 1374 G18 Switch Peak Current Limit 2.430 Feedback Pin Voltage TYPICAL 2.425 2.420 2.415 0 20 60 40 DUTY CYCLE (%) 80 100 1374 G02 2.410 – 50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 1374 G03 Standby and Shutdown Thresholds 25 STANDBY Shutdown Supply Current VSHDN = 0V 20 2.32 15 0.8 START-UP 0.4 SHUTDOWN 10 5 100 125 0 –50 –25 0 50 100 25 75 0 JUNCTION TEMPERATURE (°C) 125 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G06 1374 G04 1374 G05 1374fb LT1374 TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Supply Current 70 60 VIN = 25V 50 VIN = 10V 40 30 20 10 RLOAD = 50Ω 2500 INPUT SUPPLY CURRENT (µA) TRANSCONDUCTANCE (µMho) GAIN (µMho) 0 0 0.1 0.2 0.3 SHUTDOWN VOLTAGE (V) 0.4 1374 G07 Frequency Foldback SWITCHING FREQUENCY (kHz) OR CURRENT (µA) 500 400 FREQUENCY (kHz) 520 510 500 490 480 470 300 INPUT VOLTAGE (V) SWITCHING FREQUENCY 200 100 FEEDBACK PIN CURRENT 0 0 0.5 1.5 2.0 1.0 FEEDBACK PIN VOLTAGE (V) 2.5 1374 G10 Maximum Load Current at VOUT = 10V 4.5 VOUT = 10V L = 20µH L = 10µH CURRENT (A) CURRENT (A) CURRENT (A) 4.0 3.5 3.0 0 5 10 15 INPUT VOLTAGE (V) UW L = 5µH 20 1374 G13 Error Amplifier Transconductance 3000 Error Amplifier Transconductance 200 PHASE 2000 2500 GAIN 150 PHASE (DEG) 1500 2000 100 VC 1000 1500 VFB 2 × 10–3 ( ) ROUT 200k COUT 12pF 50 500 1000 ERROR AMPLIFIER EQUIVALENT CIRCUIT 0 0 50 0 75 100 25 –50 –25 JUNCTION TEMPERATURE (°C) 125 500 100 1k 10k 100k FREQUENCY (Hz) 1M –50 10M 1374 G09 1374 G08 Switching Frequency 550 540 530 Minimum Input Voltage with 5V Output 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 MINIMUM RUNNING VOLTAGE MINIMUM STARTING VOLTAGE 460 450 – 50 –25 0 25 50 75 100 125 1 TEMPERATURE (°C) 1374 G11 10 100 LOAD CURRENT (mA) 1000 1374 G12 Maximum Load Current at VOUT = 3.3V 4.5 L = 20µH L = 10µH 4.0 L = 5µH 4.0 4.5 Maximum Load Current at VOUT = 5V L = 20µH L = 10µH L = 5µH 3.5 3.5 VOUT = 3.3V 3.0 25 3.0 VOUT = 5V 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G14 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G15 1374fb 5 LT1374 TYPICAL PERFOR A CE CHARACTERISTICS BOOST Pin Current 100 90 DUTY CYCLE = 100% BOOST PIN CURRENT (mA) THRESHOLD VOLTAGE (V) 80 70 60 50 40 30 20 10 0 0 1 3 2 4 SWITCH CURRENT (A) 5 1374 G16 1.0 CORE LOSS (W) PI FU CTIO S FB/SENSE: The feedback pin is the input to the error amplifier which is referenced to an internal 2.42V source. An external resistive divider is used to set the output voltage. The fixed voltage (-5) parts have the divider included on-chip and the FB pin is used as a SENSE pin, connected directly to the 5V output. Three additional functions are performed by the FB pin. When the pin voltage drops below 1.7V, switch current limit is reduced. Below 1.5V the external sync function is disabled. Below 1V, switching frequency is also reduced. See Feedback Pin Function section in Applications Information for details. BOOST: The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.07Ω FET structure. Efficiency improves from 75% for conventional bipolar designs to > 89% for these new parts. VIN: This is the collector of the on-chip power NPN switch. This pin powers the internal circuitry and internal regulator when the BIAS pin is not present. At NPN switch on and off, high dI/dt edges occur on this pin. Keep the external bypass and catch diode close to this pin. All trace inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. Both VIN pins of the 16-lead TSSOP package must be shorted together on the PC board. GND: The GND pin connection needs consideration for two reasons. First, it acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. The second consideration is EMI caused by GND pin current spikes. Internal capacitance between the VSW pin and the GND pin creates very narrow (100MHz oscilloscope must be used, and waveforms should be observed on the leads of the package. This switch off spike will also cause the SW node to go below ground. The LT1374 has special circuitry inside which mitigates this problem, but negative voltages over 1V lasting longer than 10ns should be avoided. Note that 100MHz oscilloscopes are barely fast enough to see the details of the falling edge overshoot in Figure 7. A second, much lower frequency ringing is seen during switch off time if load current is low enough to allow the inductor current to fall to zero during part of the switch off time (see Figure 8). Switch and diode capacitance resonate with the inductor to form damped ringing at 1MHz to 10 MHz. This ringing is not harmful to the regulator and it has not been shown to contribute significantly to EMI. Any attempt to damp it with a resistive snubber will degrade efficiency. INPUT BYPASSING AND VOLTAGE RANGE Input Bypass Capacitor Step-down converters draw current from the input supply in pulses. The average height of these pulses is equal to load current, and the duty cycle is equal to VOUT/ VIN. Rise and fall time of the current is very fast. A local bypass capacitor across the input supply is necessary to ensure proper operation of the regulator and minimize the ripple U W U U 5V/DIV RISE AND FALL WAVEFORMS ARE SUPERIMPOSED (PULSE WIDTH IS NOT 120ns) 20ns/DIV 1374 F07 Figure 7. Switch Node Resonance 5V/DIV SWITCH NODE VOLTAGE 100mA/DIV INDUCTOR CURRENT 20ns/DIV 0.5µs/DIV 1375/76 F11 1374 F08 Figure 8. Discontinuous Mode Ringing current fed back into the input supply. The capacitor also forces switching current to flow in a tight local loop, minimizing EMI. Do not cheat on the ripple current rating of the Input bypass capacitor, but also don’t get hung up on the value in microfarads. The input capacitor is intended to absorb all the switching current ripple, which can have an RMS value as high as one half of load current. Ripple current ratings on the capacitor must be observed to ensure reliable operation. In many cases it is necessary to parallel two capacitors to obtain the required ripple rating. Both capacitors must be of the same value and manufacturer to guarantee power sharing. The actual value of the capacitor in microfarads is not particularly important because at 500kHz, any value above 5µF is essentially resistive. RMS ripple current rating is the critical parameter. Actual RMS current can be calculated from: IRIPPLE(RMS) = IOUT VOUT VIN − VOUT / VIN ( ) 2 1374fb 19 LT1374 APPLICATIONS INFORMATION The term inside the radical has a maximum value of 0.5 when input voltage is twice output, and stays near 0.5 for a relatively wide range of input voltages. It is common practice therefore to simply use the worst-case value and assume that RMS ripple current is one half of load current. At maximum output current of 4.5A for the LT1374, the input bypass capacitor should be rated at 2.25A ripple current. Note however, that there are many secondary considerations in choosing the final ripple current rating. These include ambient temperature, average versus peak load current, equipment operating schedule, and required product lifetime. For more details, see Application Notes 19 and 46, and Design Note 95. Input Capacitor Type Some caution must be used when selecting the type of capacitor used at the input to regulators. Aluminum electrolytics are lowest cost, but are physically large to achieve adequate ripple current rating, and size constraints (especially height), may preclude their use. Ceramic capacitors are now available in larger values, and their high ripple current and voltage rating make them ideal for input bypassing. Cost is fairly high and footprint may also be somewhat large. Solid tantalum capacitors would be a good choice, except that they have a history of occasional spectacular failures when they are subjected to large current surges during power-up. The capacitors can short and then burn with a brilliant white light and lots of nasty smoke. This phenomenon occurs in only a small percentage of units, but it has led some OEM companies to forbid their use in high surge applications. The input bypass capacitor of regulators can see these high surges when a battery or high capacitance source is connected. Several manufacturers have developed a line of solid tantalum capacitors specially tested for surge capability (AVX TPS series for instance, see Table 3), but even these units may fail if the input voltage surge approaches the maximum voltage rating of the capacitor. AVX recommends derating capacitor voltage by 2:1 for high surge applications. The highest voltage rating is 50V, so 25V may be a practical upper limit when using solid tantalum capacitors for input bypassing. Larger capacitors may be necessary when the input voltage is very close to the minimum specified on the data sheet. Small voltage dips during switch on time are not normally a problem, but at very low input voltage they may cause erratic operation because the input voltage drops below the minimum specification. Problems can also occur if the input-to-output voltage differential is near minimum. The amplitude of these dips is normally a function of capacitor ESR and ESL because the capacitive reactance is small compared to these terms. ESR tends to be the dominate term and is inversely related to physical capacitor size within a given capacitor type. SYNCHRONIZING (Available as -SYNC Option) The LT1374-SYNC has the SHDN pin replaced with a SYNC pin, which is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 10% and 90%. The input can be driven directly from a logic level output. The synchronizing range is equal to initial operating frequency up to 1MHz. This means that minimum practical sync frequency is equal to the worst-case high selfoscillating frequency (550kHz), not the typical operating frequency of 500kHz. Caution should be used when synchronizing above 700kHz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. At power-up, when VC is being clamped by the FB pin (see Figure 2, Q2), the sync function is disabled. This allows the frequency foldback to operate in the shorted output condition. During normal operation, switching frequency is controlled by the internal oscillator until the FB pin reaches 1.5V, after which the SYNC pin becomes operational. If no synchronization is required, this pin should be connected to ground. 1374fb 20 U W U U LT1374 APPLICATIONS INFORMATION THERMAL CALCULATIONS Power dissipation in the LT1374 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. Switch loss: Thermal resistance for LT1374 package is influenced by the presence of internal or backside planes. With a full plane under the 16-lead TSSOP package, thermal resistance will be about 40°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: TJ = TA + θJA (PTOT) With the TSSOP16 package (θJA = 40°C/W), at an ambient temperature of 50°C, TJ = 50 + 40 (0.87) = 85°C For the DD package with a good copper plane under the device, thermal resistance will be about 30°C/W. For the conditions above: TJ = 50 + 30 (0.87) = 76°C Die temperature is highest at low input voltage, so use lowest continuous input operating voltage for thermal calculations. PSW = RSW IOUT ( ) (VOUT ) + 24ns(I )(V )(f) OUT IN VIN 2 2 Boost current loss: PBOOST = VOUT IOUT / 50 VIN 2   VOUT  0.002   0.005 + VIN ( ) Quiescent current loss: PQ = VIN 0.001 + VOUT ( ) ( ) ( RSW = Switch resistance (≈ 0.07) 24ns = Equivalent switch current/voltage overlap time f = Switch frequency Example: with VIN = 10V, VOUT = 5V and IOUT = 3A: PSW (0.07)(3) (5) +  24 • 10  (3)(10) 500 • 10  =     10 2 −9 3 = 0.32 + 0.36 = 0.68W PBOOST PQ (5) (3 / 50) = 0.15W = 2 (5) (0.002) = 0.04W = 10(0.001) + 5(0.005) + 2 10 10 Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W. U W U U ) FREQUENCY COMPENSATION Loop frequency compensation of switching regulators can be a rather complicated problem because the reactive components used to achieve high efficiency also introduce multiple poles into the feedback loop. The inductor and output capacitor on a conventional step-down converter actually form a resonant tank circuit that can exhibit peaking and a rapid 180° phase shift at the resonant frequency. By contrast, the LT1374 uses a “current mode” architecture to help alleviate phase shift created by the inductor. The basic connections are shown in Figure 9. Figure 10 shows a Bode plot of the phase and gain of the power section of the LT1374, measured from the VC pin to the output. Gain is set by the 5.3A/V transconductance of the LT1374 power section and the effective complex impedance from output to ground. Gain rolls off smoothly above the 600Hz pole frequency set by the 100µF output capacitor. Phase drop is limited to about 70°. Phase recovers and gain levels off at the zero frequency (≈16kHz) set by capacitor ESR (0.1Ω). 1374fb 21 LT1374 APPLICATIONS INFORMATION Error amplifier transconductance phase and gain are shown in Figure 11. The error amplifier can be modeled as a transconductance of 2000µMho, with an output impedance of 200kΩ in parallel with 12pF. In all practical applications, the compensation network from VC pin to ground has a much lower impedance than the output impedance of the amplifier at frequencies above 500Hz. This means that the error amplifier characteristics themselves do not contribute excess phase shift to the loop, and the phase/gain characteristics of the error amplifier section are completely controlled by the external compensation network. In Figure 12, full loop phase/gain characteristics are shown with a compensation capacitor of 1.5nF, giving the error amplifier a pole at 530Hz, with phase rolling off to 90° LT1374 CURRENT MODE POWER STAGE gm = 5.3A/V VSW ERROR AMPLIFIER FB ESR R1 GAIN (µMho) 2.42V GND VC + C1 R2 CF RC CC Figure 9. Model for Loop Response 40 GAIN 20 40 GAIN: VC PIN TO OUTPUT (dB) VIN = 10V VOUT = 5V IOUT = 2A 0 LOOP GAIN (dB) 0 PHASE –20 –40 –80 –40 10 100 1k 10k FREQUENCY (Hz) 100k –120 1M 1374 F10 Figure 10. Response from VC Pin to Output 22 U W U – + U and staying there. The overall loop has a gain of 74dB at low frequency, rolling off to unity-gain at 100kHz. Phase shows a two-pole characteristic until the ESR of the output capacitor brings it back above 10kHz. Phase margin is about 75° at unity-gain. Analog experts will note that around 4.4kHz, phase dips very close to the zero phase margin line. This is typical of switching regulators, especially those that operate over a wide range of loads. This region of low phase is not a problem as long as it does not occur near unity-gain. In practice, the variability of output capacitor ESR tends to dominate all other effects with respect to loop response. Variations in ESR will cause unity-gain to move around, but at the same time phase moves with it so that adequate phase margin is maintained over a very wide range of ESR (≥ ± 3:1). 3000 200 PHASE 2500 GAIN 100 VC ROUT 200k COUT 12pF OUTPUT 150 PHASE (DEG) 2000 1500 VFB 2 × 10–3 ( ) 50 1000 ERROR AMPLIFIER EQUIVALENT CIRCUIT 0 RLOAD = 50Ω 500 100 1374 F09 1k 10k 100k FREQUENCY (Hz) 1M –50 10M 1374 F11 Figure 11. Error Amplifier Gain and Phase 80 GAIN 200 PHASE: VC PIN TO OUTPUT (DEG) 60 150 LOOP PHASE (DEG) 40 PHASE 100 20 VIN = 10V VOUT = 5V, IOUT = 2A COUT = 100µF, 10V, AVX TPS CC = 1.5nF, RC = 0, L = 10µH 10 100 1k 10k FREQUENCY (Hz) 50 0 0 –20 100k –50 1M 1374 F12 Figure 12. Overall Loop Characteristics 1374fb LT1374 APPLICATIONS INFORMATION What About a Resistor in the Compensation Network? It is common practice in switching regulator design to add a “zero” to the error amplifier compensation to increase loop phase margin. This zero is created in the external network in the form of a resistor (RC) in series with the compensation capacitor. Increasing the size of this resistor generally creates better and better loop stability, but there are two limitations on its value. First, the combination of output capacitor ESR and a large value for RC may cause loop gain to stop rolling off altogether, creating a gain margin problem. An approximate formula for RC where gain margin falls to zero is: R C Loop Gain = 1 = ( ) (G )(G )(ESR)(2.42) VOUT MP MA GMP = Transconductance of power stage = 5.3A/V GMA = Error amplifier transconductance = 2(10–3) ESR = Output capacitor ESR 2.42 = Reference voltage With VOUT = 5V and ESR = 0.03Ω, a value of 6.5k for RC would yield zero gain margin, so this represents an upper limit. There is a second limitation however which has nothing to do with theoretical small signal dynamics. This resistor sets high frequency gain of the error amplifier, including the gain at the switching frequency. If switching frequency gain is high enough, output ripple voltage will appear at the VC pin with enough amplitude to muck up proper operation of the regulator. In the marginal case, subharmonic switching occurs, as evidenced by alternating pulse widths seen at the switch node. In more severe cases, the regulator squeals or hisses audibly even though the output voltage is still roughly correct. None of this will show on a theoretical Bode plot because Bode is an amplitude insensitive analysis. Tests have shown that if ripple voltage on the VC is held to less than 100mVP-P, the LT1374 will be well behaved. The formula below will give an estimate of VC ripple voltage when RC is added to the loop, assuming that RC is large compared to the reactance of CC at 500kHz. U W U U VC(RIPPLE ) = (R )(G )(V − V )(ESR)(2.4) (V )(L)(f) C MA IN OUT IN GMA = Error amplifier transconductance (2000µMho) If a computer simulation of the LT1374 showed that a series compensation resistor of 3k gave best overall loop response, with adequate gain margin, the resulting VC pin ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω, L = 10µH, would be: VC (RIPPLE (3k) 2 • 10  (10 − 5)(0.1)(2.4) = 0.144V   )= (10) 10 • 10   500 • 10     −3 −6 3 This ripple voltage is high enough to possibly create subharmonic switching. In most situations a compromise value (< 2k in this case) for the resistor gives acceptable phase margin and no subharmonic problems. In other cases, the resistor may have to be larger to get acceptable phase response, and some means must be used to control ripple voltage at the VC pin. The suggested way to do this is to add a capacitor (CF) in parallel with the RC /CC network on the VC pin. Pole frequency for this capacitor is typically set at one-fifth of switching frequency so that it provides significant attenuation of switching ripple, but does not add unacceptable phase shift at loop unity-gain frequency. With RC = 3k, CF = (2π)(f)(R ) C 5 = 5 2π  500 • 103  3k   () = 531pF How Do I Test Loop Stability? The “standard” compensation for LT1374 is a 1.5nF capacitor for CC, with RC = 0. While this compensation will work for most applications, the “optimum” value for loop compensation components depends, to various extent, on parameters which are not well controlled. These include inductor value (± 30% due to production tolerance, load 1374fb 23 LT1374 APPLICATIONS INFORMATION current and ripple current variations), output capacitance (± 20% to ± 50% due to production tolerance, temperature, aging and changes at the load), output capacitor ESR (± 200% due to production tolerance, temperature and aging), and finally, DC input voltage and output load current . This makes it important for the designer to check out the final design to ensure that it is “robust” and tolerant of all these variations. I check switching regulator loop stability by pulse loading the regulator output while observing transient response at the output, using the circuit shown in Figure 13. The regulator loop is “hit” with a small transient AC load current at a relatively low frequency, 50Hz to 1kHz. This causes the output to jump a few millivolts, then settle back to the original value, as shown in Figure 14. A well behaved loop will settle back cleanly, whereas a loop with poor phase or gain margin will “ring” as it settles. The number of rings indicates the degree of stability, and the frequency of the ringing shows the approximate unity-gain frequency of the loop. Amplitude of the signal is not particularly important, as long as the amplitude is not so high that the loop behaves nonlinearly. The output of the regulator contains both the desired low frequency transient information and a reasonable amount of high frequency (500kHz) ripple. The ripple makes it difficult to observe the small transient, so a two-pole, 100kHz filter has been added. This filter is not particularly critical; even if it attenuated the transient signal slightly, this wouldn’t matter because amplitude is not critical. After verifying that the setup is working correctly, I start varying load current and input voltage to see if I can find any combination that makes the transient response look suspiciously “ringy.” This procedure may lead to an adjustment for best loop stability or faster loop transient response. Nearly always you will find that loop response looks better if you add in several kΩ for RC. Do this only if necessary, because as explained before, RC above 1k may require the addition of CF to control VC pin ripple. If everything looks OK, I use a heat gun and cold spray on the circuit (especially the output capacitor) to bring out any temperature-dependent characteristics. Keep in mind that this procedure does not take initial component tolerance into account. You should see fairly clean response under all load and line conditions to ensure that component variations will not cause problems. One note here: according to Murphy, the component most VOUT AT IOUT = 500mA BEFORE FILTER VOUT AT IOUT = 500mA AFTER FILTER VOUT AT IOUT = 50mA AFTER FILTER LOAD PULSE THROUGH 50Ω f ≈ 780Hz 0.2ms/DIV 1374 F14 SWITCHING REGULATOR ADJUSTABLE INPUT SUPPLY ADJUSTABLE DC LOAD Figure 13. Loop Stability Test Circuit 1374fb 24 U W U U 10mV/DIV 5A/DIV Figure 14. Loop Stability Check RIPPLE FILTER 470Ω 4.7k 330pF TO X1 OSCILLOSCOPE PROBE + 100µF TO 1000µF 50Ω 3300pF TO OSCILLOSCOPE SYNC 100Hz TO 1kHz 100mV TO 1VP-P 1374 F13 LT1374 APPLICATIONS INFORMATION likely to be changed in production is the output capacitor, because that is the component most likely to have manufacturer variations (in ESR) large enough to cause problems. It would be a wise move to lock down the sources of the output capacitor in production. A possible exception to the “clean response” rule is at very light loads, as evidenced in Figure 14 with ILOAD = 50mA. Switching regulators tend to have dramatic shifts in loop response at very light loads, mostly because the inductor current becomes discontinuous. One common result is very slow but stable characteristics. A second possibility is low phase margin, as evidenced by ringing at the output with transients. The good news is that the low phase margin at light loads is not particularly sensitive to component variation, so if it looks reasonable under a transient test, it will probably not be a problem in production. Note that frequency of the light load ringing may vary with component tolerance but phase margin generally hangs in there. POSITIVE-TO-NEGATIVE CONVERTER The circuit in Figure 15 is a classic positive-to-negative topology using a grounded inductor. It differs from the standard approach in the way the IC chip derives its feedback signal, however, because the LT1374 accepts only positive feedback signals, the ground pin must be tied to the regulated negative output. A resistor divider to ground or, in this case, the sense pin, then provides the proper feedback voltage for the chip. D1 CMDSH-3 C2 0.27µF VSW L1* 5µH INPUT 5.5V TO 20V C3 10µF TO 50µF BOOST VIN LT1374-5 + GND SENSE VC CC RC D2 MBRS330T3 + * INCREASE L1 TO 10µH OR 20µH FOR HIGHER CURRENT APPLICATIONS. SEE APPLICATIONS INFORMATION ** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION Figure 15. Positive-to-Negative Converter 1374fb U W U U Inverting regulators differ from buck regulators in the basic switching network. Current is delivered to the output as square waves with a peak-to-peak amplitude much greater than load current. This means that maximum load current will be significantly less than the LT1374’s 4.5A maximum switch current, even with large inductor values. The buck converter in comparison, delivers current to the output as a triangular wave superimposed on a DC level equal to load current, and load current can approach 4.5A with large inductors. Output ripple voltage for the positiveto-negative converter will be much higher than a buck converter. Ripple current in the output capacitor will also be much higher. The following equations can be used to calculate operating conditions for the positive-to-negative converter. Maximum load current:   VIN VOUT  IP −  2 VOUT + VIN f L    IMAX = VOUT + VIN − 0.35 ( ( ( )( ) (V )(V − 0.35 ) )( )( ) OUT IN )(VOUT + VF) IP = Maximum rated switch current VIN = Minimum input voltage VOUT = Output voltage VF = Catch diode forward voltage 0.35 = Switch voltage drop at 4.5A Example: with VIN(MIN) = 5.5V, VOUT = 5V, L = 10µH, VF = 0.5V, IP = 4.5A: IMAX = 2A. Note that this equation does not take into account that maximum rated switch current (IP) on the LT1374 is reduced slightly for duty cycles above 50%. If duty cycle is expected to exceed 50% (input voltage less than output voltage), use the actual IP value from the Electrical Characteristics table. Operating duty cycle: C1 100µF 10V TANT ×2 OUTPUT** –5V, 1.8A DC = VOUT + VF VIN − 0.3 + VOUT + VF 1374 F15 (This formula uses an average value for switch loss, so it may be several percent in error.) 25 LT1374 APPLICATIONS INFORMATION With the conditions above: DC = 5 + 0.5 = 51% 5.5 − 0.3 + 5 + 0.5 lowest value of inductance that can be used, but in some cases (lower output load currents) it may give a value that creates unnecessarily high output ripple voltage. A compromise value is often chosen that reduces output ripple. As you can see from the graph, large inductors will not give arbitrarily low ripple, but small inductors can give high ripple. The difficulty in calculating the minimum inductor size needed is that you must first know whether the switcher will be in continuous or discontinuous mode at the critical point where switch current is 4.5A. The first step is to use the following formula to calculate the load current where the switcher must use continuous mode. If your load current is less than this, use the discontinuous mode formula to calculate minimum inductor needed. If load current is higher, use the continuous mode formula. Output current where continuous mode is needed: ICONT = This duty cycle is close enough to 50% that IP can be assumed to be 4.5A. OUTPUT DIVIDER If the adjustable part is used, the resistor connected to VOUT (R2) should be set to approximately 5k. R1 is calculated from: R1 = R2 VOUT – 2.42 2.42 ( ) INDUCTOR VALUE Unlike buck converters, positive-to-negative converters cannot use large inductor values to reduce output ripple voltage. At 500kHz, values larger than 25µH make almost no change in output ripple. The graph in Figure 16 shows peak-to-peak output ripple voltage for a 5V to – 5V converter versus inductor value. The criteria for choosing the inductor is therefore typically based on ensuring that peak switch current rating is not exceeded. This gives the 250 OUTPUT RIPPLE VOLTAGE (mVP-P) 200 5V TO – 5V CONVERTER OUTPUT CAPACITOR’S ESR = 0.05Ω 150 ILOAD = 1A 100 50 ILOAD = 0.25A 0 0 5 15 10 INDUCTOR SIZE (µH) 20 1374 F16 Figure 16. Ripple Voltage on Positive-to-Negative Converter 26 U W U U (V ) (I ) 4(V + V )(V + V 2 2 IN P IN OUT IN OUT + VF ) Minimum inductor discontinuous mode: L MIN = 2 VOUT IOUT 2 P ( )( ) (f)(I )   V +V I − I  1 + OUT F  P OUT  VIN   Minimum inductor continuous mode: L MIN = (V )(V ) IN OUT 2 f VIN + VOUT ( )( ) ( )   For the example above, with maximum load current of 1A: ICONT = (5.5) (4.5) = 1.15 A 4 (5.5 + 5)(5.5 + 5 + 0.5 ) 2 2 1374fb LT1374 APPLICATIONS INFORMATION This says that discontinuous mode can be used and the minimum inductor needed is found from: L MIN = ( )( )  500 • 10  4.5  ( ) 25 1 3 2 = 1µH In practice, the inductor should be increased by about 30% over the calculated minimum to handle losses and variations in value. This suggests a minimum inductor of 1.3µH for this application, but looking at the ripple voltage chart shows that output ripple voltage could be reduced by a factor of two by using a 15µH inductor. There is no rule of thumb here to make a final decision. If modest ripple is needed and the larger inductor does the trick, go for it. If ripple is noncritical use the smaller inductor. If ripple is extremely critical, a second filter may have to be added in any case, and the lower value of inductance can be used. Keep in mind that the output capacitor is the other critical factor in determining output ripple voltage. Ripple shown on the graph (Figure 16) is with two parallel capacitor’s ESR of 0.1Ω. This is reasonable for AVX type TPS “D” or “E” size surface mount solid tantalum capacitors, but the final capacitor chosen must be looked at carefully for ESR characteristics. Ripple Current in the Input and Output Capacitors Positive-to-negative converters have high ripple current in both the input and output capacitors. For long capacitor lifetime, the RMS value of this current must be less than the high frequency ripple current rating of the capacitor. The following formula will give an approximate value for RMS ripple current. This formula assumes continuous mode and large inductor value. Small inductors will give U W U U somewhat higher ripple current, especially in discontinuous mode. The exact formulas are very complex and appear in Application Note 44, pages 30 and 31. For our purposes here I have simply added a fudge factor (ff). The value for ff is about 1.2 for higher load currents and L ≥10µH. It increases to about 2.0 for smaller inductors at lower load currents. Capacitor IRMS = ff IOUT ff = Fudge factor (1.2 to 2.0) Diode Current ( )( ) VOUT VIN Average diode current is equal to load current. Peak diode current will be considerably higher. Peak diode current: Continuous Mode = IOUT (VIN + VOUT ) + (VIN)(VOUT ) VIN 2(L)( f)( VIN + VOUT ) 2 IOUT VOUT Discontinuous Mode = ( )( ) (L)(f) Keep in mind that during start-up and output overloads, average diode current may be much higher than with normal loads. Care should be used if diodes rated less than 3A are used, especially if continuous overload conditions must be tolerated. 1374fb 27 LT1374 APPLICATIONS INFORMATION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663, Exposed Pad Variation BB) 6.60 ± 0.10 4.50 ± 0.10 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC RECOMMENDED SOLDER PAD 4.30 – 4.48* (.169 – .176) 0.105 – 0.180 (.0041 – .0071) 0.50 – 0.70 (.020 – .028) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 28 U W U U 4.95 – 5.05* (.196 – .204) 3.8 (.149) 16 1514 13 12 1110 9 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 3.0 6.25 – 6.50 (.118) (.246 – .256) 12345678 1.15 (.0453) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) 0.05 – 0.15 (.002 – .006) FE16 TSSOP 1101 1374fb LT1374 PACKAGE DESCRIPTION R Package 7-Lead Plastic DD Pak (LTC DWG # 05-08-1462) 0.060 (1.524) TYP 0.390 – 0.415 (9.906 – 10.541) 15° TYP 0.060 (1.524) 0.183 (4.648) 0.059 (1.499) TYP 0.256 (6.502) 0.060 (1.524) 0.075 (1.905) 0.300 (7.620) BOTTOM VIEW OF DD PAK HATCHED AREA IS SOLDER PLATED COPPER HEAT SINK +0.012 0.143 –0.020 0.040 – 0.060 (1.016 – 1.524) 0.026 – 0.036 (0.660 – 0.914) 0.013 – 0.023 (0.330 – 0.584) U 0.165 – 0.180 (4.191 – 4.572) 0.045 – 0.055 (1.143 – 1.397) +0.008 0.004 –0.004 0.330 – 0.370 (8.382 – 9.398) ( +0.203 0.102 –0.102 ) 0.095 – 0.115 (2.413 – 2.921) 0.050 ± 0.012 (1.270 ± 0.305) ( +0.305 3.632 –0.508 ) R (DD7) 0396 1374fb 29 LT1374 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 30 U 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.053 – 0.069 (1.346 – 1.752) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) TYP SO8 0996 1374fb LT1374 PACKAGE DESCRIPTION T7 Package 7-Lead Plastic TO-220 (Standard) (LTC DWG # 05-08-1422) 0.165 – 0.180 (4.191 – 4.572) 0.390 – 0.415 (9.906 – 10.541) 0.460 – 0.500 (11.684 – 12.700) 0.040 – 0.060 (1.016 – 1.524) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 0.147 – 0.155 (3.734 – 3.937) DIA 0.230 – 0.270 (5.842 – 6.858) 0.570 – 0.620 (14.478 – 15.748) 0.330 – 0.370 (8.382 – 9.398) 0.045 – 0.055 (1.143 – 1.397) 0.620 (15.75) TYP 0.700 – 0.728 (17.780 – 18.491) 0.152 – 0.202 0.260 – 0.320 (3.860 – 5.130) (6.604 – 8.128) 0.026 – 0.036 (0.660 – 0.914) 0.135 – 0.165 (3.429 – 4.191) 0.095 – 0.115 (2.413 – 2.921) 0.013 – 0.023 (0.330 – 0.584) 0.155 – 0.195 (3.937 – 4.953) T7 (TO-220) (FORMED) 1197 1374fb 31 LT1374 TYPICAL APPLICATION Dual Output SEPIC Converter The circuit in Figure 17 generates both positive and negative 5V outputs with a single piece of magnetics. The two inductors shown are actually just two windings on a standard BH Electronics inductor. The topology for the 5V output is a standard buck converter. The – 5V topology would be a simple flyback winding coupled to the buck converter if C4 were not present. C4 creates the SEPIC (Single-Ended Primary Inductance Converter) topology which improves regulation and reduces ripple current in L1. Without C4, the voltage swing on L1B compared to L1A would vary due to relative loading and coupling losses. C4 provides a low impedance path to maintain an equal voltage swing in L1B, improving regulation. In a flyback converter, during switch on time, all the converter’s energy is stored in L1A only, since no current flows in L1B. At switch off, energy is transferred by magnetic coupling into L1B, powering the – 5V rail. C4 pulls L1B positive during switch on time, causing current to flow, and energy to build in L1B and C4. At switch off, the energy stored in both L1B and C4 supply the – 5V rail. This reduces the current in L1A and changes L1B current waveform from square to triangular. For details on this circuit see Design Note 100. INPUT 6V TO 25V GND * L1 IS A SINGLE CORE WITH TWO WINDINGS BH ELECTRONICS #501-0726 ** TOKIN IE475ZY5U-C304 † IF LOAD CAN GO TO ZERO, AN OPTIONAL PRELOAD OF 1k TO 5k MAY BE USED TO IMPROVE LOAD REGULATION RELATED PARTS PART NUMBER DESCRIPTION LT1074/LT1076 Step-Down Switching Regulators LTC®1148 High Efficiency Synchronous Step-Down Switching Regulator LTC1149 High Efficiency Synchronous Step-Down Switching Regulator LTC1174 High Efficiency Step-Down and Inverting DC/DC Converter LT1176 Step-Down Switching Regulator LT1370 High Efficiency DC/DC Converter LT1371 High Efficiency DC/DC Converter LT1372/LT1377 500kHz and 1MHz High Efficiency 1.5A Switching Regulators LTC1735 High Efficiency Step-Down Converter LT1765 3A Step-Down Switching Regulator LT1766 1.5A Step-Down Switching Regulator LT1767 1.5A Step-Down Switching Regulator Burst Mode is a registered trademark of Linear Technology Corporation. COMMENTS 40V Input, 100kHz, 5A and 2A External FET Switches External FET Switches 0.5A, 150kHz Burst Mode® Operation PDIP LT1076 42V, 6A, 500kHz Switch 35V, 3A, 500kHz Switch Boost Topology External Switches, Very High Efficiency 1.25MHz, 3A, 25V Input, SO-8 and TSSOP16 Packages 200kHz, 1.5A, 60V Input, SO-8 and GN16 Packages 1.25MHz, 1.5A, 25V Input, MS8 Package 1374fb 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U VIN BOOST VSW C2 0.27µF D2 CMDSH-3 L1A* 6.8µH OUTPUT 5V LT1374-5 BIAS SHDN GND SENSE VC RC 470Ω CC 0.01µF C4** 4.7nF + D1 MBRD340 + C3 22µF 35V TANT C1** 100µF 10V TANT + L1B* D3 MBRD340 + C5** 100µF 10V TANT OUTPUT –5V† 1374 F17 Figure 17. Dual Output SEPIC Converter LT/TP 0102 1.5K REV B • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 1998