LT1640AHCS8

LT1640AL/LT1640AH Negative Voltage Hot Swap Controller FEATURES s s s s s s s s DESCRIPTIO Allows Safe Board Insertion and Removal from a Live – 48V Backplane Operates from –10V to – 80V Programmable Inrush Current Allows 50mA of Reverse Drain Pin Current Programmable Electronic Circuit Breaker Programmable Overvoltage Protection Programmable Undervoltage Lockout Power Good Control Output APPLICATIO S s s s Central Office Switching – 48V Distributed Power Systems Negative Power Supply Control The LT®1640AL/LT1640AH are 8-pin, negative voltage Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable electronic circuit breaker protects the system against shorts. The PWRGD (LT1640AL) or PWRGD (LT1640AH) signal can be used to directly enable a power module. The LT1640AL is designed for modules with a low enable input and the LT1640AH for modules with a high enable input. The LT1640AL/LT1640AH are available in 8-pin PDIP and SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO GND GND R4† 562k 1% UV = 37V R5† 9.09k 1% R6† 10k 1% * 8 VDD 3 UV LT1640AL 2 OV VEE 4 SENSE 5 C1† 150nF 25V 4 2 GATE 6 (SHORT PIN) CONTACT BOUNCE PWRGD 1 OV = 71V DRAIN 7 R2 10Ω 5% R3 † 18k C2 5% 3.3nF 100V 2 ON/OFF 1 9 VOUT+ VIN+ 8 SENSE + 7 TRIM –6 SENSE 4 5 VOUT– VIN– LUCENT JW050A1-E 5V † 3 – 48V 1 R1† 0.02Ω 5% Q1 IRF530 † * DIODES INC. SMAT70A THESE COMPONENTS ARE APPLICATION SPECIFIC AND MUST BE SELECTED BASED UPON OPERATING CONDITIONS AND DESIRED PERFORMANCE. SEE APPLICATIONS INFORMATION. C3 0.1µF 100V + C4 100µF 100V + C5 100µF 16V 1640A TA01 U Input Inrush Current 1640A F07b U U 1 LT1640AL/LT1640AH ABSOLUTE MAXIMUM RATINGS U WW U W (Note 1), All Voltages Referred to VEE Supply Voltage (VDD – VEE) .................... – 0.3V to 100V PWRGD, PWRGD Pins ........................... – 0.3V to 100V DRAIN Pin ................................................. – 2V to 100V SENSE, GATE Pins .................................... – 0.3V to 20V UV, OV Pins .............................................. – 0.3V to 60V Maximum Junction Temperature ......................... 125°C Operating Temperature Range LT1640ALC/LT1640AHC ........................ 0°C to 70°C LT1640ALI/LT1640AHI ...................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C PACKAGE/ORDER I FOR ATIO TOP VIEW PWRGD 1 OV 2 UV 3 VEE 4 N8 PACKAGE 8-LEAD PDIP 8 7 6 5 VDD DRAIN GATE SENSE ORDER PART NUMBER LT1640ALCN8 LT1640ALCS8 LT1640ALIN8 LT1640ALIS8 S8 PART MARKING 1640AL 640ALI PWRGD 1 OV 2 UV 3 VEE 4 N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 120°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL DC VDD IDD VCB IPU IPD ISENSE ∆VGATE VUVH VUVL VUVHY IINUV VOVH VOVL VOVHY IINOV Supply Operating Range Supply Current Circuit Breaker Trip Voltage GATE Pin Pull-Up Current GATE Pin Pull-Down Current SENSE Pin Current External Gate Drive UV Pin High Threshold Voltage UV Pin Low Threshold Voltage UV Pin Hysteresis UV Pin Input Current OV Pin High Threshold Voltage OV Pin Low Threshold Voltage OV Pin Hysteresis OV Pin Input Current VOV = VEE VUV = VEE PARAMETER The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted. CONDITIONS q UV = 3V, OV = VEE, SENSE = VEE VCB = (VSENSE – VEE) Gate Drive On, VGATE = VEE Any Fault Condition VSENSE = 50mV (VGATE – VEE), 15V ≤ VDD ≤ 80V (VGATE – VEE), 10V ≤ VDD < 15V UV Low to High Transition UV High to Low Transition OV Low to High Transition OV High to Low Transition 2 U TOP VIEW 8 7 6 5 VDD DRAIN GATE SENSE W ORDER PART NUMBER LT1640AHCN8 LT1640AHCS8 LT1640AHIN8 LT1640AHIS8 S8 PART MARKING 1640AH 640AHI S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 120°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) MIN 10 TYP MAX 80 UNITS V mA mV µA mA µA V V V V mV µA V V mV µA q q q 1.3 40 – 30 24 50 – 45 50 – 20 13.5 8 1.243 1.223 20 – 0.02 1.198 1.165 1.223 1.203 20 – 0 .03 5 60 – 60 70 18 15 1.272 1.247 – 0.5 1.247 1.232 – 0.5 q q q q 10 6 1.213 1.198 q q q q LT1640AL/LT1640AH ELECTRICAL CHARACTERISTICS SYMBOL VPG VPGHY IDRAIN VOL PARAMETER Power Good Threshold Power Good Threshold Hysteresis Drain Input Bias Current PWRGD Output Low Voltage VDRAIN = 48V PWRGD (LT1640AL), (VDRAIN – VEE) < VPG IOUT = 1mA IOUT = 5mA PWRGD (LT1640AH), VDRAIN = 5V IOUT = 1mA PWRGD (LT1640AL), VDRAIN =48V, VPWRGD = 80V PWRGD (LT1640AH), (VDRAIN – VEE) < VPG q q The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted. CONDITIONS VDRAIN – VEE, High to Low Transition MIN 1.1 10 TYP 1.4 0.4 50 0.48 1.50 0.75 0.05 2 6.5 500 0.8 3.0 1.0 10 MAX 2.0 UNITS V V µA V V V µA kΩ PWRGD Output Low Voltage (PWRGD – DRAIN) IOH ROUT AC tPHLOV tPHLUV tPLHOV tPLHUV tPHLSENSE tPHLPG tPLHPG OV High to GATE Low UV Low to GATE Low OV Low to GATE High UV High to GATE High SENSE High to Gate Low DRAIN Low to PWRGD Low DRAIN Low to (PWRGD – DRAIN) High DRAIN High to PWRGD High DRAIN High to (PWRGD – DRAIN) Low Output Leakage Power Good Output Impedance (PWRGD to DRAIN) q q q Figures 1, 2 Figures 1, 3 Figures 1, 2 Figures 1, 3 Figures 1, 4 (LT1640AL) Figures 1, 5 (LT1640AH) Figures 1, 5 (LT1640AL) Figures 1, 5 (LT1640AH) Figures 1, 5 2 1.7 1.5 5.5 6.5 3 0.5 0.5 0.5 0.5 4 µs µs µs µs µs µs µs µs µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 1.8 1.7 SUPPLY CURRENT (mA) TA = 25°C 1.6 1.5 1.4 1.3 1.2 1.1 0 0 20 80 60 SUPPLY VOLTAGE (V) 40 100 1640A G01 SUPPLY CURRENT (mA) 1.4 1.3 1.2 1.1 GATE VOLTAGE (V) UW Supply Current vs Temperature 1.6 1.5 VDD = 48V 15 14 13 12 11 10 9 8 7 Gate Voltage vs Supply Voltage TA = 25°C 1.0 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640A G02 6 0 20 80 60 40 SUPPLY VOLTAGE (V) 100 1640A G03 3 LT1640AL/LT1640AH TYPICAL PERFOR A CE CHARACTERISTICS Gate Voltage vs Temperature 15.0 14.5 14.0 13.5 13.0 12.5 12.0 – 50 TRIP VOLTAGE (mV) VDD = 48V GATE PULL-UP CURRENT (µA) GATE VOLTAGE (V) – 25 25 50 0 TEMPERATURE (°C) Gate Pull-Down Current vs Temperature 55 VGATE = 2V 0.5 PWRGD OUTPUT LOW VOLTAGE (V) GATE PULL-DOWN CURRENT (mA) OUTPUT IMPEDANCE (kΩ) 52 49 46 43 40 – 50 – 25 0 50 25 TEMPERATURE (°C) PI FU CTIO S PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin will toggle when VDRAIN is within VPG of VEE. This pin can be connected directly to the enable pin of a power module. When the DRAIN pin of the LT1640AL is above VEE by more than VPG, the PWRGD pin will be high impedance, allowing the pull-up current of the module’s enable pin to pull the pin high and turn the module off. When VDRAIN drops below VPG, the PWRGD pin sinks current to VEE, pulling the enable pin low and turning on the module. When the DRAIN pin of the LT1640AH is above VEE by more than VPG, the PWRGD pin will sink current to the DRAIN pin which pulls the module’s enable pin low, forcing it off. When VDRAIN drops below VPG, the PWRGD sink current is turned off and a 6.5k resistor is connected between PWRGD and DRAIN, allowing the module’s pullup current to pull the enable pin high and turn on the module. 4 UW 75 1640A G04 Circuit Breaker Trip Voltage vs Temperature 55 54 53 52 51 50 49 48 – 50 48 47 46 45 44 43 42 41 Gate Pull-Up Current vs Temperature VGATE = 0V 100 – 25 50 0 25 TEMPERATURE (°C) 75 100 1640A G05 40 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640A G06 PWRGD Output Low Voltage vs Temperature (LT1640AL) 8 IOUT = 1mA PWRGD Output Impedance vs Temperature (LT1640AH) VDRAIN – VEE > 2.4V 0.4 7 6 5 4 3 2 – 50 0.3 0.2 0.1 75 100 1640A G07 0 – 50 – 25 25 50 0 TEMPERATURE (°C) 75 100 1640A G08 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640A G09 U U U LT1640AL/LT1640AH PIN FUNCTIONS OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.223V low-to-high threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.203V high-to-low threshold. UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.223V high to low threshold, an undervoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.243 low-to-high threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the circuit breaker will trip when the voltage across the resistor exceeds 50mV. Noise spikes of less than 2µs are filtered out and will not trip the circuit breaker. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, VEE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low and (VSENSE – VEE) < 50mV. The GATE pin is pulled high by a 45µA current source and pulled low with a 50mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel and the V – pin of the power module. When the DRAIN pin is below VPG, the PWRGD or PWRGD pin will toggle. In some conditions, the DRAIN pin is pulled below VEE. The part is not damaged if the reverse DRAIN pin current is limited to 50mA. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. The input supply voltage ranges from 10V to 80V. BLOCK DIAGRA UV REF OV –+ VEE SENSE + – W + + – – U U U VDD VCC AND REFERENCE GENERATOR VCC REF OUTPUT DRIVE PWRGD/PWRGD 50mV LOGIC AND GATE DRIVE + + – VEE VPG – 1640A BD GATE DRAIN 5 LT1640AL/LT1640AH TEST CIRCUIT V+ 5V R 5k PWRGD/PWRGD VDD OV VOV DRAIN + – VDRAIN 48V LT1640AL/LT1640AH UV GATE SENSE VUV VEE VSENSE 1640A F01 Figure 1. Test Circuit TIMING DIAGRAMS 2V OV 0V tPHLOV GATE tPLHOV 1.223V 1.203V 1V Figure 2. OV to GATE Timing SENSE 50mV tPHLSENSE GATE PWRGD 1V 1640A F04 Figure 4. SENSE to GATE Timing 6 W UW 2V UV 0V 1.223V 1.243V tPHLUV GATE tPLHUV 1V 1640A F02 1V 1V 1640A F03 Figure 3. UV to GATE Timing 1.8V DRAIN VEE tPLHPG 1.4V tPHLPG VEE 1.8V DRAIN 0V 1V 1V 1.4V tPLHPG PWRGD VPWRGD – VDRAIN = 0V tPHLPG 1V 1V 1640A F05 Figure 5. DRAIN to PWRGD/PWRGD Timing LT1640AL/LT1640AH APPLICATIO S I FOR ATIO Hot Circuit Insertion When circuit boards are inserted into a live – 48V backplane, the bypass capacitors at the input of the board’s power module or switching power supply can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board’s components and cause glitches on the system power supply. The LT1640A is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage, overvoltage and overcurrent protection while keeping the power module off until its input voltage is stable and within tolerance. GND GND (SHORT PIN) R4 562k 1% UV = 37V R5 9.09k 1% R6 10k 1% VDD 3 UV LT1640AH 2 OV VEE 4 SENSE 5 C1 150nF 25V 4 2 GATE 6 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V DRAIN 7 PWRGD 1 OV = 71V * 3 – 48V * DIODES INC. SMAT70A 1 R1 0.02Ω 5% Figure 6a. Inrush Control Circuitry U Power Supply Ramping The input to the power module on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 6a, all waveforms are with respect to the VEE pin of the LT1640A). R1 provides current fault detection and R2 prevents high frequency oscillations. Resistors R4, R5 and R6 provide undervoltage and overvoltage sensing. By ramping the gate of Q1 up at a slow rate, the surge current charging load capacitors C3 and C4 can be limited to a safe value when the board makes connection. Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The inrush current can be calculated with the following equation: IINRUSH = (45µA • CL)/C2 where CL is the total load capacitance equal to C3 + C4 + module input capacitance. 8 C3 0.1µF 100V W UU + VICOR VI-J3D-CY C4 100µF 100V VIN+ GATE IN VIN– VOUT– VOUT+ 5V + C5 100µF 16V 1640A F06a Q1 IRF530 7 LT1640AL/LT1640AH APPLICATIO S I FOR ATIO Capacitor C1 and resistor R3 prevent Q1 from momentarily turning on when the power pins first make contact. Without C1 and R3, capacitor C2 would pull the gate of Q1 up to a voltage roughly equal to VEE • C2/CGS(Q1) before the LT1640A could power up and actively pull the gate low. By placing capacitor C1 in parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R3, the problem is solved. The value of C1 should be:  VINMAX − VTH    • (C 2 + C GD )   VTH where VTH is the MOSFET’s minimum gate threshold and VINMAX is the maximum operating input voltage. CONTACT BOUNCE Figure 6b. Inrush Control Waveforms 8 U R3’s value is not critical and is given by (VINMAX + ∆VGATE)/ 5mA. The waveforms are shown in Figure 6b. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT1640A senses an undervoltage condition and the GATE is immediately pulled low when the power pins are disconnected. Once the power pins stop bouncing, the GATE pin starts to ramp up. When Q1 turns on, the GATE voltage is held constant by the feedback network of R3 and C2. When the DRAIN voltage has finished ramping, the GATE pin then ramps to its final value. 1640A F07b W UU LT1640AL/LT1640AH APPLICATIO S I FOR ATIO Electronic Circuit Breaker The LT1640A features an electronic circuit breaker function that protects against short circuits or excessive supply currents. By placing a sense resistor between the VEE and SENSE pin, the circuit breaker will be tripped whenever the voltage across the sense resistor is greater than 50mV for more than 3µs as shown in Figure 7. Note that the circuit breaker threshold should be set sufficiently high to account for the sum of the load current and the inrush current. If the load current can be controlled by the PWRGD/PWRGD pin (as in Figure 6a), the threshold can be set lower, since it will never need to accommodate inrush current and load current simultaneously. When the circuit breaker trips, the GATE pin is immediately pulled to VEE and the external N-channel turns off. The GATE pin will remain low until the circuit breaker is reset by pulling UV low, then high or cycling power to the part. If more than 3µs deglitching time is needed to reject current noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 8. R7 and C3 act as a lowpass filter that will slow down the SENSE pin voltage from rising too fast. Since the SENSE pin will source current, typically 20µA, there will be a voltage drop Figure 7. Short-Circuit Protection Waveforms U on R7. This voltage will be counted into the circuit breaker trip voltage just as the voltage across the sense resistor. A small resistor is recommended for R7. A 100Ω for R7 will cause a 2mV error. The following equation can be used to estimate the delay time at the SENSE pin: W UU  V( t) – V( tO ) t = –R • C • In  1 –  Vi – V( tO )   Where V(t) is the circuit breaker trip voltage, typically 50mV. V(tO) is the voltage drop across the sense resistor before the short or overcurrent condition occurs. Vi is the voltage across the sense resistor when the short current or overcurrent is applied on it. Example: A system has a 1A current load and a 0.02Ω sense resistor is used. An extended delay circuit needs to be designed for a 50µs delay time after the load jumps to 5A. In this case: V(t) = 50mV V(tO) = 20mV Vi = 5A • 0.02Ω = 100mV If we choose R = 100Ω, we will get C = 1µF. GND GND (SHORT PIN) 8 R4 562k 1% UV = 37V R5 9.09k 1% R6 10k 1% VDD 3 UV LT1640AL 2 OV VEE 4 C3 SENSE 5 GATE 6 DRAIN 7 PWRGD 1 OV = 71V + CL 100µF 100V * R1 0.02Ω 5% 1 2 R7 C1 150nF 25V 4 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V Q1 IRF530 1640A F08 3 – 48V 1640A F07 * DIODES INC. SMAT70A Figure 8. Extending the Short-Circuit Protection Delay 9 LT1640AL/LT1640AH APPLICATIO S I FOR ATIO Under some conditions, a short circuit at the output can cause the input supply to dip below the UV threshold, resetting the circuit breaker immediately. The LT1640A then cycles on and off repeatedly until the short is removed. This can be minimized by adding a deglitching delay to the UV pin with a capacitor from UV to VEE. This capacitor forms an RC time constant with the resistors at UV, allowing the input supply to recover before the UV pin resets the circuit breaker. A circuit that automatically resets the circuit breaker after a current fault is shown in Figure 9. (SHORT PIN) GND GND R7 1M 5% C4 1µF 100V 2 * Q2 2N2222 3 Q3 ZVN3310 R8 510k 5% D1 1N4148 – 48V * DIODES INC. SMAT70A Figure 9. Automatic Restart After Current Fault 10 U Transistors Q2 and Q3 along with R7, R8, C4 and D1 form a programmable one-shot circuit. Before a short occurs, the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts to charge C4 and Q2 turns on, pulling the UV pin low and resetting the circuit breaker. As soon as C4 is fully charged, R8 turns off Q2, UV goes high and the GATE starts to ramp up. Q3 turns back on and quickly pulls node 2 back to VEE. Diode D1 clamps node 3 one diode drop below VEE. The duty cycle is set to 10% to prevent Q1 from overheating. R4 562k 1% R5 9.09k 1% R6 10k 1% 8 VDD 3 UV LT1640AL 2 OV VEE 4 SENSE 5 C1 150nF 25V 4 2 GATE 6 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V Q1 IRF530 1640A F09a W UU PWRGD 1 + DRAIN 7 C3 100µF 100V 3 1 R1 0.02Ω 5% 1640A F09b LT1640AL/LT1640AH APPLICATIO S I FOR ATIO Undervoltage and Overvoltage Detection The UV (Pin 3) and OV (Pin 2) pins can be used to detect undervoltage and overvoltage conditions at the power supply input. The UV and OV pins are internally connected to analog comparators with 20mV of hysteresis. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low. The undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in (SHORT PIN) VUV = 1.223 R4 + R5+ R6 VOV = 1.223 R6 Figure 10a. Undervoltage and Overvoltage Sensing GND GND R4 506k 1% UV UV OV = 37.6V = 43V = 71V R5 8.87k 1% * 3 – 48V * DIODES INC. SMAT70A 1 Figure 10b. Programmable Hysteresis for Undervoltage Detection U Figure 10a. With R4 = 562k, R5 = 9.09k and R6 = 10k, the undervoltage threshold is set to 37V and the overvoltage threshold is set to 71V. The resistor divider will also amplify the 20mV hysteresis at the UV pin and OV pin to 0.6V and 1.2V at the input, respectively. More hysteresis can be added to the UV threshold by connecting resistor R3 between the UV pin and the GATE pin as shown in Figure 10b. GND GND 8 W UU ( ( R4 + R5+ R6 R5 + R6 ) ) R4 3 R5 2 R6 OV UV VDD LT1640AL LT1640AH VEE 4 – 48V 1640A F10a (SHORT PIN) 8 VDD 2 R1 562k 1% R2 16.9k 1% R3 1.62M 1% OV LT1640AL /LT1640AH 3 UV VEE 4 SENSE 5 C1 150nF 25V 4 2 Q1 1640A F10b IRF530 GATE 6 R6 10Ω 5% R1 0.02Ω 5% 11 LT1640AL/LT1640AH APPLICATIO S I FOR ATIO  R2 • R3 + R1 • R3 + R1 • R2  VUV,LH = VUVH   R2 • R3   The new threshold voltage when the input moves from low to high is: where VUVH is typically 1.243V. The new threshold voltage when the input moves from high to low is:  R2 • R3 + R1 • R3 + R1 • R2   R1 VUV,HL = VUVL   –  VGATE •  R2 • R3 R3    where VUVL is typically 1.223V. The new hysteresis value will be:  R2 • R3 + R1 • R3 + R1 • R2   R1 VHYS = VUVHY   +  VGATE •  R2 • R3 R3    With R1 = 562k, R2 = 16.9k and R3 = 1.62M, VGATE = 13.5V and VUVHY = 20mV, the undervoltage threshold will be 43V (from low to high) and 37.6V (from high to low). The hysteresis is 5.4V. A separate resistor divider should be used to set the overvoltage threshold given by: GND GND 8 R4 3 R5 2 R6 VEE 4 * C1 3 – 48V * DIODES INC. SMAT70A 1 R1 2 4 SENSE 5 OV LT1640AH UV VDD R7 6.5k (SHORT PIN) + – VPG Figure 11. Active High Enable Module 12 U  R4 + R5  VOV = VOVH    R5  W UU With R4 = 506k, R5 = 8.87k and VOVH = 1.223V, the overvoltage threshold will be 71V. PWRGD/PWRGD Output The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module is within tolerance. The LT1640AL has a PWRGD output for modules with an active low enable input, and the LT1640AH has a PWRGD output for modules with an active high enable input. When the DRAIN voltage of the LT1640AH is high with respect to VEE (Figure 11), the internal transistor Q3 is turned off and R7 and Q2 clamp the PWRGD pin one diode drop (≈ 0.7V) above the DRAIN pin. Transistor Q2 sinks the module’s pull-up current and the module turns off. When the DRAIN voltage drops below VPG, Q3 will turn on, shorting the bottom of R7 to DRAIN and turning Q2 off. The pull-up current in the module then flows through R7, pulling the PWRGD pin high and enabling the module. ACTIVE HIGH ENABLE MODULE VIN+ PWRGD 1 VOUT+ + Q2 Q3 C3 ON/OFF + – VEE GATE 6 R2 DRAIN 7 VIN– VOUT– R3 C2 1640A F11 Q1 LT1640AL/LT1640AH APPLICATIO S I FOR ATIO When the DRAIN voltage of the LT1640AL is high with respect to VEE, the internal pull-down transistor Q2 is off and the PWRGD pin is in a high impedance state (Figure 12). The PWRGD pin will be pulled high by the module’s internal pull-up current source, turning the module off. When the DRAIN voltage drops below VPG, Q2 will turn on and the PWRGD pin will pull low, enabling the module. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good as shown in Figure 13. Gate Pin Voltage Regulation When the supply voltage to the chip is more than 15.5V, the GATE pin voltage is regulated at 13.5V above VEE. If the supply voltage is less than 15.5V, the GATE voltage will be about 2V below the supply voltage. At the minimum 10V supply voltage, the gate voltage is guaranteed to be greater GND GND (SHORT PIN) R4 3 R5 LT1640AL UV 2 + – OV VPG R6 VEE 4 * C1 3 – 48V * DIODES INC. SMAT70A 1 R1 2 4 1640A F12 Figure 12. Active Low Enable Module U than 6V. The gate voltage will be no greater than 18V for supply voltages up to 80V. Drain Pin Protection A unique feature of the LT1640A is the ruggedness of the DRAIN pin. The DRAIN is designed to withstand negative voltages (with respect to VEE) without requiring an external diode. A short circuit on the – 48V backplane pulls up the VEE pin, but due to the storage capacitor C3 (Figure 12), the DRAIN pin is held more negative than the VEE pin. The body diode of Q1, plus the I • R drop across R1 (if R1 is small), holds the DRAIN pin to less than 1.5V below VEE. A 1.5V reverse voltage gives rise to a 50mA reverse drain current, which is within the design capability of the LT1640A. A design with R1 larger than 0.1Ω may require a resistor in series with the DRAIN pin to not exceed the 50mA drain current maximum. ACTIVE LOW ENABLE MODULE 8 VDD PWRGD Q2 VEE DRAIN SENSE 5 GATE 6 R2 R3 C2 7 VIN– VOUT– 1 VIN+ VOUT+ W UU + – + C3 ON/OFF Q1 13 LT1640AL/LT1640AH APPLICATIO S I FOR ATIO GND GND R7 51k 5% PWRGD (SHORT PIN) R4 562k 1% R5 9.09k 1% R6 10k 1% * 3 UV LT1640AL PWRGD 2 OV VEE 4 SENSE 5 C1 150nF 25V 4 2 GATE 6 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V Q1 IRF530 1640A F13 3 – 48V * DIODES INC. SMAT70A 1 R1 0.02Ω 5% Figure 13. Using PWRGD to Drive an Optoisolator PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 14 U 8 VDD 1 4N25 U W UU + C3 100µF 100V DRAIN 7 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 0.100 (2.54) BSC LT1640AL/LT1640AH PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC SO8 1298 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT1640AL/LT1640AH TYPICAL APPLICATION Using an EMI Filter Module Many applications place an EMI filter module in the power path to prevent switching noise of the module from being injected back onto the power supply. A typical application R7 51k 5% GND GND R4 562k 1% R5 9.09k 1% R6 10k 1% * 3 – 48V * DIODES INC. SMAT70A 1 8 VDD 3 UV 1 PWRGD DRAIN LT1640AL 2 OV VEE 4 R1 0.02Ω 5% 2 GATE SENSE 5 4 Q1 IRF530 C1 150nF 25V 6 7 C2 3.3nF 100V C3 0.1µF 100V VIN+ R3 18k 5% R2 10Ω 5% VOUT+ C4 0.1µF 100V 2 ON/OFF (SHORT PIN) 4N25 1 LUCENT JW050A1-E VIN+ VOUT+ SENSE + RELATED PARTS PART NUMBER LTC®1421 LTC1422 LT1641 LTC1642 LTC1643 LTC1645 LTC1646 LTC1647 DESCRIPTION Dual Channel, Hot Swap Controller Hot Swap Controller in SO-8 Positive 48V Hot Swap Controller in SO-8 Fault Protected Hot Swap Controller PCI Hot Swap Controller Dual Hot Swap Controller CompactPCI Hot Swap Controller Dual Hot Swap Controller TM CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U using the Lucent FLTR100V10 filter module is shown in Figure 14. When using a filter, an optoisolator is required to prevent common mode transients from destroying the PWRGD and ON/OFF pins. 9 8 7 6 5V + TRIM SENSE – LUCENT FLTR100V10 VIN– VOUT– + C5 100µF 100V C6 0.1µF 100V C7 100µF 16V 4 VIN– 3 VOUT– CASE 5 CASE 1640A F14 Figure 14. Typical Application Using a Filter Module COMMENTS Operates from 3V to 12V System Reset Output with Programmable Delay, 3V to 12V Foldback Analog Current Limit Operates Up to 16.5V, Protected to 33V 3.3V, 5V, 12V, – 12V Supplies for PCI Bus Operates from 1.2V to 12V, Power Sequencing 3.3V, 5V Supplies, 1V Precharge, Local PCI Reset Logic Dual ON Pins for Supplies from 3V to 15V 1640alahf LT/TP 0501 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2001