LT1683IG

FEATURES s s s LT1683 Ultralow Noise Push-Pull DC/DC Controller DESCRIPTIO The LT ®1683 is a switching regulator controller designed to lower conducted and radiated electromagnetic interference (EMI). Ultralow noise and EMI are achieved by controlling the voltage and current slew rates of external N-channel MOSFET switches. Current and voltage slew rates can be independently set to optimize harmonic content of the switching waveforms vs efficiency. The LT1683 can reduce high frequency harmonic power by as much as 40dB with only minor losses in efficiency. The LT1683 utilizes a dual output (push-pull) current mode architecture optimized for low noise topologies. The IC includes gate drivers and all necessary oscillator, control and protection circuitry. Unique error amp circuitry can regulate both positive and negative voltages. The oscillator may be synchronized to an external clock for more accurate placement of switching harmonics. Protection features include gate drive lockout for low VIN, opposite gate lockout, soft-start, output current limit, short-circuit current limiting, gate drive overvoltage clamp and input supply undervoltage lockout. s s s s s s Greatly Reduced Conducted and Radiated EMI Low Switching Harmonic Content Independent Control of Output Switch Voltage and Current Slew Rates Greatly Reduced Need for External Filters Dual N-Channel MOSFET Drivers 20kHz to 250kHz Oscillator Frequency Easily Synchronized to External Clock Regulates Positive and Negative Voltages Easier Layout Than with Conventional Switchers APPLICATIO S s s s s s s Power Supplies for Noise Sensitive Communication Equipment EMI Compliant Offline Power Supplies Precision Instrumentation Systems Isolated Supplies for Industrial Automation Medical Instruments Data Acquisition Systems , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO 51k 510Ω 0.5W FZT853 1N4148 2N3904 8.2V 11V 23.2k 14 976Ω 1.2nF 7 16.9k 25k 25k 3.3k 3.3k 1.5k 0.22µF 22nF 10nF 8 16 15 12 5 6 SHDN V5 SYNC CT LT1683 RT RVSL RCSL VC SS 13 GND 11 GATE B CS GATE A CAP B 68µF 20V 17 3 VIN GCL CAP A 2 1 5pF 18 19 4 Si9422 10µF 20V Ultralow Noise 48V to 5V DC/DC Converter 48V 39µF 63V MIDCOM 31244 MBR0530 MBRS340 22µH 150µF OS-CON 5pF 10pF 200V MBRS340 10pF 200V 30pF Si9422 0.1Ω PGND FB NFB 10 1683 TA01 OPTIONAL B 22µH 2×100µF POSCAP A 5V/2A A 200µV/DIV B 20mV/DIV 20 7.50k 9 30pF 2.49k 5µs/DIV 1683 TA01a U U U 5V Output Noise (Bandwidth = 100MHz) 200µVP-P 1683f 1 LT1683 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW GATE A CAP A GCL CS V5 SYNC CT RT FB 1 2 3 4 5 6 7 8 9 20 PGND 19 GATE B 18 CAP B 17 VIN 16 RVSL 15 RCSL 14 SHDN 13 SS 12 VC 11 GND Supply Voltage (VIN) ................................................ 20V Gate Drive Current ..................................... Internal Limit V5 Current ................................................. Internal Limit SHDN Pin Voltage .................................................... 20V Feedback Pin Voltage (Trans. 10ms) ...................... ±10V Feedback Pin Current ............................................ 10mA Negative Feedback Pin Voltage (Trans. 10ms) ........ ±10V CS Pin .......................................................................... 5V GCL Pin ..................................................................... 16V SS Pin .......................................................................... 3V Operating Junction Temperature Range (Note 3) ............................................ – 40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LT1683EG LT1683IG NFB 10 G PACKAGE 20-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 110°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and other pins open unless otherwise noted. SYMBOL VREF IFB FBREG VNFR INFR NFBREG gm IESK IESRC VCLH VCLL AV FBOV ISS PARAMETER Reference Voltage Feedback Input Current Reference Voltage Line Regulation Negative Feedback Reference Voltage Negative Feedback Input Current Negative Feedback Reference Voltage Line Regulation Error Amplifier Transconductance Error Amp Sink Current Error Amp Source Current Error Amp Clamp Voltage Error Amp Clamp Voltage Error Amplifier Voltage Gain FB Overvoltage Shutdown Soft-Start Charge Current Outputs Drivers Disabled VSS = 1V CONDITIONS Measured at Feedback Pin VFB = VREF 2.7V ≤ VIN ≤ 20V Measured at Negative Feedback Pin with Feedback Pin Open VNFB = VNFR 2.7V ≤ VIN ≤ 20V ∆IC = ± 50µA q q q q q q ELECTRICAL CHARACTERISTICS MIN 1.235 TYP 1.250 250 0.012 MAX 1.265 1000 0.03 – 2.45 UNITS V nA %/V V µA Error Amplifiers – 2.56 – 37 1100 700 120 120 – 2.500 – 25 0.009 1500 200 200 1.27 0.12 0.03 2200 2500 350 350 µmho µmho µA µA V V V/V V VFB = VREF + 150mV, VC = 0.9V VFB = VREF – 150mV, VC = 0.9V High Clamp, VFB = 1V Low Clamp, VFB = 1.5V q q 180 250 1.47 9.0 12 1683f 2 U %/V µA W U U WW W LT1683 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and other pins open unless otherwise noted. SYMBOL fMAX fSYNC VSYNC RSYNC DCMAX VGON VGOFF IGSO IGSK VINUVLO tIBL VSENSE VSENSEF VSLEWR VSLEWF VISLEWR VISLEWF VINMIN IVIN VSHDN ∆VSHDN ISHDN V5 IV5SC PARAMETER Max Switch Frequency Synchronization Frequency Range SYNC Pin Input Threshold SYNC Pin Input Resistance Maximum Switch Duty Cycle Gate On Voltage Gate Off Voltage Max Gate Source Current Max Gate Sink Current Gate Drive Undervoltage Lockout (Note 5) Switch Current Limit Blanking Time Sense Voltage Shutdown Voltage Sense Voltage Fault Threshold Output Voltage Slew Rising Edge Output Voltage Slew Falling Edge Output Current Slew Rising Edge (CS Pin Voltage) Output Current Slew Falling Edge (CS Pin Voltage) Minimum Input Voltage (Note 4) Supply Current (Note 2) Shutdown Turn-On Threshold Shutdown Turn-On Voltage Hysteresis Shutdown Input Current Hysteresis 5V Reference Voltage 5V Reference Short-Circuit Current 6.5V ≤ VIN ≤ 20V, IV5 = 5mA 6.5V ≤ VIN ≤ 20V, IV5 = – 5mA VIN = 6.5V Source VIN = 6.5V Sink RVSL = RCSL = 17k RVSL = RCSL = 17k RVSL = RCSL = 17k RVSL = RCSL = 17k VGCL = VIN RVSL = RCSL = 17k, VIN = 12 RVSL = RCSL = 17k, VIN = 20 q q q q q q ELECTRICAL CHARACTERISTICS CONDITIONS MIN TYP 250 MAX UNITS kHz kHz Oscillator and Sync Oscillator Frequency = 250kHz q 290 0.7 1.4 40 2.0 kΩ % 10.7 8.1 0.35 V V V A A Gate Drives (Specifications Apply to Either A or B Unless Otherwise Noted) RVSL = RCSL = 4.85k, Osc Frequency = 25kHz VIN = 12, GCL = 12 VIN = 12, GCL = 8 VIN = 12V VIN = 12V VIN = 12V VGCL = 6.5V, Gates Enabled 0.3 0.3 7.3 100 VC Pulled Low q q q 45 10 7.6 46 10.4 7.9 0.2 7.5 V ns Current Sense 86 103 230 26 19 2.1 2.1 2.55 25 35 1.31 50 10 4.85 4.80 10 –10 1.39 110 24 5 5 3.6 45 55 1.48 180 35 5.20 5.15 120 300 mV mV V/µs V/µs V/µs V/µs V mA mA V mV µA V V mA mA Slew Control (for the Following Slew Tests See Test Circuit in Figure 1b) Supply and Protection Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Supply current specification includes loads on each gate as in Figure 1a. Actual supply currents vary with operating frequency, operating voltages, V5 load, slew rates and type of external FET. Note 3: The LT1683E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 125°C operating range are assured by design, characterization and correlation with statistical process controls. The LT1683I is guaranteed and tested over the – 40° to 125° operating temperature range. Note 4: Output gate drivers will be enabled at this voltage. The GCL voltage will also determine drivers’ activity. Note 5: Gate drivers are ensured to be on when VIN is greater than the maximum value. 1683f 3 LT1683 TYPICAL PERFOR A CE CHARACTERISTICS Feedback Voltage and Input Current vs Temperature 1.260 1.258 1.256 750 NEGATIVE FEEDBACK VOLTAGE (V) 700 650 600 550 500 450 400 350 300 0 250 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G01 FEEDBACK VOLTAGE (V) 1.254 1.252 1.250 1.248 1.246 1.244 1.242 1.240 –50 –25 Feedback Overvoltage Shutdown vs Temperature 1.70 1.65 1.60 FEEDBACK VOLTAGE (V) 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G03 TRANSCONDUCTANCE (µmho) CURRENT (µA) VC Pin Threshold and Clamp Voltage vs Temperature 1.4 1.2 CS PIN VOLTAGE (mV) VC PIN VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 –50 –25 240 220 200 180 160 140 120 SHDN PIN VOLTAGE (V) 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G06 4 UW Negative Feedback Voltage and Input Current vs Temperature 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 –50 –25 0 3.2 3.0 NFB INPUT CURRENT (µA) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G02 Error Amp Transconductance vs Temperature 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G04 CS Pin Trip and CS Fault Voltage vs Temperature 1.50 FB INPUT CURRENT (nA) FAULT TRIP 0 Error Amp Output Current vs Feedback Pin Voltage from Nominal 500 400 300 200 100 0 –100 –200 –300 –400 –500 –400 –300 –200 –100 0 100 200 300 400 FEEDBACK PIN VOLTAGE FROM NOMINAL (mV) 1683 G05 –40°C 25°C 125°C SHDN Pin On and Off Thresholds vs Temperature 1.45 ON 1.40 1.35 1.30 100 80 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G07 OFF 1.25 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G08 1683f LT1683 TYPICAL PERFOR A CE CHARACTERISTICS SHDN Pin Hysteresis Current vs Temperature 27 24 25 SHDN PIN CURRENT (µA) VIN CURRENT (mA) 23 21 19 17 15 –50 –25 22 20 18 16 14 12 10 –50 –25 VIN = 12 RCSL, RVSL = 5.7k VIN = 20 RCSL, RVSL = 17k VIN = 12 RCSL, RVSL = 17k VC PIN VOLTAGE (V) 1.2 1.0 0.8 0.6 0.4 0.2 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G10 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G09 Slope Compensation 110 GATE DRIVE A/B PIN VOLTAGE (V) PERCENT OF MAX CS VOLTAGE 100 90 80 70 60 50 VC PIN = 0.9V TA = 25°C 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 9.90 9.80 0 10 20 30 DUTY CYCLE (%) 40 50 1683 G12 GCL = 12V 6.3 6.2 VIN = 12V NO LOAD 6.1 6.0 5.9 GATE DRIVE A/B PIN VOLTAGE (V) Gate Drive Undervoltage Lockout Voltage vs Temperature 7.3 7.2 7.1 SS PIN CURRENT (µA) VIN PIN VOLTAGE (V) 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G15 GCL = 6V 8.9 8.7 8.5 8.3 8.1 7.9 7.7 7.5 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G16 V5 PIN VOLTAGE (V) UW VIN Current vs Temperature 1.6 WITH NO EXTERNAL MOSFETs 1.4 CS Pin to VC Pin Transfer Function TA = 25°C 0 0 20 40 60 80 CS PIN VOLTAGE (mV) 100 120 1683 G11 Gate Drive A/B High Voltage vs Temperature 6.5 6.4 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 Gate Drive A/B Low Voltage vs Temperature VIN = 12V NO LOAD GCL = 6V 5.8 5.7 5.6 9.70 –50 –25 0 5.5 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G13 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1683 G14 Soft-Start Current vs Temperature 9.5 9.3 9.1 SS VOLTAGE = 0.9V 5.06 5.04 5.02 5.00 5.08 V5 Voltage vs Load Current T = 125°C T = 25°C T = –40°C 4.98 4.96 –15 –10 –5 0 5 LOAD CURRENT (mA) 10 15 1683 G17 1683f 5 LT1683 PI FU CTIO S Part Supply V5 (Pin 5): This pin provides a 5V output that can sink or source 10mA for use by external components. V5 source current comes from VIN . Sink current goes to GND. VIN must be greater than 6.5V in order for this voltage to be in regulation. If this pin is used, a small capacitor ( VGCL + 0.8V. If this pin is tied to VIN, then undervoltage lockout is disabled. There is an internal 19V Zener tied from this pin to ground to provide a fail-safe for maximum gate voltage. The voltage slew rate is inversely proportional to this capacitance and proportional to the current that the part will sink and source on this pin. That current is inversely proportional to RVSL. RCSL (Pin 15): A resistor to ground sets the current slew rate for the external drive MOSFETs during switching. The minimum resistor value is 3.3k and the maximum value is 68k. The time to slew between on and off states of the MOSFET current will determine how the di/dt related harmonics are reduced. This time is proportional to RCSL and RS (the current sense resistor) and maximum current. Longer times produce a greater reduction of higher frequency harmonics. RVSL (Pin 16): A resistor to ground sets the voltage slew rate for the drains of the external drive MOSFETs. The minimum resistor value is 3.3k and the maximum value is 68k. The time to slew between on and off states on the MOSFET drain voltage will determine how harmonics are reduced from this source. This time is proportional to RVSL, CVA/B and the input voltage. Longer times produce more rolloff of harmonics. CVA/B is the equivalent capacitance from CAP A or B to the drain of the MOSFET. Slew Control CAP A, CAP B (Pins 2, 18): These pins are the feedback nodes for the external voltage slewing capacitors. Normally a small 1pf to 5pf capacitor is connected from this pin to the drain of its respective MOSFET. U U U Switch Mode Control SS (Pin 3): The SS pin allows for ramping of the switch current threshold at startup. Normally a capacitor is placed on this pin to ground. An internal 9µA current source will charge this capacitor up. The voltage on the VC pin cannot exceed the voltage on SS. Thus peak current will ramp up as the SS pin ramps up. During a short circuit fault the SS pin will be discharged to ground thus reinitializing softstart. When SS is below the VC clamp voltage the VC pin will closely track the SS pin. This pin can be left open if not used. 1683f 7 LT1683 PI FU CTIO S CS (Pin 4): This is the input to the current sense amplifier. It is used for both current mode control and current slewing of the external MOSFETs. Current sense is accomplished via a sense resistor (RS) connected from the sources of the external MOSFETs to ground. CS is connected to the top of RS. Current sense is referenced to the GND pin. The switch maximum operating current will be equal to 0.1V/RS. At CS = 0.1V, the gate drivers will be immediately turned off (no slew control). If CS = 0.22V in addition to the drivers being turned off, VC and SS will be discharged to ground (short-circuit protection). This will hasten turn off on subsequent cycles. FB (Pin 9): The feedback pin is used for positive voltage sensing. It is the inverting input to the error amplifier. The noninverting input of this amplifier connects internally to a 1.25V reference. If the voltage on this pin exceeds the reference by 220mV, then the output drivers will immediately turn off the external MOSFETs (no slew control). This provides for output overvoltage protection When this input is below 0.9V then the current sense blanking will be disabled. This will assist start up. NFB (Pin 10): The negative feedback pin is used for sensing a negative output voltage. The pin is connected to the inverting input of the negative feedback amplifier through a 100k source resistor. The negative feedback amplifier provides a gain of –0.5 to the FB pin. The nominal regulation point would be –2.5V on NFB. This pin should be left open if not used. If NFB is being used then overvoltage protection will occur at 0.44V below the NFB regulation point. At NFB < –1.8 current sense blanking will be disabled. VC (Pin 12): The compensation pin is used for frequency compensation and current limiting. It is the output of the error amplifier and the input of the current comparator. Loop frequency compensation can be performed with an RC network connected from the VC pin to ground. The voltage on VC is proportional to the switch peak current. The normal range of voltage on this pin is 0.25V to 1.27V. However, during slope compensation the upper clamp voltage is allowed to increase with the compensation. During a short-circuit fault the VC pin will be discharged to ground. TEST CIRCUITS 20mA 5pF CAP A/CAP B IN5819 CAP A/CAP B 5pF 0.9A IN5819 GATE A/GATE B 2 Figure 1a. Typical Test Circuitry 8 U U U ZVN3306A + – 10 GATE A/GATE B CS 0.1 Si4450DY + – 10 1683 F01a 1683 F01b Figure 1b. Test Circuit for Slew 1683f LT1683 BLOCK DIAGRA + – NFB 100k NEGATIVE FEEDBACK AMP 50k CAP A FB GATE A VREG GCL CVA + 1.25V CVC VC CSS SS COMP RT RT OSCILLATOR CT CT SYNC – + W VIN CIN RCSL SHDN VIN V5 RCSL RVSL RVSL TO DRIVERS REGULATOR MA CVB CAP B GATE B ERROR AMP SLEW CONTROL MB PGND – + + S FF R Q SENSE AMP CS RSENSE – T FF Q QB SUB GND 1683 BD 1683f 9 LT1683 OPERATIO In noise sensitive applications switching regulators tend to be ruled out as a power supply option due to their propensity for generating unwanted noise. When switching supplies are required due to efficiency or input/output constraints, great pains must be taken to work around the noise generated by a typical supply. These steps may include pre and post regulator filtering, precise synchronization of the power supply oscillator to an external clock, synchronizing the rest of the circuit to the power supply oscillator or halting power supply switching during noise sensitive operations. The LT1683 greatly simplifies the task of eliminating supply noise by enabling the design of an inherently low noise switching regulator power supply. The LT1683 is a fixed frequency, current mode switching regulator with unique circuitry to control the voltage and current slew rates of the output switches. Current mode control provides excellent AC and DC line regulation and simplifies loop compensation. Slew control capability provides much greater control over the power supply components that can create conducted and radiated electromagnetic interference. Compliance with EMI standards will be an easier task and will require fewer external filtering components. The LT1683 uses two external N-channel MOSFETs as the power switches. This allows the user to tailor the drive conditions to a wide range of voltages and currents. CURRENT MODE CONTROL Referring to the block diagram. A switching cycle begins with an oscillator discharge pulse, which resets the RS flip-flop, turning on one of the external MOSFET drivers. The switch current is sensed across the external sense resistor and the resulting voltage is amplified and compared to the output of the error amplifier (VC pin). The driver is turned off once the output of the current sense amplifier exceeds the voltage on the VC pin. In this way pulse by pulse current limit is achieved. The toggle flipflop ensures that the two MOSFETs are enabled on alternate clock cycles. Internal slope compensation is provided to ensure stability under high duty cycle conditions. 10 U Output regulation is obtained using the error amp to set the switch current trip point. The error amp is a transconductance amplifier that integrates the difference between the feedback output voltage and an internal 1.25V reference. The output of the error amp adjusts the switch current trip point to provide the required load current at the desired regulated output voltage. This method of controlling current rather than voltage provides faster input transient response, cycle-by-cycle current limiting for better output switch protection and greater ease in compensating the feedback loop. The VC pin is used for loop compensation and current limit adjustment. During normal operation the VC voltage will be between 0.25V and 1.27V. An external clamp on VC or SS may be used for lowering the current limit. The negative voltage feedback amplifier allows for direct regulation of negative output voltages. The voltage on the NFB pin gets amplified by a gain of – 0.5 and driven on to the FB input, i.e., the NFB pin regulates to –2.5V while the amplifier output internally drives the FB pin to 1.25V as in normal operation. The negative feedback amplifier input impedance is 100k (typ) referred to ground. Soft-Start Control of the switch current during start up can be obtained by using the SS pin. An external capacitor from SS to ground is charged by an internal 9µA current source. The voltage on VC cannot exceed the voltage on SS. Thus as the SS pin ramps up the VC voltage will be allowed to ramp up. This will then provide for a smooth increase in switch maximum current. SS will be discharged as a result of the CS voltage exceeding the short circuit threshold of approximately 0.22V. Slew Control Control of output voltage and current slew rates is achieved via two feedback loops. One loop controls the MOSFET drain dV/dt and the other loop controls the MOSFET dI/dt. The voltage slew rate uses an external capacitor between CAP A or CAP B and the respective MOSFET drain. These integrating caps close the voltage feedback loop. The external resistor RVSL sets the current for the integrator. 1683f LT1683 OPERATIO The voltage slew rate is thus inversely proportional to both the value of capacitor and RVSL. The current slew feedback loop consists of the voltage across the external sense resistor, which is internally amplified and differentiated. The derivative is limited to a value set by RCSL. The current slew rate is thus inversely proportional to both the value of sense resistor and RCSL. The two control loops are combined internally so that a smooth transition from current slew control to voltage slew control is obtained. When turning on, the driver current will slew before voltage. When turning off, voltage will slew before current. In general it is desirable to have RVSL and RCSL of similar value. Internal Regulator Most of the control circuitry operates from an internal 2.4V low dropout regulator that is powered from VIN. The internal low dropout design allows VIN to vary from 2.7V to 20V with stable operation of the controller. When SHDN < 1.3V the internal regulator is completely disabled. 5V Regulator A 5V regulator is provided for powering external circuitry. This regulator draws current from VIN and requires VIN to be greater than 6.5V to be in regulation. It can sink or source 10mA. The output is current limited to prevent against destruction from accidental short circuits. Safety and Protection Features There are several safety and protection features on the chip. The first is overcurrent limit. Normally the gate drivers will go low when the output of the internal sense amplifier exceeds the voltage on the VC pin. The VC pin is clamped such that maximum output current is attained when the CS pin voltage is 0.1V. At that level the outputs will be immediately turned off (no slew). The effect of this control is that the output voltage will foldback with overcurrent. In addition, if the CS voltage exceeds 0.22V, the VC and SS pins will be discharged to ground also, resetting the softstart function. Thus if a short is present this will allow for faster MOSFET turnoff and less MOSFET stress. U If the voltage on the FB pin exceeds regulation by approximately 0.22V, the outputs will immediately go low. The implication is that there is an overvoltage fault. The voltage on GCL determines two features. The first is the maximum gate drive voltage. This will protect the MOSFET gate from overvoltage. With GCL tied to a Zener or an external voltage source then the maximum gate driver voltage is approximately VGCL – 0.2V. If GCL is tied to VIN, then the maximum gate voltage is determined by VIN and is approximately VIN – 1.6V. There is an internal 19V Zener on the GCL pin that prevents the gate driver pin from exceeding approximately 19V. In addition, the GCL voltage determines undervoltage lockout of the gate drives. This feature disables the gate drivers if VIN is too low to provide adequate voltage to turn on the MOSFETs. This is helpful during start up to insure the MOSFETs have sufficient gate drive to saturate. If GCL is tied to a voltage source or Zener less than 6.8V, the gate drivers will not turn on until VIN exceeds GCL voltage by 0.8V. For VGCL above 6.5V, the gate drives are insured to be off for VIN < 7.3V and they will be turned on by VGCL + 0.8V. If GCL is tied to VIN, the gate drivers are always enabled (undervoltage lockout is disabled). When driving a push pull transformer, it is important to make sure that both drivers are not on at the same time. Even though runaway cannot occur under such cross conduction with this chip because current slew is regulated, increased current would be possible. This chip has opposite gate lockout whereby when one MOSFET is on the other MOSFET cannot be turned on until the gate of the first drops below 1V. This insures that cross conduction will not occur. The gate drives have current limits for the drive currents. If the sink or source current is greater than 300mA then the current will be limited. The V5 regulator also has internal current limiting that will only guarantee ±10mA output current. 1683f 11 LT1683 OPERATIO There is also an on chip thermal shutdown circuit that will turn off the outputs in the event the chip temperature rises to dangerous levels. Thermal shutdown has hysteresis that will cause a low frequency ( VREG + 0.22V (Output Overvoltage) Set Max Gate Voltage to Prevent FET Gate Breakdown Disable Gate Drives When VIN Is Too Low. Set Via GCL Pin Turn Off Drivers If Chip Temperature Is Too Hot Prevents Opposite Driver from Turning on Until Driver Is Off (Cross Conduction in Transformer) Disable Part When VIN ≅ 2.55V Limit Gate Drive Current Limit Current from V5 Disable Part When SHDN VGCL + 0.8V. This could be used to bias a Zener. The GCL pin has an internal 19V Zener to ground that will provide a failsafe for maximum gate voltage. As an example say we are using a Siliconix Si4480DY which has RDS(ON) rated at 6V. To get 6V, VGCL needs to be set to 6.2V and VIN needs to be at least 7.6V. 1683f W U U 21 LT1683 APPLICATIO S I FOR ATIO Gate Driver Considerations In general, the MOSFETs should be positioned as close to the part as possible to minimize inductance. When the part is active the gate drives will be pulled low to less than 0.2V. When the part is off, the gate drives contain a 40k resistor in series with a diode to ground that will offer passive holdoff protection. If you are using some logic level MOSFETs this might not be sufficient. A resistor may be placed from gate to ground, however the value should be reasonably high to minimize DC losses and possible AC issues. The gate drive source current comes from VIN. The sink current exits through PGND. In general the decoupling cap should be placed close to these two pins. Switching Diodes In general, switching diodes should be Schottky diodes. Size and breakdown voltage depend on the specific converter. A lower forward drop will improve converter efficiency. No other special requirements are needed. PCB Layout Considerations As with any switcher careful consideration should be given to PC board layout. Because this part reduces high frequency EMI the board layout is less critical, however high currents and voltages still produce the need for careful board layout to eliminate poor and erratic performance. Basic Considerations Keep the high current loops physically small in area. The main loops are shown in Figure 8: the power switch loops (A and B) and the rectifier loop (C and D). These loops can be kept small by physically keeping the components close to one another. In addition, connection traces should be kept wide to lower resistance and inductances. Components should be placed to minimize connecting paths. Careful attention to ground connections must also be maintained. Without getting into elaborate detail be careful that currents from different high current loops do not 22 U get coupled into the ground paths of other loops. Using singular points of connection for the grounds is the best way to do this. The two major points of connection are the bottom of the input decoupling cap and the bottom of the output decoupling cap. Typically the sense resistor device PGND and device GND will tie to the bottom of the input cap. There are two other loops to pay attention to. The current slew involves a high bandwidth control that goes through the MOSFET switch, the sense resistor and into the CS pin of the part and out the GATE pin to the MOSFET. Trace inductance and resistance should be kept low on the GATE drive trace. The CS trace should have low inductance. The sense resistor should be physically close to PGND and the MOSFETs’ sources. Finally care should be taken with the CAP A, CAP B pins. The part will tolerate stray capacitance to ground on these pins (