LT1719IS8

LT1719 4.5ns Single/Dual Supply 3V/5V Comparator with Rail-to-Rail Output FEATURES s s s s DESCRIPTIO s s s UltraFast: 4.5ns at 20mV Overdrive 7ns at 5mV Overdrive Low Power: 4.2mA at 3V SOT-23 Package Separate Input and Output Power Supplies (SO-8 Only) Output Optimized for 3V and 5V Supplies TTL/CMOS Compatible Rail-to-Rail Output Low Power Shutdown Mode: 0.1µA APPLICATIO S s s s s s s s High Speed Differential Line Receiver Crystal Oscillator Circuits Level Translators Threshold Detectors/Discriminators Zero-Crossing Detectors High Speed Sampling Circuits Delay Lines The LT ®1719 is an UltraFastTM comparator optimized for low voltage operation. The input voltage range extends from 100mV below VEE to 1.2V below VCC. Internal hysteresis makes the LT1719 easy to use even with slow moving input signals. The rail-to-rail outputs directly interface to TTL and CMOS. Alternatively the symmetric output drive can be harnessed for analog applications or for easy translation to other single supply logic levels. A shutdown control allows for reduced power consumption and extended battery life in portable applications. The LT1719 is available in the SO-8 and 6-lead SOT-23 package. The SO-8 package has separate supplies which allow flexible operation, accomodating separate analog input ranges and output logic levels. For a dual/quad comparator with similar performance, see the LT1720/LT1721. , LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. TYPICAL APPLICATION 2.7V to 6V Crystal Oscillator with TTL/CMOS Output 2.7V TO 6V 2k 1MHz TO 10MHz CRYSTAL (AT-CUT) 8 7 6 GROUND CASE OUTPUT RISING EDGE (tPDLH) 25°C VSTEP = 100mV V+ = 5V CLOAD = 10pF Propagation Delay vs Overdrive 220Ω DELAY (ns) 620Ω 5 4 3 2 FALLING EDGE (tPDHL) + – C1 LT1719 2k 1719 TA01 1 0 0 10 20 30 OVERDRIVE (mV) 40 50 1719 TA02 0.1µF 1.8k U U U 1 LT1719 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW VCC 1 +IN 2 –IN 3 VEE 4 + – Supply Voltage + VS to GND (LT1719S8) ...................................... 7V VCC to VEE (LT1719S8) ....................................... 12V + VS to VEE (LT1719S8) ...................................... 12V VEE to GND (LT1719S8) ...................... – 12V to 0.3V V+ to V– (LT1719S6) ............................................. 7V Input Current (+ IN, – IN or SHDN)..................... ±10mA Output Current (Continuous) ............................ ± 20mA Operating Temperature Range C Grade .................................................. 0°C to 70°C I Grade .............................................. – 40°C to 85°C Junction Temperature .......................................... 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER 8 7 6 5 + VS OUT SHDN GND LT1719CS8 LT1719IS8 S8 PART MARKING 1719 1719I ORDER PART NUMBER S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 110°C/ W TOP VIEW –IN 1 V2 +IN 3 – 6 SHDN 5 OUT 4 V+ LT1719CS6 LT1719IS6 S6 PART MARKING LTHW LTJF S6 PACKAGE 6-LEAD PLASTIC SOT-23 TJMAX = 150°C, θJA = 230°C/ W Consult factory for parts specified with wider operating temperature ranges. The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the LT1719S8 VCC = +VS = 5V and VEE = – 5V, for the LT1719S6 V+ = 5V, V – = 0V, unless otherwise specified. SYMBOL VCC – VEE + VS V+ – V – VCMR VTRIP+ VTRIP– VOS VHYST ∆VOS/∆T IB IOS CMRR PSRR AV VOH PARAMETER Input Supply Voltage Output Supply Voltage Supply Voltage Input Voltage Range Input Trip Points Input Offset Voltage Input Hysteresis Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Voltage Gain Output High Voltage (Note 4) (Note 5) (Note 6) (Note 7) (Note 8) ISOURCE = 4mA, VIN = VTRIP+ + 10mV (LT1719S8) (LT1719S6) q + VS – 0.4 q V+ – 0.4 ELECTRICAL CHARACTERISTICS CONDITIONS (LT1719S8 only) (LT1719S8 only) (LT1719CS6 only) (Note 2) (Note 3) (Note 3) q q q q q q q q MIN 2.7 2.7 2.7 VEE – 0.1 V – – 0.1 – 1.5 – 5.5 TYP MAX 10.5 6 6 VCC – 1.2 V + – 1.2 5.5 1.5 UNITS V V V V V mV mV mV mV mV µV/°C µA µA dB dB dB dB V V (LT1719S8) (LT1719S6) 0.4 q q q q 2.5 3.5 7 0 0.6 (Note 3) 2.0 –6 55 55 65 65 3.5 10 –2.5 0.2 70 65 80 80 (LT1719S8) (LT1719S6) (LT1719S8) (LT1719S6) q q ∞ 2 U W U U WW W LT1719 The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the LT1719S8 VCC = +VS = 5V and VEE = – 5V, for the LT1719S6 V+ = 5V, V – = 0V, unless otherwise specified. SYMBOL PARAMETER VOL tPD20 Output Low Voltage Propagation Delay CONDITIONS ISINK = 10mA, VIN = VTRIP– – 10mV q ELECTRICAL CHARACTERISTICS MIN VEE = 0V(LT1719S8) V – = 0V(LT1719S6) q (LT1719S8 only) TYP 4.5 4.2 7 0.5 2.5 2.2 MAX 0.4 6.5 8.0 10 13 1.5 UNITS V ns ns ns ns ns ns ns ns psRMS psRMS MHz MHz ns ns VOVERDRIVE = 20mV (Note 9) VOVERDRIVE = 20mV, VEE = – 5V tPD5 tSKEW tr tf tJITTER fMAX tOFF tON ICC IEE IS I+ ISHDN5 ISHDN3 ICCS ISS IEES I+S ICCSO ISSO IEEO I+O Propagation Delay Propagation Delay Skew Output Rise Time Output Fall Time Output Timing Jitter Maximum Toggle Frequency Turn-Off Delay Wake-Up Delay Positive Input Stage Supply Current Negative Input Stage Supply Current VOVERDRIVE = 5mV (Notes 9, 10) VEE = 0V(LT1719S8) V – = 0V(LT1719S6) q (Note 11) 10% to 90% 90% to 10% VIN = 1.2VP-P (6dBm), ZIN = 50Ω f = 20MHz VOVERDRIVE = 50mV, +VS or V+ = 3V VOVERDRIVE = 50mV, +VS or V+ = 5V Time to ZOUT ≥ 10kΩ Time to VOH or VOL, ILOAD = 1mA + VS = VCC = 5V, VEE = – 5V + VS = VCC = 5V, VEE = – 5V q q q q q q q q q q q q q q q q q q tPD+ tPD– 15 11 70 62.5 75 350 1.0 0.9 – 4.8 – 3.8 – 2.6 – 2.2 4.2 3.3 4.6 4.2 –300 –200 –110 –80 0.2 7 – 0.2 7 0.1 0.1 0.1 0.2 8 6 9 7 –30 –20 30 50 80 20 20 40 2.2 1.8 mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA µA (LT1719S8 0nly) + VS = VCC = 3V, VEE = 0V (LT1719S8 0nly) + VS = VCC = 3V, VEE = 0V Positive Output Stage Supply Current + VS = VCC = 5V, VEE = – 5V (LT1719S8 0nly) VS = VCC = 3V, VEE = 0V Supply Current Shutdown Pin Current Shutdown Pin Current (LT1719S6) V+ = 5V V+ = 3V +VS o r V + = 5V +VS or V+ = 3V Disabled Supply Currents (LT1719S8) + VS = 6V, VCC = 5V, VEE = – 5V (LT1719S8) VSHDN = +VS – 0.5V (LT1719S8) (LT1719S6) V+ = 6V, V SHDN = +VS – 0.5V – 30 (LT1719S8) + VS = 6V, VCC = 5V, VEE = – 5V (LT1719S8) Shutdown Pin Open (LT1719S8) (LT1719S6) V+ = 6V, Shutdown Pin Open – 20 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: If one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. Note 3: The LT1719 comparator includes internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is defined as the average of VTRIP+ and VTRIP–, while the hysteresis voltage is the difference of these two. Note 4: The LT1719S8 common mode rejection ratio is measured with VCC = 5V, VEE = – 5V and is defined as the change in offset voltage measured from VCM = – 5.1V to VCM = 3.8V, divided by 8.9V. Note 5: The LT1719S6 common mode rejection ratio is measured with V+ = 5V and is defined as the change in offset voltage measured from VCM = – 0.1V to VCM = 3.8V, divided by 3.9V. Note 6: The LT1719S8 power supply rejection ratio is measured with VCM = 1V and is defined as the worst of: the change in offset voltage from VEE = – 5.5V to VEE = 0V divided by 5.5V, or the change in offset voltage from VCC = + VS = 2.7V to VCC = + VS = 6V (with VEE = 0V) divided by 3.3V. Note 7: The 1719S6 power supply rejection ratio is measured with VCM = 1V and is defined as the change in offset voltage measured from V+ = 2.7V to V+ = 6V, divided by 3.3V. 3 LT1719 ELECTRICAL CHARACTERISTICS Note 8: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring VOH and VOL with only 10mV of overdrive. Note 9: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to VTRIP±. Note 10: t PD cannot be measured in automatic handling equipment with low values of overdrive. The LT1719 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that t PD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Note 11: Propagation Delay Skew is defined as: tSKEW = |tPDLH – tPDHL| TYPICAL PERFORMANCE CHARACTERISTICS Input Offset and Trip Voltages vs Supply Voltage 3 VOS AND TRIP POINT VOLTAGE (mV) COMMON MODE INPUT VOLTAGE (V) VOS AND TRIP POINT VOLTAGE (mV) VTRIP 2 1 VOS 0 –1 –2 25°C VCM = 1V VEE OR V – = GND + VTRIP– –3 2.5 5.5 6.0 5.0 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE, VCC = + VS OR V + (V) 1719 G01 Input Current vs Differential Input Voltage 2 1 0 INPUT BIAS (µA) 25°C SUPPLY CURRENT (mA) 6 4 2 0 –2 –4 IEE (LT1719S8) 0 25 50 75 100 125 ICC (LT1719S8) +IS (LT1719S8) SUPPLY CURRENTS (mA) –1 –2 –3 –4 –5 –6 –7 – 5 – 4 – 3 – 2 –1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 4 UW 1719 G04 Input Offset and Trip Voltages vs Temperature 3 2 1 VOS 0 –1 –2 VTRIP+ 4.2 4.0 3.8 0 – 0.2 – 5.0 – 5.2 Input Common Mode Limits vs Temperature +VS = VCC OR V+ = 5V V – = GND (LT1719S6) VTRIP– +VS = VCC or V + = 5V VCM = 1V VEE OR V – = GND VEE = – 5V (LT1719S8) 50 25 75 0 TEMPERATURE (°C) 100 125 –3 – 60 – 40 – 20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1719 G02 – 5.4 – 50 – 25 1719 G03 Quiescent Supply Current vs Temperature 10 VCC = +VS OR V+ = 5V 8 VEE = GND 6 Quiescent Supply Current vs Supply Voltage 5 4 3 2 1 0 –1 –2 –3 0 IEE (LT1719S8) 1 3 4 5 6 2 SUPPLY VOLTAGE, VCC = +VS OR V+ (V) 7 ICC (LT1719S8) IS (LT1719S8) TA = 25°C VEE = GND I+ (LT1719S6) I+ (LT1719S6) –6 –50 –25 TEMPERATURE (°C) 1339 G05 1719 G06 LT1719 TYPICAL PERFORMANCE CHARACTERISTICS Propagation Delay vs Load Capacitance 9 8 PROPAGATION DELAY (ns) 8.0 PROPAGATION DELAY (ns) 7 6 5 4 3 2 1 0 0 7.0 6.5 6.0 5.5 5.0 4.5 4.0 – 50 – 25 0 PROPAGATION DELAY (ns) 25°C VSTEP = 100mV OVERDRIVE = 20mV +VS = VCC OR V+ = 5V VEE OR V – = 0V RISING EDGE (tPDLH) FALLING EDGE (tPDHL) 40 30 OUTPUT LOAD CAPACITANCE (pF) 10 20 Output Low Voltage vs Load Current 0.5 OUTPUT VOLTAGE RELATIVE TO +VS (V) +VS OR V+ = 5V VIN = – 10mV 125°C VCC = 2.7V OUTPUT VOLTAGE (V) 0.4 +VS SUPPLY CURRENT (mA) 0.3 – 55°C 0.2 25°C 0.1 0 4 12 16 8 OUTPUT SINK CURRENT (mA) Shutdown Currents vs Shutdown Voltage 4 IS SUPPLY CURRENTS (mA) SUPPLY I+ CURRENT (mA) 3 LT1719S8 2 1 ICC 0 – 50 TA = 25°C VEE = GND +VS = VCC = 5V SHDN PIN CURRENT (µA) SHDN PIN CURRENT (µA) –100 VS – 4 UW 125°C Propagation Delay vs Temperature 7.5 tPDLH VCM = 1V VSTEP = 100mV CLOAD = 10pF VEE OR V – = GND +VS = VCC = V + 3V 5V OVERDRIVE = 5mV OVERDRIVE = 20mV 3V 5V Propagation Delay vs Supply Voltage 5.5 25°C VSTEP = 100mV OVERDRIVE = 20mV CLOAD = 10pF VEE /V –= GND 5.0 tTPLH tTPHL 4.5 tTPLH 4.0 tTPHL VEE = – 5V (VCC, +VS = 5.5VMAX) (LT1719S8 ONLY) 3.5 2.5 5.5 6.0 5.0 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE, +VS = VCC OR V + (V) 1719 G09 50 1719 G07 75 50 25 TEMPERATURE (°C) 100 125 1719 G08 Output High Voltage vs Load Current 0.0 125°C – 55°C +VS OR V+= 5V VIN = 10mV 9 8 7 Supply Current vs Frequency 25°C + VS = 5V – 0.2 – 0.4 25°C CLOAD = 20pF 6 5 4 NO LOAD 3 2 CLOAD = 10pF – 0.6 – 0.8 25°C VCC = 2.7V 0 4 12 16 8 OUTPUT SOURCE CURRENT (mA) 20 1719 G11 –1.0 20 1719 G10 0 10 20 FREQUENCY (MHz) 30 40 1719 G12 Shutdown Currents vs Shutdown Voltage 5 4 LT1719S6 3 2 1 0 – 50 TA = 25°C V+ = 5V V+ – 3 V+ – 2 V+ – 1 SHDN PIN VOLTAGE (V) V+ 1719 G13b VS – 3 VS – 2 VS – 1 SHDN PIN VOLTAGE (V) VS 1719 G13a –100 V+ – 4 5 LT1719 TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Currents vs Temperature 700 10 SHUTDOWN = +VS – 0.5V SHUTDOWN CURRENTS (µA) WAKE-UP DELAY (ns) 1 +IS SHUTDOWN PIN OPEN 0.1 –50 –25 0 PIN FUNCTIONS LT1719S8 VCC (Pin 1): Positive Supply Voltage for Input Stage. + IN (Pin 2): Noninverting Input of Comparator. – IN (Pin 3): Inverting Input of Comparator. VEE (Pin 4): Negative Supply Voltage for Input Stage and Chip Substrate. GND (Pin 5): Ground. SHDN (Pin 6): Shutdown. Pull to ground to enable comparator. OUT (Pin 7): Output of Comparator. + VS (Pin 8): Positive Supply Voltage for Output Stage. 6 UW Wake-Up Delay vs Temperature +IS SHUTDOWN PIN CURRENT 600 500 400 300 200 VCC = + VS = 5V VEE = – 5V 25 50 75 100 125 150 TEMPERATURE (°C) 1719 G14 100 – 50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1719 G15 U U U LT1719S6 – IN (Pin 1): Inverting Input of Comparator. V – (Pin 2): Negative Supply, usually Grounded. + IN (Pin3): Noninverting Input of Comparator. V+ (Pin 4): Positive Supply Voltage. OUT (Pin 5): Output of Comparator. SHDN (Pin 6): Shutdown. Pull to ground to enable comparator. LT1719 TEST CIRCUITS Response Time Test Circuit +Vs – VCM (V + – VCM) VCC – VCM –100mV 25Ω 1 2 0V 0.01µF + – 4 8 7 6(6) 0.01µF 10 × SCOPE PROBE (CIN ≈ 10pF) 25Ω 0.1µF 0V –3V 50Ω 400Ω 750Ω PULSE IN 130Ω 2N3866 1N5711 50k 50Ω 3 DUT LT1719S8 5 V1* VEE – VCM – VCM *V1 = –1000 • (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1719 INPUTS –5V 1719 TC02 ±VTRIP Test Circuit BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM ± 7.5V 14 VCC 50k 0.1µF LTC203 15 3 2 1000 × VTRIP+ 10nF 1µF 1 8 – 1/2 LT1112 + 10k + 50Ω 50Ω DUT LT1719 16 9 200k – 1000 × VHYST VCM 11 10 6 7 1000 × VOS 10k LTC203 3 1/2 LT1638 100k 100k 1 2.4k 8 9 1/2 LT1112 0.15µF 6 NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ± 15V. 200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED 7 11 10 1719 TC01 2 14 15 1000 × VTRIP– 1µF 16 100k 100k 1/2 LT1638 – + – + – + 10nF 7 LT1719 APPLICATIONS INFORMATION Power Supply Configurations (SO-8 Package) The LT1719S8 has separate supply pins for the input and output stages that allow flexible operation, accommodating separate voltage ranges for the analog input and the output logic. Of course, a single 3V/5V supply may be used by tying + VS and VCC together as well as GND and VEE. The minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.7V and the VEE pin must be equal to or less than ground. The following rules must be adhered to in any configuration: 2.7V ≤ (VCC – VEE) ≤ 10.5V 2.7V ≤ (+ VS – GND) ≤ 6V (+ VS – VEE) ≤ 10.5V VEE ≤ Ground Although the ground pin need not be tied to system ground, most applications will use it that way. Figure 1 shows three common configurations. The final one is uncommon, but it will work and may be useful as a level translator; the input stage is run from – 5.2V and ground while the output stage is run from 3V and ground. In this case the common mode input voltage range does not include ground, so it may be helpful to tie VCC to 3V anyway. Conversely, VCC may also be tied below ground, as long as the above rules are not violated. Input Voltage Considerations The LT1719 is specified for a common mode range of –100mV to 3.8V when used with a single 5V supply. A more general consideration is that the common mode range is 100mV below VEE /V – to 1.2V below VCC/V +. The criterion for this common mode limit is that the output still responds correctly to a small differential input signal. If one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits, and the output will retain the correct polarity. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode + LT1719S8 2.7V TO 6V 5V VCC + VS GND VEE VCC 3V + VS GND VEE – 5V 8 U W U U + LT1719S8 – – Single Supply 10V VCC 5V + VS GND VEE ± 5VIN, 3VOUT VCC 3V + VS GND VEE – 5.2V 1719 F01 + LT1719S8 + LT1719S8 – – 10VIN, 5VOUT Front End Entirely Negative Figure 1. Variety of SO-8 Power Supply Configurations between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least – 400mV common mode. However, the offset and hysteresis in this mode will increase dramatically, to as much as 15mV each. The input bias currents will also increase. When both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. However, the internal hysteresis will hold the output to a valid logic level. When at least one of the inputs returns to within the common mode limits, recovery from this state can take as long as 1µs. The propagation delay does not increase significantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an RC delay caused by the 2pF typical input capacitance. Input Protection The input stage is protected against damage from large differential signals, up to and beyond a differential voltage LT1719 APPLICATIONS INFORMATION equal to the supply voltage, limited only by the absolute maximum currents noted. External input protection circuitry is only needed if currents would otherwise exceed these absolute maximums. The internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltage is at the absolute maximum rating. The LT1719 input stage has general purpose internal ESD protection for the human body model. For use as a line receiver, additional external protection may be required. As with most integrated circuits, the level of immunity to ESD is much greater when residing on a printed circuit board where the power supply decoupling capacitance will limit the voltage rise caused by an ESD pulse. Input Bias Current Input bias current is measured with both inputs held at 1V. As with any PNP differential input stage, the LT1719 bias current flows out of the device. It will go to zero on the higher of the two inputs and double on the lower of the two inputs. With more than two diode drops of differential input voltage, the LT1719’s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4µA or less. See the Typical Performance curve “Input Current vs Differential Input Voltage.” High Speed Design Considerations Application of high speed comparators is often plagued by oscillations. The LT1719 has 4mV of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. However, with the 2V/ns slew rate of the LT1719 outputs, a 4mV step can be created at a 100Ω input source with only 0.02pF of output to input coupling. The LT1719’s pinout has been arranged to minimize problems by placing the sensitive inputs away from the outputs, shielded by the power rails. The input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the output and the inputs. For multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and the output. Figure 2 shows a typical topside layout of the LT1719S8 on such a multilayer board. Shown is the topside metal etch including traces, pin escape vias, and the land pads for an SO-8 LT1719 and its adjacent X7R 10nF bypass capacitors in the 1206 case. The same principles should be used with the SOT 23-6. U W U U 1719 F02 Figure 2. Typical Topside Metal for Multilayer PCB Layouts The ground trace from Pin 5 runs under the device up to the bypass capacitor, shielding the inputs from the outputs. Note the use of a common via for the LT1719 and the bypass capacitors, which minimizes interference from high frequency energy running around the ground plane or power distribution traces. The supply bypass should include an adjacent 10nF ceramic capacitor and a 2.2µF tantalum capacitor no farther than 5cm away; use more capacitance on + VS if driving more than 4mA loads. To prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1kΩ or less. The outputs of the LT1719 are capable of very high slew rates. To prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to maintain signal integrity. The LT1719 can drive DC terminations of 200Ω or more, but lower characteristic impedance traces can be used with series termination or AC termination topologies. Shutdown Control The LT1719 features a shutdown control pin for reduced quiescent current when the comparator is not needed. During shutdown, the inputs and the outputs become high impedances. The LT1719 is enabled when the shutdown input is pulled low with a threshold roughly two diode drops below + VS or V+. Therefore, if driven by a standard TTL gate, a pull-up resistor should be used. Because 9 LT1719 APPLICATIONS INFORMATION shutdown is active high, this resistor adds little power drain during shutdown. A logic high disables the comparator. The LT1719S8 logic interface is based on the output power rails, + VS and GND. For applications that do not use the shutdown feature, it may be helpful to tie the shutdown control to ground through a 100Ω resistor rather than directly. This allows the SHDN pin to be pulled high during debug or in-circuit test (bed of nails) so that the output node can be wiggled without damaging the low impedance output driver of the LT1719. The shutdown state is not guaranteed to be useful as a multiplexer. Digital signals can have extremely fast edge rates that may be enough to momentarily activate the LT1719 output stage via internal capacitive coupling. No damage to the LT1719 will result, but this could prove deleterious to the intended recipient of the signal. The LT1719 includes a FET pull-up on the shutdown control pin (see Simplified Schematic) as well as other internal structures to make the shutdown state current drain