LT1739CFE

LT1739 Dual 500mA, 200MHz xDSL Line Driver Amplifier FEATURES s s DESCRIPTIO s s s s s s s s s 3mm × 4mm High Power DFN Package Exceeds All Requirements For Full Rate, Downstream ADSL Line Drivers ± 500mA Minimum IOUT ± 11.1V Output Swing, VS = ± 12V, RL = 100Ω ±10.9V Output Swing, VS = ± 12V, IL = 250mA Low Distortion: – 82dBc at 1MHz, 2VP-P Into 50Ω Power Saving Adjustable Supply Current Power Enhanced TSSOP-20 Small Footprint Package 200MHz Gain Bandwidth 600V/µs Slew Rate Specified at ±12V and ± 5V The LT®1739 is a 500mA minimum output current, dual op amp with outstanding distortion performance. The amplifiers are gain-of-ten stable, but can be easily compensated for lower gains. The extended output swing allows for lower supply rails to reduce system power. Supply current is set with an external resistor to optimize power dissipation. The LT1739 features balanced, high impedance inputs with low input bias current and input offset voltage. Active termination is easily implemented for further system power reduction. Short-circuit protection and thermal shutdown insure the device’s ruggedness. The outputs drive a 100Ω load to ±11.1V with ±12V supplies, and ±10.9V with a 250mA load. The LT1739 is a pin-for-pin replacement for the LT1794 in xDSL line driver applications and requires no circuit changes. The LT1739 is available in the very small, thermally enhanced, 3mm × 4mm DFN package or a 20-lead TSSOP for maximum port density in central office line driver applications. For a dual version of the LT1739, see the LT6301 data sheet. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s High Density ADSL Central Office Line Drivers High Efficiency ADSL, HDSL2, G.lite, SHDSL Line Drivers Buffers Test Equipment Amplifiers Cable Drivers TYPICAL APPLICATIO 12V RBIAS 24.9k SHDN High Efficiency ±12V Supply ADSL Central Office Line Driver 3mm × 4mm DFN Package Bottom View 12.7Ω EXPOSED THERMAL PAD +IN + 1/2 LT1739 – 1k 110Ω 1000pF 110Ω 1:2* 0.8 mm • • 100Ω 1k 1739 TA01 173 9T A0 2 – 1/2 LT1739 –IN 12.7Ω SHDNREF *COILCRAFT X8390-A OR EQUIVALENT ISUPPLY = 10mA PER AMPLIFIER WITH RBIAS = 24.9k + –12V U 3m m m 4m 1739fas, sn1739 U U 1 LT1739 ABSOLUTE MAXIMUM RATINGS Supply Voltage (V + to V –) ................................. ±13.5V Input Current ..................................................... ± 10mA Output Short-Circuit Duration (Note 2) ........... Indefinite Operating Temperature Range ............... – 40°C to 85°C Specified Temperature Range (Note 3) .. – 40°C to 85°C PACKAGE/ORDER INFORMATION TOP VIEW V– 1 20 V– ORDER PART NUMBER TOP VIEW NC 2 –IN 3 +IN 4 SHDN 5 SHDNREF 6 +IN 7 –IN 8 NC 9 V – 10 19 NC 18 OUT 17 V + 16 NC 15 NC 14 V+ LT1739CFE LT1739IFE 13 OUT 12 NC 11 V – FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4) UNDERSIDE METAL CONNECTED TO V – Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VOS PARAMETER Input Offset Voltage The q denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCM = 0V, pulse tested, ± 5V ≤ VS ≤ ± 12V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3) CONDITIONS q Input Offset Voltage Matching q Input Offset Voltage Drift IOS IB Input Offset Current Input Bias Current q Input Bias Current Matching q en in Input Noise Voltage Density Input Noise Current Density f = 10kHz f = 10kHz 2 U U W WW U W (Note 1) Junction Temperature FE Package ....................................................... 150°C UE Package ...................................................... 125°C Storage Temperature Range FE Package ....................................... – 65°C to 150°C UE Package ...................................... – 65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER –IN A +IN A SHDN SHDNREF +IN B –IN B 1 2 3 4 5 6 12 V – 11 OUT A 10 V + 9 8 7 V+ OUT B V– LT1739CUE LT1739IUE UE PART MARKING 1739 1739I UE12 PACKAGE 12-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 60°C/W, θJC = 3°C/W (Note 4) UNDERSIDE METAL CONNECTED TO V – MIN TYP 1 0.3 MAX 5.0 7.5 5.0 7.5 500 800 ±4 ±6 500 800 UNITS mV mV mV mV µV/°C nA nA µA µA nA nA nV/√Hz pA/√Hz 1739fas, sn1739 q q 10 100 ± 0.1 100 8 0.8 LT1739 ELECTRICAL CHARACTERISTICS SYMBOL RIN CIN PARAMETER Input Resistance Input Capacitance Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR PSRR AVOL Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain (Note 8) (Note 5) (Note 5) VCM = (V + – 2V) to (V – + 2V) q q q The q denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCM = 0V, pulse tested, ± 5V ≤ VS ≤ ± 12V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3) CONDITIONS VCM = 2V) to Differential (V + – (V –+ 2V) q MIN 5 TYP 50 6.5 3 V+ – 1 V– + 1 83 88 76 70 11.1 10.9 4.0 3.9 1200 10 8 6 4 MAX UNITS MΩ MΩ pF V V dB dB dB dB dB dB dB dB ±V ±V ±V ±V ±V ±V ±V ±V mA V+ – 2 74 66 74 66 63 57 60 54 10.9 10.7 10.6 10.4 3.7 3.5 3.6 3.4 500 8.0 6.7 V– + 2 VS = ± 4V to ±12V q VS = ±12V, VOUT = ±10V, RL = 40Ω q VS = ± 5V, VOUT = ±3V, RL = 25Ω q VOUT Output Swing (Note 8) VS = ± 12V, RL = 100Ω q VS = ± 12V, IL = 250mA q VS = ±5V, RL = 25Ω q VS = ± 5V, IL = 250mA q IOUT IS Maximum Output Current (Note 8) Supply Current per Amplifier VS = ± 12V, RL = 1Ω VS = ± 12V, RBIAS = 24.9k (Note 6) VS = ± 12V, RBIAS = 32.4k (Note 6) VS = ± 12V, RBIAS = 43.2k (Note 6) VS = ± 12V, RBIAS = 66.5k (Note 6) VS = ± 5V, RBIAS = 24.9k (Note 6) q q 13.5 15.0 mA mA mA mA mA mA mA mA mA dB dB V/µs V/µs dBc dBc MHz 2.2 1.8 3.4 0.1 0.3 5.0 5.8 1 1 Supply Current in Shutdown Output Leakage in Shutdown Channel Separation (Note 8) SR HD2 HD3 GBW Slew Rate Differential 2nd Harmonic Distortion Differential 3rd Harmonic Distortion Gain Bandwidth VSHDN = 0.4V VSHDN = 0.4V VS = ±12V, VOUT = ±10V, RL = 40Ω q 80 77 300 100 110 600 200 – 85 – 82 200 VS = ± 12V, AV = – 10, (Note 7) VS = ± 5V, AV = – 10, (Note 7) VS = ± 12V, AV = 10, 2VP-P, RL = 50Ω, 1MHz VS = ± 12V, AV = 10, 2VP-P, RL = 50Ω, 1MHz f = 1MHz Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Applies to short circuits to ground only. A short circuit between the output and either supply may permanently damage the part when operated on supplies greater than ± 10V. Note 3: The LT1739C is guaranteed to meet specified performance from 0°C to 85°C and is designed, characterized and expected to meet these extended temperature limits, but is not tested at – 40°C. The LT1739I is guaranteed to meet the extended temperature limits. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to the device and rate of air flow over the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. Note 5: Guaranteed by the CMRR tests. Note 6: RBIAS is connected between V + and the SHDN pin, with the SHDNREF pin grounded. Note 7: Slew rate is measured at ± 5V on a ±10V output signal while operating on ±12V supplies and ±1V on a ± 3V output signal while operating on ± 5V supplies. Note 8: This parameter of the LT1739CUE/LT1739IUE is 100% tested at room temperature, but is not tested at –40°C, 0°C or 85°C. 1739fas, sn1739 3 LT1739 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Ambient Temperature VS = ±12V 14 RBIAS = 24.9k TO SHDN VSHDNREF = 0V 13 12 11 10 9 8 7 6 5 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 15 V+ –0.5 COMMON MODE RANGE (V) –1.0 –1.5 ± IBIAS (nA) –2.0 ISUPPLY PER AMPLIFIER (mA) Input Noise Spectral Density 100 TA = 25°C VS = ± 12V IS PER AMPLIFIER = 10mA en 100 OUTPUT SATURATION VOLTAGE (V) INPUT VOLTAGE NOISE (V/√Hz) 10 ISC (mA) 1 in 0.1 1 10 100 1k FREQUENCY (Hz) 10k Open-Loop Gain and Phase vs Frequency 120 100 80 60 GAIN (dB) 40 20 0 GAIN TA = 25°C VS = ±12V AV = – 10 RL = 100Ω IS PER AMPLIFIER = 10mA 1M 10M FREQUENCY (Hz) 100M 1739 G07 PHASE –3dB BANDWIDTH (MHz) 30 25 20 15 10 5 0 2 4 6 8 10 12 14 SUPPLY CURRENT PER AMPLIFIER (mA) 1739 G08 –40 –80 –120 –160 –200 –240 –280 SLEW RATE (V/µs) –20 –40 –60 –80 100k 4 UW 1739 G01 1739 G04 Input Common Mode Range vs Supply Voltage TA = 25°C ∆VOS > 1mV 200 Input Bias Current vs Ambient Temperature VS = ± 12V 180 IS PER AMPLIFIER = 10mA 160 140 120 100 80 60 40 20 2.0 1.5 1.0 0.5 V– 2 4 8 10 6 SUPPLY VOLTAGE (± V) 12 14 1739 G02 0 –50 –30 10 30 50 –10 TEMPERATURE (°C) 70 90 1739 G03 Output Short-Circuit Current vs Ambient Temperature 800 780 VS = ± 12V IS PER AMPLIFIER = 10mA V+ –0.5 –1.0 –1.5 Output Saturation Voltage vs Ambient Temperature VS = ± 12V RL = 100Ω ILOAD = 250mA INPUT CURRENT NOISE (pA/√Hz) PHASE (DEG) 760 740 720 700 680 660 640 620 SOURCING SINKING 10 1 1.5 1.0 0.5 V– – 50 –30 –10 ILOAD = 250mA RL = 100Ω 0.1 100k 600 –50 –30 30 –10 10 50 TEMPERATURE (°C) 70 90 50 30 10 TEMPERATURE (°C) 70 90 1739 G06 1739 G05 –3dB Bandwidth vs Supply Current 120 80 40 0 Slew Rate vs Supply Current 1000 900 800 700 600 500 400 300 200 100 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SUPPLY CURRENT PER AMPLIFIER (mA) 1739 G09 45 40 35 TA = 25°C VS = ±12V AV = 10 RL = 100Ω TA = 25°C VS = ±12V AV = – 10 RL = 1k RISING FALLING 1739fas, sn1739 LT1739 TYPICAL PERFOR A CE CHARACTERISTICS CMRR vs Frequency 100 COMMON MODE REJECTION RATIO (dB) 90 80 70 60 50 40 30 20 10 0 0.1 POWER SUPPLY REJECTION (dB) TA = 25°C VS = ±12V IS = 10mA PER AMPLIFIER GAIN (dB) 1 10 FREQUENCY (MHz) Output Impedance vs Frequency 1000 TA = 25°C VS ± 12V IS PER AMPLIFIER = 2mA 10 IS PER AMPLIFIER = 10mA IS PER AMPLIFIER = 15mA ISHDN (mA) 2.5 SUPPLY CURRENT PER AMPLIFIER (mA) 100 OUTPUT IMPEDANCE (Ω) 1 0.1 0.01 0.01 0.1 1 10 FREQUENCY (MHz) Differential Harmonic Distortion vs Output Amplitude f = 1MHz TA = 25°C –50 VS = ±12V AV = 10 RL = 50Ω –60 I PER AMPLIFIER = 10mA S HD3 –70 –80 HD2 –90 –100 0 2 4 6 8 10 12 VOUT(P-P) 14 16 18 –40 DISTORTION (dBc) DISTORTION (dBc) UW 1739 G10 PSRR vs Frequency 100 90 80 70 60 50 40 30 20 10 0 100 Frequency Response vs Supply Current 30 25 20 15 10 5 0 –5 –10 –15 –20 2mA PER AMPLIFIER 10mA PER AMPLIFIER 15mA PER AMPLIFIER VS = ±12V AV = 10 VS = ±12V AV = 10 IS = 10mA PER AMPLIFIER (–) SUPPLY (+) SUPPLY –10 0.01 0.1 1 10 FREQUENCY (MHz) 100 1739 G11 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1739 G12 ISHDN vs VSHDN TA = 25°C VS = ± 12V VSHDNREF = 0V 35 30 25 20 15 10 5 0 Supply Current vs VSHDN TA = 25°C VS = ± 12V VSHDNREF = 0V 2.0 1.5 1.0 0.5 100 1739 G13 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V) 1739 G14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V) 1739 G14 Differential Harmonic Distortion vs Frequency –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 HD2 HD3 VO = 10VP-P TA = 25°C VS = ±12V AV = 10 RL = 50Ω IS PER AMPLIFIER = 10mA –90 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1739 G17 1739 G16 1739fas, sn1739 5 LT1739 TYPICAL PERFOR A CE CHARACTERISTICS Differential Harmonic Distortion vs Supply Current –40 –45 –50 DISTORTION (dBc) –55 f = 1MHz, HD3 –60 –65 –70 –75 –80 –85 2 3 4 5 f = 1MHz, HD2 6 7 8 9 10 ISUPPLY PER AMPLIFIER (mA) 11 f = 100kHz, HD2 f = 100kHz, HD3 OUTPUT VOLTAGE (VP-P) TEST CIRCUIT SUPPLY BYPASSING 12V V+ +IN A RBIAS SHDN A –IN A 10k –12V OUT (+) EIN 49.9Ω MINICIRCUITS ZSC5-2-2 SPLITTER OUT (–) 110Ω 10k –IN B +IN B 110Ω 0.01µF 1k 12.7Ω B OUT B SHDNREF V– –12V *COILCRAFT X8390-A OR EQUIVALENT VOUTP-P AMPLITUDE SET AT EACH AMPLIFIER OUTPUT DISTORTION MEASURED ACROSS LINE LOAD 1739 TC 6 UW Undistorted Output Swing vs Frequency 20 VO = 10VP-P VS = ± 12V AV = 10 RL = 50Ω 15 10 SFDR > 40dB TA = 25°C VS = ± 12V AV = 10 RL = 50Ω IS PER AMPLIFIER = 10mA 300k 1M 3M FREQUENCY (Hz) 10M 1739 G19 5 0 100k 1739 G18 0.1µF 0.1µF VOUT(P-P) OUT A 12.7Ω + + 12V 4.7µF 4.7µF –12V + 4.7µF 0.1µF + – 1k RL ≈ 50Ω 1:2* 100 LINE LOAD – + 1739fas, sn1739 LT1739 APPLICATIO S I FOR ATIO The LT1739 is a high speed, 200MHz gain bandwidth product, dual voltage feedback amplifier with high output current drive capability, 500mA source and sink. The LT1739 is ideal for use as a line driver in xDSL data communication applications. The output voltage swing has been optimized to provide sufficient headroom when operating from ± 12V power supplies in full-rate ADSL applications. The LT1739 also allows for an adjustment of the operating current to minimize power consumption. In addition, the LT1739 is available in small footprint 3mm × 4mm DFN and 20-lead TSSOP surface mount package to minimize PCB area in multiport central office DSL cards. To minimize signal distortion, the LT1739 amplifiers are decompensated to provide very high open-loop gain at high frequency. As a result each amplifier is frequency stable with a closed-loop gain of 10 or more. If a closedloop gain of less than 10 is desired, external frequency compensating components can be used. Setting the Quiescent Operating Current Power consumption and dissipation are critical concerns in multiport xDSL applications. Two pins, Shutdown (SHDN) and Shutdown Reference (SHDNREF), are provided to control quiescent power consumption and allow for the complete shutdown of the driver. The quiescent current should be set high enough to prevent distortion induced errors in a particular application, but not so high that power is wasted in the driver unnecessarily. A good starting point to evaluate the LT1739 is to set the quiescent current to 10mA per amplifier. The internal biasing circuitry is shown in Figure 1. Grounding the SHDNREF pin and directly driving the SHDN pin with a voltage can control the operating current as seen in the Typical Performance Characteristics. When the SHDN pin is less than SHDNREF + 0.4V, the driver is shut down and consumes typically only 100µA of supply current and the outputs are in a high impedance state. Part to part variations, however, will cause inconsistent control of the quiescent current if direct voltage drive of the SHDN pin is used. Using a single external resistor, RBIAS, connected in one of two ways provides a much more predictable control of the quiescent supply current. Figure 2 illustrates the effect ISUPPLY PER AMPLIFIER (mA) ISUPPLY PER AMPLIFIER (mA) U on supply current per amplifier with RBIAS connected between the SHDN pin and the 12V V + supply of the LT1739 and the approximate design equations. Figure 3 illustrates the same control with RBIAS connected between the SHDNREF pin and ground while the SHDN pin is tied to V +. Either approach is equally effective. SHDN 5I I 2k 2I 2I 1k TO START-UP CIRCUITRY SHDNREF IBIAS TO AMPLIFIERS BIAS CIRCUITRY 1739 F01 W UU IBIAS = 2 ISHDN = ISHDNREF 5 ISUPPLY PER AMPLIFIER (mA) = 64 • IBIAS Figure 1. Internal Current Biasing Circuitry 30 25 20 15 RBIAS = VS = ± 12V V + = 12V RBIAS SHDN IS PER AMPLIFIER (mA) ≈ V + – 1.2V • 25.6 RBIAS + 2k 10 SHDNREF V + – 1.2V • 25.6 – 2k IS PER AMPLIFIER (mA) 5 0 7 10 40 70 100 RBIAS (kΩ) 130 160 190 1739 F02 Figure 2. RBIAS to V+ Current Control 45 40 35 30 25 20 15 10 5 0 4 7 10 30 50 70 90 100 130 150 170 190 210 230 250 270 290 RBIAS (kΩ) 1739 F03 VS = ± 12V V + = 12V SHDN V + – 1.2V • 64 IS PER AMPLIFIER (mA) ≈ RBIAS + 5k V + – 1.2V • 64 – 5k IS PER AMPLIFIER (mA) RBIAS = SHDNREF RBIAS Figure 3. RBIAS to Ground Current Control 1739fas, sn1739 7 LT1739 APPLICATIO S I FOR ATIO Logic Controlled Operating Current The DSP controller in a typical xDSL application can have I/O pins assigned to provide logic control of the LT1739 line driver operating current. As shown in Figure 4 one or two logic control inputs can set two or four different operating modes. The logic inputs add or subtract current to the SHDN input to set the operating current. The one logic input example selects the supply current to be either full power, 10mA per amplifier or just 2mA per amplifier, which significantly reduces the driver power consumption while maintaining less than 2Ω output impedance to frequencies less than 1MHz. This low power mode retains termination impedance at the amplifier outputs and the line driving back termination resistors. With this termination, while a DSL port is not transmitting data, it can still sense a received signal from the line across the backtermination resistors and respond accordingly. The two logic input control provides two intermediate (approximately 7mA per amplifier and 5mA per amplifier) operating levels between full power and termination modes. For proper operation of the current control circuitry, it is necessary that the SHDNREF pin be biased at least 2V more positive than V –. In single supply applications where V – is at ground potential, special attention to the DC bias of the SHDNREF pin is required. Contact Two Control Inputs RESISTOR VALUES (kΩ) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 11.5 13.0 21.5 8.66 10.7 20.5 RC1 19.1 22.1 36.5 14.3 17.8 34.0 RCO VC0 SUPPLY CURRENT PER AMPLIFIER (mA) H 10 10 10 10 10 10 L 7 7 7 7 7 7 H 5 5 5 5 5 5 L 2 2 2 2 2 2 VLOGIC VC1 0V VC0 RC1 RC0 12V OR VLOGIC RSHDN SHDN 2k VC1 H H L L One Control Input RESISTOR VALUES (kΩ) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 RC 7.32 8.25 13.7 5.49 6.65 12.7 VC H L SUPPLY CURRENT PER AMPLIFIER (mA) 10 10 10 10 10 10 2 2 2 2 2 2 1739 F04 12V OR VLOGIC VLOGIC 0V VC RSHDN SHDN 2k RC Figure 4. Providing Logic Input Control of Operating Current 8 U Linear Technology for assistance in implementing a single supply design with operating current control. These modes can be useful for overall system power management when full power transmissions are not necessary. Shutdown and Recovery The ultimate power saving action on a completely idle port is to fully shut down the line driver by pulling the SHDN pin to within 0.4V of the SHDNREF potential. As shown in Figure 5 complete shutdown occurs in less than 10µs and, more importantly, complete recovery from the shut down state to full operation occurs in less than 2µs. The biasing circuitry in the LT1739 reacts very quickly to bring the amplifiers back to normal operation. VSHDN SHDNREF = 0V AMPLIFIER OUTPUT 1794 F05 W UU Figure 5. Shutdown and Recovery Timing Power Dissipation and Heat Management xDSL applications require the line driver to dissipate a significant amount of power and heat compared to other components in the system. The large peak to RMS variations of DMT and CAP ADSL signals require high supply voltages to prevent clipping, and the use of a step-up transformer to couple the signal to the telephone line can require high peak current levels. These requirements result in the driver package having to dissipate significant amounts of power. Several multiport cards inserted into a rack in an enclosed central office box can add up to many, many watts of power dissipation in an elevated ambient temperature environment. The LT1739 has builtin thermal shutdown circuitry that will protect the amplifiers if operated at excessive temperatures, however data transmissions will be seriously impaired. It is important in 1739fas, sn1739 SHDNREF SHDNREF LT1739 APPLICATIO S I FOR ATIO the design of the PCB and card enclosure to take measures to spread the heat developed in the driver away to the ambient environment to prevent thermal shutdown (which occurs when the junction temperature of the LT1739 exceeds 165°C). Estimating Line Driver Power Dissipation Figure 6 is a typical ADSL application shown for the purpose of estimating the power dissipation in the line driver. Due to the complex nature of the DMT signal, which looks very much like noise, it is easiest to use the RMS values of voltages and currents for estimating the driver power dissipation. The voltage and current levels shown for this example are for a full-rate ADSL signal driving 20dBm or 100mWRMS of power on to the 100Ω telephone line and assuming a 0.5dBm insertion loss in the transformer. The quiescent current for the LT1739 is set to 10mA per amplifier. The power dissipated in the LT1739 is a combination of the quiescent power and the output stage power when driving a signal. The two amplifiers are configured to place a differential signal on to the line. The Class AB output stage in each amplifier will simultaneously dissipate power in 12V 20mA DC 24.9k – SETS IQ PER AMPLIFIER = 10mA +IN + A 2VRMS SHDN 17.4Ω – 1k 110Ω 1000pF ILOAD = 57mARMS 110Ω 1k 1:1.7 • • – B –IN + –12V SHDNREF –2VRMS Figure 6. Estimating Line Driver Power Dissipation 1739fas, sn1739 U the upper power transistor of one amplifier, while sourcing current, and the lower power transistor of the other amplifier, while sinking current. The total device power dissipation is then: PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER) PD = (V+ – V–) • IQ + (V+ – VOUTARMS) • ILOAD + (V – – VOUTBRMS) • ILOAD With no signal being placed on the line and the amplifier biased for 10mA per amplifier supply current, the quiescent driver power dissipation is: PDQ = 24V • 20mA = 480mW This can be reduced in many applications by operating with a lower quiescent current value. When driving a load, a large percentage of the amplifier quiescent current is diverted to the output stage and becomes part of the load current. Figure 7 illustrates the total amount of biasing current flowing between the + and – power supplies through the amplifiers as a function of load current. As much as 60% of the quiescent no load operating current is diverted to the load. 100Ω 3.16VRMS 17.4Ω 1739 F06 W UU 9 LT1739 APPLICATIO S I FOR ATIO 25 20 TOTAL IQ (mA) 15 10 5 0 –240 –200 –160 –120 –80 –40 0 40 ILOAD (mA) 80 120 160 Figure 7. IQ vs ILOAD At full power to the line the driver power dissipation is: PD(FULL) = 24V • 8mA + (12V – 2VRMS) • 57mARMS + [|–12V – (– 2VRMS)|] • 57mARMS PD(FULL) = 192mW + 570mW + 570mW = 1.332W* The junction temperature of the driver must be kept less than the thermal shutdown temperature when processing a signal. The junction temperature is determined from the following expression: TJ = TAMBIENT (°C) + PD(FULL) (W) • θJA (°C/W) θJA is the thermal resistance from the junction of the LT1739 to the ambient air, which can be minimized by heat-spreading PCB metal and airflow through the enclosure as required. For the example given, assuming a maximum ambient temperature of 85°C and keeping the junction temperature of the LT1739 to 140°C maximum, the maximum thermal resistance from junction to ambient required is: θJA(MAX) = 140°C – 85°C = 41.3°C / W 1.332W Heat Sinking Using PCB Metal Designing a thermal management system is often a trial and error process as it is never certain how effective it is until it is manufactured and evaluated. As a general rule, the more copper area of a PCB used for spreading heat away from the driver package, the more the operating junction temperature of the driver will be reduced. The limit to this approach however is the need for very 10 U compact circuit layout to allow more ports to be implemented on any given size PCB. Fortunately xDSL circuit boards use multiple layers of metal for interconnection of components. Areas of metal beneath the LT1739 connected together through several small 13 mil vias can be effective in conducting heat away from the driver package. The use of inner layer metal can free up top and bottom layer PCB area for external component placement. Figure 8 shows examples of PCB metal being used for heat spreading. These are provided as a reference for what might be expected when using different combinations of metal area on different layers of a PCB. These examples are with a 4-layer board using 1oz copper on each. The most effective layers for spreading heat are those closest to the LT1739 junction. The small TSSOP and DFN packages are very effective for compact line driver designs. Both packages also have an exposed metal heat sinking pad on the bottom side which, when soldered to the PCB top layer metal, directly conducts heat away from the IC junction. Soldering the thermal pad to the board produces a thermal resistance from junction to case, θJC, of approximately 3°C/W. As a minimum, the area directly beneath the package on all PCB layers can be used for heat spreading. Limiting the area of metal to just that of the exposed metal heat sinking pad however is not very effective, particularly if the amplifiers are required to dissipate significant power levels. This is shown in Figure 8 for both the TSSOP and DFN packages. Expanding the area of metal on various layers significantly reduces the overall thermal resistance. If possible, an entire unbroken plane of metal close to the heat sinking pad is best for multiple drivers on one PCB card. The addition of vias (small 13mil or smaller holes which fill during PCB plating) connecting all layers of heat spreading metal also helps to reduce operating temperatures of the driver. These too are shown in Figure 8. Important Note: The metal planes used for heat sinking the LT1739 are electrically connected to the negative supply potential of the driver, typically – 12V. These planes must be isolated from any other power planes used in the board design. *Note: Design techniques exist to significantly reduce this value. (See Line Driving Back Termination) 1739fas, sn1739 200 240 1739 F07 W UU LT1739 APPLICATIO S I FOR ATIO When PCB cards containing multiple ports are inserted into a rack in an enclosed cabinet, it is often necessary to provide airflow through the cabinet and over the cards. As STILL AIR θJA TSSOP 100°C/W PACKAGE TOP LAYER TSSOP 50°C/W TSSOP 45°C/W DFN 130°C/W DFN 75°C/W Typical Reduction in θJA with Laminar Airflow Over the Device 0 –10 REDUCTION IN θJA (%) –20 –30 –40 –50 –60 0 100 200 300 400 500 600 700 800 900 1000 AIRFLOW (LINEAR FEET PER MINUTE, lfpm) 1739 F08b Figure 8. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top Layer. Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size 1739fas, sn1739 U seen in the graph of Figure 8, this is also very effective in further reducing the junction-to-ambient thermal resistance of each line driver. 2ND LAYER 3RD LAYER BOTTOM LAYER 1739 F08a W UU % REDUCTION RELATIVE TO θJA IN STILL AIR 11 LT1739 APPLICATIO S I FOR ATIO Layout and Passive Components With a gain bandwidth product of 200MHz the LT1739 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and a combination of RF-quality supply bypass capacitors (i.e., 0.1µF). As the primary applications have high drive current, use low ESR supply bypass capacitors (1µF to 10µF). The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause frequency peaking. In general, use feedback resistors of 1k or less. Compensation The LT1739 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. Figure 9 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the RF RG VI RC CC (OPTIONAL) VO –RF = RG VI VO (RC || RG) ≤ RF/9 1 < 5MHz 2πRCCC 1739 F09 VI RC CC (OPTIONAL) RG 1739 F10 Figure 9. Compensation for Inverting Gains Figure 10. Compensation for Noninverting Gains Vi VI RC CC VO RF RG CC RG ≤ RF/9 1 < 5MHz 2πRGCC RG CBIG 1739 F11 Figure 11. Alternate Noninverting Compensation Figure 12. Combination Compensation 12 – + VO = 1 (LOW FREQUENCIES) VI R = 1 + F (HIGH FREQUENCIES) RG RF – + U parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by R C and CC should be less than 5MHz to minimize peaking. Figure 10 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the network is bootstrapped. This network can also be placed between the inverting input and an AC ground. Another compensation scheme for noninverting circuits is shown in Figure 11. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of Figures 10 and 11 can be combined as shown in Figure 12. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies. RF VO =1+ VI RG VO (RC || RG) ≤ RF/9 1 < 5MHz 2πRCCC RF VO VO = 1 AT LOW FREQUENCIES VI R = 1 + F AT MEDIUM FREQUENCIES RG =1+ RF AT HIGH FREQUENCIES (RC || RG) 1739 F12 W UU + – – + 1739fas, sn1739 LT1739 APPLICATIO S I FOR ATIO In differential driver applications, as shown on the first page of this data sheet, it is recommended that the gain setting resistor be comprised of two equal value resistors connected to a good AC ground at high frequencies. This ensures that the feedback factor of each amplifier remains less than 0.1 at any frequency. The midpoint of the resistors can be directly connected to ground, with the resulting DC gain to the VOS of the amplifiers, or just bypassed to ground with a 1000pF or larger capacitor. Line Driving Back-Termination The standard method of cable or line back-termination is shown in Figure 13. The cable/line is terminated in its characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.). A back-termination resistor also equal to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. An alternate method of back-termination is shown in Figure 14. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor of n. To analyze this circuit, first ground the input. As RBT = RL/n, and assuming RP2>>RL we require that: ∆VA = ∆VO (1 – 1/n) to increase the effective value of RBT by n. ∆VP = ∆VO (1 – 1/n)/(1 + RF/RG) ∆VO = ∆VP (1 + RP2/RP1) VI RG Figure 13. Standard Cable/Line Back Termination RP2 RP1 VI VP RG Figure 14. Back Termination Using Postive Feedback – + – + U Eliminating ∆VP, we get the following: (1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n) For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 = 12.3. Note that the overall gain is increased: W UU RP2 / (RP2 + RP1) VO = VI (1+ 1/n) / (1+ RF /RG ) − RP1/(RP2 + RP1) [ ][ ] CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL RBT VO RL RF RBT = RL VO 1 = (1 + RF/RG) VI 2 1739 F13 VA RBT RL RF RL n VO 1739 F14 FOR RBT = ( )( 1+ VO = VI 1 RP1 RF =1– n RG RP1 + RP2 RP2/(RP2 + RP1) ) () 1+ RF RG 1 + 1/n – RP1 RP2 + RP1 1739fas, sn1739 13 LT1739 APPLICATIO S I FOR ATIO VI + – RF RG RP RP RG RF VA RBT VO FOR RBT = n= RL 1 RF RP RL n 1– RL VO = VI RR 1+ F + F RG RP 2 1– RBT –VA –VO 1739 F15 –VI Figure 15. Back Termination Using Differential Postive Feedback A simpler method of using positive feedback to reduce the back-termination is shown in Figure 15. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of –RF/RP from –VO to VA ∆VA = ∆VO (RF/RP) and assuming RP >> RL, we require ∆VA = ∆VO (1 – 1/n) solving RF/RP = 1 – 1/n So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: VO/VI = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)] Using positive feedback is often referred to as active termination. Figure 18 shows a full-rate ADSL line driver incorporating positive feedback to reduce the power lost in the back termination resistors by 40% yet still maintains the proper impedance match to the100Ω characteristic line impedance. This circuit also reduces the transformer turns ratio 14 U over the standard line driving approach resulting in lower peak current requirements. With lower current and less power loss in the back termination resistors, this driver dissipates only 1W of power, a 30% reduction. (Additional power savings are possible by further reducing the termination resistors’ value). While the power savings of positive feedback are attractive there is one important system consideration to be addressed, received signal sensitivity. The signal received from the line is sensed across the back termination resistors. With positive feedback, signals are present on both ends of the RBT resistors, reducing the sensed amplitude. Extra gain may be required in the receive channel to compensate, or a completely separate receive path may be implemented through a separate line coupling transformer. A demo board, DC306A-C, is available for the LT1739CFE. This demo board is a complete line driver with an LT1361 receiver included. It allows the evaluation of both standard and active termination approaches. It also has circuitry built in to evaluate the effects of operating with reduced supply current. The schematic of this demo board is shown in Figure 17. Considerations for Fault Protection The basic line driver design, shown on the front page of this data sheet, presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. If left unchecked, the high DC current can heat the LT1739 to thermal shutdown. W UU () RF RP + – 1739fas, sn1739 LT1739 APPLICATIO S I FOR ATIO Using DC blocking capacitors, as shown in Figure 16, to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbs®, varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also +IN • • LINE LOAD 1k 110Ω 1000pF 110Ω –IN Figure 16. Protecting the Driver Against Load Faults and Line Transients U create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT1739 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs. TransZorb is a registered trademark of General Instruments, GSI W UU 12V 12V –12V 24.9k + 1/2 LT1739 SHDN 12.7Ω 0.1µF BAV99 – 1k 1:2 – 1/2 LT1739 12.7Ω SHDNREF 0.1µF + –12V BAV99 12V –12V 1739 F16 1739fas, sn1739 15 LT1739 APPLICATIO S I FOR ATIO C1 0.1µF VCC E2 DRV (+) R2 10k VCC R21 10k 3 R22 10k JP6 1 2 R5 OPT R24 107Ω R25 107Ω R23 OPT C9 0.1µF C15 OPT 4 14 + – U2A LT1739CFE 17 18 5 3 1 20 11 10 1 VEE R3 1k R4 2.49k C16 1000pF C18 OPT 1206 PLACE C4 AND C5 AS CLOSE TO U2 AS POSSIBLE E7 RCVIN (+) C4 0.1µF 25V 0603 R6 2.49k E8 DRV (–) R26 OPT C17 OPT R9 10k 7 R7 1k + U2B LT1739CFE 13 6 19 8 – 2 VEE 9 12 VDD ON 1 8 E10 ON/OFF R13 10k 5 + – JP3 7 6 U4B LT1541CS8 4 E11 VC0NTROL R18 10k 3 + U4A LT1541CS8 1 1 2 – VBIAS Figure 17. LT1739, LT1361 ADSL Demo Board (DC306A-C) 16 U R1 15.4Ω 1/2W 2010 C8 0.1µF 100V 10 E4 LINE (+) JP1 1 4 8 6 COILCRAFT X8504-A C12 0.1µF 100V E5 LINE (–) 2 3 5V VDD U1 LT1121CST-5 SOT233 1 OUT IN GND C2 + 2 1µF 25V 3216 3 2 7 W UU + C3 1µF 25V 3216 + C5 10µF 35V 7343 C6 0.1µF + C7 1µF 25V 3216 C11 1µF 25V 3216 E1 VCC C10 0.1µF + E3 GND R8 15.4Ω 1/2W 2010 E6 VEE 3 JP2 2 1 C13 VCC 0.1µF 3 + – ON/OFF 2 3 R11 1.6k R14 1.6k ADJ 2 3 JP4 FIXED 1 R17 21.5k R10 1k 2 8 U3A LT1361CS8 4 VEE 1 E9 RCV (+) R12 1k R15 OPT C14 0.1µF R16 1k 6 R19 1k – U3B LT1361CS8 7 E12 RCV (–) Q1 FMMT3904 2 5 + R20 9.31k E13 RCVIN (–) 3 2 JP5 1 VBIAS 1739 SD 1739fas, sn1739 LT1739 SI PLIFIED SCHE ATIC V+ Q9 Q10 Q13 Q17 Q3 –IN Q1 R1 Q2 Q4 Q8 Q16 Q12 Q11 V– 1739 SS W W (one amplifier shown) Q7 Q6 Q5 C1 +IN C2 Q14 OUT Q15 Q18 1739fas, sn1739 17 LT1739 PACKAGE DESCRIPTIO 4.95 (.195) 6.60 ± 0.10 4.50 ± 0.10 SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0 ° – 8° 0.65 (.0256) BSC 0.09 – 0.20 (.0036 – .0079) 0.45 – 0.75 (.018 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 18 U FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 6.40 – 6.60* (.252 – .260) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 2.74 (.108) 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX 2.74 6.40 (.108) BSC 0.195 – 0.30 (.0077 – .0118) 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0203 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 1739fas, sn1739 LT1739 PACKAGE DESCRIPTIO 3.40 ± 0.05 1.70 ± 0.05 2.24 ± 0.05 (2 SIDES) 0.23 ± 0.05 3.30 ± 0.05 (2 SIDES) 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (2 SIDES) R = 0.20 TYP 3.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK 6 0.23 ± 0.05 3.30 ± 0.10 (2 SIDES) 1 0.50 BSC 1.70 ± 0.10 (2 SIDES) PIN 1 NOTCH (UE12) DFN 0102 0.200 REF BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE IS A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UE12 Package 12-Lead Plastic DFN (3mm × 4mm) (Reference LTC DWG # 05-08-1695) 0.58 ± 0.05 7 R = 0.115 TYP 0.38 ± 0.10 12 0.75 ± 0.05 0.00 – 0.05 1739fas, sn1739 19 LT1739 TYPICAL APPLICATIO +IN • • 182Ω 1000pF 182Ω –IN RELATED PARTS PART NUMBER LT1361 LT1794 LT1795 LT1813 LT1886 LT1969 LT6300 DESCRIPTION Dual 50MHz, 800V/µs Op Amp Dual 500mA, 200MHz xDSL Line Driver Dual 500mA, 50MHz Current Feedback Amplifier Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp Dual 200mA, 700MHz Op Amp Dual 200mA, 700MHz Op Amp with Power Control Dual 500mA, 200MHz xDSL Line Driver COMMENTS ±15V Operation, 1mV VOS, 1µA IB ADSL CO Driver, Extended Output Swing, Low Power Shutdown/Current Set Function, ADSL CO Driver Low Noise, Low Power Differential Receiver, 4mA/Amplifier 12V Operation, 7mA/Amplifier, ADSL Modem Line Driver 12V Operation, MSOP Package, ADSL Modem Line Driver ADSL CO Driver in SSOP Package 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q www.linear.com U 12V 24.9k + 1/2 LT1739 SHDN 13.7Ω – 1k 1.65k 1.65k 1k *COILCRAFT X8502-A OR EQUIVALENT 1W DRIVER POWER DISSIPATION 1.15W POWER CONSUMPTION 1739 F17 1:1.2* 100Ω LINE – 1/2 LT1739 13.7Ω SHDNREF + –12V Figure 18. ADSL Line Driver Using Active Termination 1739fas, sn1739 LT/TP 0602 1.5K REV A • PRINTED IN THE USA © LINEAR TECHNOLOGY CORPORATION 2001