LT1762

LT1965 1.1A, Low Noise, Low Dropout Linear Regulator FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LT®1965 is a low noise, low dropout linear regulator. The device supplies 1.1A of output current with a 290mV typical dropout voltage. Operating quiescent current is 500μA, reducing to 3V TO 20V + OUT 5.11k 1% ADJ + 4.75k 1% *CERAMIC, TANTALUM OR ALUMINUM ELECTROLYTIC 1965f 1 LT1965 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage .........................................................±22V OUT Pin Voltage ......................................................±22V Input to Output Differential Voltage (Note 2) ......... ±22V ADJ Pin Voltage ........................................................±9V ⎯S⎯H⎯D⎯N Pin Voltage ...................................................±22V Output Short-Circuit Duration .......................... Indefinite Operating Junction Temperature Range (E, I Grade) (Notes 2, 13)......................................–40°C to 125°C Storage Temperature Range...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) (Only for MSOP, TO-220, DD-PAK Packages) ... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW OUT 1 OUT 2 ADJ 3 GND 4 9 8 7 6 5 IN IN SHDN GND OUT OUT ADJ GND 1 2 3 4 8 7 6 5 IN IN SHDN GND 9 MS8E PACKAGE 8-LEAD PLASTIC MSOP DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 65°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB FRONT VIEW 5 4 TAB IS GND 3 2 1 Q PACKAGE 5-LEAD PLASTIC DD-PAK ADJ OUT GND IN SHDN TJMAX = 125°C, θJA = 60°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB FRONT VIEW 5 4 TAB IS GND 3 2 1 T PACKAGE 5-LEAD PLASTIC TO-220 ADJ OUT GND IN SHDN TJMAX = 125°C, θJA = 30°C/W TJMAX = 125°C, θJA = 50°C/W ORDER INFORMATION LEAD FREE FINISH LT1965EDD#PBF LT1965EMS8E#PBF LT1965EQ#PBF LT1965ET#PBF LT1965IDD#PBF LT1965IMS8E#PBF LT1965IQ#PBF LT1965IT#PBF TAPE AND REEL LT1965EDD#TRPBF LT1965EMS8E#TRPBF LT1965EQ#TRPBF LT1965ET#TRPBF LT1965IDD#TRPBF LT1965IMS8E#TRPBF LT1965IQ#TRPBF LT1965IT#TRPBF PART MARKING* LCXW LTCXX LT1965Q LT1965T LCXW LTCXX LT1965Q LT1965T PACKAGE DESCRIPTION 8-Lead (3mm × 3mm) Plastic DFN 8-Lead Plastic MSOP 5-Lead Plastic DD-PAK 5-Lead Plastic TO-220 8-Lead (3mm × 3mm) Plastic DFN 8-Lead Plastic MSOP 5-Lead Plastic DD-PAK 5-Lead Plastic TO-220 TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 1965f 2 LT1965 ELECTRICAL CHARACTERISTICS PARAMETER Minimum Input Voltage (Notes 4, 12) ADJ Pin Voltage (Notes 4, 5) Line Regulation (Note 4) Load Regulation Dropout Voltage VIN = VOUT(NOMINAL) (Notes 6, 7, 12) CONDITIONS ILOAD = 0.5A ILOAD = 1.1A VIN = 2.1V, ILOAD = 1mA 2.3V < VIN < 20V, 1mA < ILOAD < 1.1A ΔVIN = 2.1V to 20V, ILOAD = 1mA VIN = 2.3V, ΔILOAD = 1mA to 1.1A VIN = 2.3V, ΔILOAD = 1mA to 1.1A ILOAD = 1mA ILOAD = 1mA ILOAD = 100mA ILOAD = 100mA ILOAD = 500mA ILOAD = 500mA ILOAD = 1.1A ILOAD = 1.1A GND Pin Current VIN = VOUT(NOMINAL) + 1V (Notes 6, 8) ILOAD = 0mA ILOAD = 1mA ILOAD = 100mA ILOAD = 500mA ILOAD = 1.1A COUT = 10μF, ILOAD = 1.1A, BW = 10Hz to 100kHz VOUT = Off to On VOUT = On to Off V⎯S⎯H⎯D⎯N = 0V V⎯S⎯H⎯D⎯N = 20V VIN = 6V, V⎯S⎯H⎯D⎯N = 0V VIN – VOUT = 1.5V (AVG), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 0.75A VIN = 7V, VOUT = 0 VIN = VOUT(NOMINAL) + 1V, ΔVOUT = -0.1V (Note 6) VIN = –20V, VOUT = 0 VOUT = 1.2V, VIN < 1.2V (Note 4) 175 ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN TYP 1.65 1.8 1.182 1.164 1.20 1.20 3 4.25 0.05 ● MAX 2.3 1.218 1.236 8 8 16 0.08 0.14 0.175 0.28 0.25 0.36 0.36 0.49 1.1 1.5 5.5 20 40 4.5 2 1 10 1 UNITS V V V V mV mV mV V V V V V V V V mA mA mA mA mA μVRMS μA V V μA μA μA dB A A 0.10 ● 0.19 ● 0.29 ● ● ● ● ● ● 0.5 0.6 2.2 8.2 21 40 1.3 0.2 0.85 0.45 0.01 5.5 0.01 57 75 2 1.2 Output Voltage Noise ADJ Pin Bias Current (Notes 4, 9) Shutdown Threshold ⎯S⎯H⎯D⎯N Pin Current (Note 10) Quiescent Current in Shutdown Ripple Rejection Current Limit Input Reverse Leakage Current Reverse Output Current (Note 11) 1 400 mA μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Absolute maximum input to output differential voltage is not achievable with all combinations of rated IN pin and OUT pin voltages. With the IN pin at 22V, the OUT pin may not be pulled below 0V. The total measured voltage from IN to OUT must not exceed ±22V. Note 3: The LT1965 is tested and specified under pulse load conditions such that TJ ≅ TA. The LT1965E is 100% tested at TA = 25°C. Performance at –40°C and 125°C is assured by design, characterization, and correlation with statistical process controls. The LT1965I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 4: The LT1965 is tested and specified for these conditions with the ADJ connected to the OUT pin. Note 5: Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. Limit the output current range if operating at the maximum input voltage. Limit the input-to-output voltage differential if operating at the maximum output current. Note 6: To satisfy minimum input voltage requirements, the LT1965 is tested and specified for these conditions with an external resistor divider (bottom 4.02k, top 4.32k) for an output voltage of 2.5V. The external resistor divider adds 300μA of output DC load current. Note 7: Dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage equals: (VIN – VDROPOUT) Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) + 1V and a current source load. GND pin current increases slightly in dropout. See GND pin current curves in the Typical Performance Characteristics section. 1965f 3 LT1965 ELECTRICAL CHARACTERISTICS Note 9: ADJ pin bias current flows into the ADJ pin. Note 10: ⎯S⎯H⎯D⎯N pin current flows into the ⎯S⎯H⎯D⎯N pin. Note 11: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current flows into the OUT pin and out of the GND pin. Note 12: For the LT1965, the minimum input voltage specification limits the dropout voltage under some output voltage/load conditions. Note 13: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS Typical Dropout Voltage 500 GUARANTEED DROPOUT VOLTAGE (mV) 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 0.2 0.6 0.8 0.4 OUTPUT CURRENT (A) 1 1.2 1965 G01 Guaranteed Dropout Voltage 500 450 TJ = 125°C DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 0.2 0.6 0.8 0.4 OUTPUT CURRENT (A) 1 1.2 1965 G02 Dropout Voltage 500 450 400 350 300 250 200 150 100 50 0 –50 –25 IL = 500mA IL = 1.1A = TEST POINTS TJ = 125°C TJ = 25°C TJ = 25°C IL = 100mA IL = 1mA 0 25 50 75 TEMPERATURE (°C) 100 125 1965 G03 Quiescent Current 1.0 0.9 QUIESCENT CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 VIN = 6V R L = ∞ , IL = 0 VSHDN = VIN ADJ PIN VOLTAGE (V) 1.218 1.214 ADJ Pin Voltage IL = 1mA QUIESCENT CURRENT (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 Quiescent Current TJ = 25°C RL = 4.02k VSHDN = VIN 1.210 1.206 1.202 1.198 1.194 1.190 1.186 1.182 –50 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) 1965 G06 1965 G04 1965 G05 1965f 4 LT1965 TYPICAL PERFORMANCE CHARACTERISTICS GND Pin Current 2.0 1.8 1.6 GND PIN CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10 0 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10 RL = 120Ω, IL = 10mA* RL = 1.2k, IL = 1mA* TJ = 25°C VSHDN = VIN *FOR VOUT = 1.2V 25 GND Pin Current TJ = 25°C VSHDN = VIN *FOR VOUT = 1.2V GND PIN CURRENT (mA) RL = 1.091Ω, IL = 1.1A* 15 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.50 5.00 RL = 12Ω, IL = 100mA* 2.50 0 GND Pin Current vs ILOAD VIN = VOUT(NOMINAL) + 1V GND PIN CURRENT (mA) RL = 24Ω, IL = 50mA* 20 10 RL = 2.4Ω, IL = 500mA* 5 0 0.2 0.6 0.8 0.4 LOAD CURRENT (A) 1.0 1.2 1965 G09 1965 G07 1965 G08 ⎯S⎯H⎯D⎯N Pin Threshold 1.0 0.9 SHDN PIN THRESHOLD (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –50 0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 ON TO OFF OFF TO ON SHDN PIN INPUT CURRENT (μA) 6 5 4 3 2 1 ⎯S⎯H⎯D⎯N Pin Input Current 6.0 5.9 SHDN PIN INPUT CURRENT (μA) 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 0 2 4 6 8 10 12 14 16 18 20 SHDN PIN VOLTAGE (V) 1965 G11 ⎯S⎯H⎯D⎯N Pin Input Current VSHDN = 20V 5.0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1965 G10 1965 G12 ADJ Pin Bias Current 4.5 4.0 ADJ PIN BIAS CURRENT (μA) 3.5 CURRENT LIMIT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 2.0 2.5 Current Limit vs VIN –VOUT ΔVOUT = –100mV 3.0 2.5 TJ = –50°C CURRENT LIMIT (A) 2.0 1.5 1.0 0.5 Current Limit vs Temperature VIN = 7V VOUT = 0V 1.5 TJ = 125°C 1.0 TJ = 25°C 0.5 0 2 4 6 8 10 12 14 16 18 20 INPUT/OUTPUT DIFFERENTIAL (V) 1965 G14 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1965 G13 1965 G15 1965f 5 LT1965 TYPICAL PERFORMANCE CHARACTERISTICS Reverse Output Current 6 REVERSE OUTPUT CURRENT (mA) 5 4 3 2 1 0 0 2 4 6 8 OUTPUT VOLTAGE (V) 10 1965 G16 Reverse Output Current 0.50 REVERSE OUTPUT CURRENT (mA) 0.45 0.40 RIPPLE REJECTION (dB) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 VIN = 0V VOUT = 1.2V 90 80 70 60 50 40 30 Ripple Rejection vs Frequency TJ = 25°C VIN = 0V CURRENT FLOWS INTO OUTPUT PIN VOUT = VADJ 20 IL = 0.75A COUT = 10μF CERAMIC 10 VIN = VOUT(NOMINAL) + 1V + 50mVRMS RIPPLE 0 100 10 1k 10k FREQUENCY (Hz) 100k 1M 1965 G18 1965 G17 Ripple Rejection vs Temperature 100 2.5 Minimum Input Voltage 0 –2 MINIMUM INPUT VOLTAGE (V) LOAD REGULATION (mV) Load Regulation VIN = 2.3V ΔIL = 1mA TO 1.1A RIPPLE REJECTION (dB) 90 2.0 IL = 1.1A 1.5 IL = 500mA IL = 100mA 1.0 –4 –6 –8 –10 –12 –14 80 70 IL = 0.75A VIN = VOUT(NOMINAL) + 1V + 0.5P-P RIPPLE AT f = 120Hz 60 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 0.5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 –16 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1965 G19 1965 G20 1965 G21 Output Noise Spectral Density OUTPUT NOISE SPECTRAL DENSITY (μV Hz) 1.00 OUTPUT NOISE VOLTAGE (μVRMS) COUT = 10μF IL = 1.1A 80 RMS Output Noise vs Load Current (10Hz to 100kHz) COUT = 10μF 70 IL = 1.1A 60 50 VOUT = 2.5V 40 30 20 10 0 0.0001 0.001 VOUT = 1.5V VOUT = 1.8V VOUT = 3.3V 1.8V 10Hz to 100kHz Output Noise COUT = 10μF IL = 1.1A VOUT = 2.5V 0.10 VOUT = 1.8V VOUT = 1.5V VOUT = 3.3V VOUT 100μV/DIV VOUT = 1.2V VOUT = 1.2V 400μs/DIV 1965 G24 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 1965 G22 0.01 0.1 LOAD CURRENT (A) 1 10 1965 G23 1965f 6 LT1965 TYPICAL PERFORMANCE CHARACTERISTICS Transient Response OUTPUT VOLTAGE DEVIATION (mV) 100 50 0 –50 4.0 VOUT = 3.3V SHDN AND OUTPUT VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 OUTPUT 1.0 0.5 0.0 0 10 20 30 40 50 TIME (μs) 60 70 80 0 10 20 30 40 50 60 70 80 90 100 TIME (μs) 1965 G26 VIN = 3.3V COUT = 10μF CERAMIC RL = 2.5k, IL = 1mA FOR VOUT = 2.5V SHDN ⎯S⎯H⎯D⎯N Transient Response –100 LOAD CURRENT (A) 1.5 1.0 0.5 0.0 VIN = 4.3V CIN = 10μF CERAMIC COUT = 10μF CERAMIC 1965 G25 PIN FUNCTIONS (DFN/MSOP/DD-PAK/TO-220) OUT (Pins 1, 2 / 1, 2 / 4 / 4): Output. This pin supplies power to the load. Use a minimum output capacitor of 10μF to prevent oscillations. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitance and reverse output characteristics. ADJ (Pins 3 / 3 / 5 / 5): Adjust. This pin is the input to the error amplifier. It has a typical bias current of 1.3μA that flows into the pin. The ADJ pin voltage is 1.20V referenced to ground. GND (Pins 4, 5 / 4, 5 / 3 / 3): Ground. For the adjustable LT1965, connect the bottom of the resistor divider, setting output voltage, directly to GND for optimum regulation. ⎯S⎯H⎯D⎯N (Pin 6 / 6 / 1 / 1): Shutdown. Pulling the ⎯S⎯H⎯D⎯N pin low puts the LT1965 into a low power state and turns the output off. Drive the ⎯S⎯H⎯D⎯N pin with either logic or an open collector/drain with a pull-up resistor. The resistor supplies the pull-up current to the open collector/drain logic, ⎯⎯⎯⎯ normally several microamperes and the SHDN pin current, typically less than 6μA. If unused, connect the ⎯S⎯H⎯D⎯N pin to VIN. The LT1965 will be in its low power shutdown state if the ⎯S⎯H⎯D⎯N pin is not connected. The ⎯S⎯H⎯D⎯N pin cannot be driven below GND unless it is tied to the IN pin. If the ⎯S⎯H⎯D⎯N pin is driven below GND while IN is powered, the output will turn on. ⎯S⎯H⎯D⎯N pin logic cannot be referenced to a negative supply rail. IN (Pins 7, 8 / 7, 8 / 2 / 2): Input. This pin supplies power to the device. The LT1965 requires a bypass capacitor at IN if located more than six inches from the main input filter capacitor. Include a bypass capacitor in battery-powered circuits as a battery’s output impedance generally rises with frequency. A bypass capacitor in the range of 1μF to 10μF suffices. The LT1965’s design withstands reverse voltages on the IN pin with respect to ground and the OUT pin. In the case of a reversed input, which occurs if a battery is plugged in backwards, the LT1965 behaves as if a diode is in series with its input. No reverse current flows into the LT1965 and no reverse voltage appears at the load. The device protects itself and the load. Exposed Pad (Pin 9 / 9, DFN and MSOP Packages Only): Ground. Tie this pin directly to Pins 4 and 5 and the PCB ground. This pin provides enhanced thermal performance with its connection to the PCB ground. See the Applications Information section for thermal considerations and calculating junction temperature. 1965f 7 LT1965 APPLICATIONS INFORMATION The LT1965 is a 1.1A low dropout regulator with shutdown. The device is capable of supplying 1.1A at a typical dropout voltage of 290mV. The low operating quiescent current (500μA) drops to less than 1μA in shutdown. In addition to its low quiescent current, the LT1965 regulator incorporates several protection features that make it ideal for use in battery-powered systems. The device protects itself against both reverse input and reverse output voltages. In battery backup applications, if a backup battery holds up the output when the input is pulled to ground, the LT1965 performs like it has a diode in series with its output, preventing reverse current flow. Also, in dual supply applications where the regulator load is returned to a negative supply, the output can be pulled below ground by as much as 20V. The LT1965 still starts and operates normally in this situation. Adjustable Operation The LT1965 has an output voltage range of 1.20V to 20V. Figure 1 illustrates that the ratio of two external resistors sets the output voltage. The device servos the output to maintain the ADJ pin voltage at 1.20V referenced to ground. R1’s current equals 1.20V/R1. R2’s current equals R1’s current plus the ADJ pin bias current. The ADJ pin bias current, 1.3μA at 25°C, flows through R2 into the ADJ pin. Use the formula in Figure 1 to calculate output voltage. Linear Technology recommends that R1’s value be less than 12.1k to minimize output voltage errors due to the ADJ pin bias current. In shutdown, the output turns off and the divider current is zero. For curves depicting ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current vs Temperature, see the Typical Performance Characteristics section. IN VIN OUT LT1965 ADJ GND 1965 F01 The adjustable device is tested and specified with the ADJ pin tied to the OUT pin for an output voltage of 1.20V. Specifications for output voltages greater than 1.20V are proportional to the ratio of the desired output voltage to 1.20V: VOUT/1.20V. For example, load regulation for an output current change of 1mA to 1.1A is typically –4.25mV at VOUT = 1.20V. At VOUT = 5V, load regulation is: 5V • – 4 . 25mV = – 17 . 71mV 1 . 20 V Output Capacitance The LT1965’s design is stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 10μF with an ESR of 3Ω or less is recommended to prevent oscillations. The LT1965 is a low quiescent current device and output load transient response is a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger current changes. Ceramic capacitors require extra consideration. Manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics provide high C-V products in a small package at low cost, but exhibit strong voltage and temperature coefficients as shown in Figures 2 and 3. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as low as 1μF to 2μF for the DC bias applied and over the operating temperature range. The X5R and X7R dielectrics yield much more stable characteristics and are more suitable for use as the output capacitor. The X7R type works over a wider temperature range and has better temperature stability whereas X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop 1965f R2 + VOUT ⎛ R2⎞ VOUT = 1.20 V ⎜1 + ⎟ + IADJ • R2 ⎝ R1⎠ VADJ = 1.20 V IADJ = 1.3µA AT 25º C OUTPUT RANGE = 1.20 V TO 19.5V R1 Figure 1. Adjustable Operation 8 LT1965 APPLICATIONS INFORMATION capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltages should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise. A ceramic capacitor produced the trace in Figure 4 in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise. 20 0 CHANGE IN VALUE (%) CHANGE IN VALUE (%) X5R –20 –40 –60 Y5V –80 –100 Overload Recovery Like many IC power regulators, the LT1965 has safe operating area protection. The safe area protection decreases current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. The protective design provides some output current at all values of input-tooutput voltage up to the device breakdown. When power is first applied, as input voltage rises, the output follows the input, allowing the regulator to start up into very heavy loads. During start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. With a high input voltage, a problem can occur wherein removal of an output short will not allow the output to recover. BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF 40 20 0 –20 –40 –60 –80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF 50 25 75 0 TEMPERATURE (°C) 100 125 1965 F03 X5R Y5V 0 2 4 8 6 10 12 DC BIAS VOLTAGE (V) 14 16 1965 F02 –100 –50 –25 Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics 1mV/DIV VOUT = 1.3V COUT = 10μF ILOAD = 0 1ms/DIV 1965 F04 Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor 1965f 9 LT1965 APPLICATIONS INFORMATION Other regulators, such as the LT1083/LT1084/LT1085 family, also exhibit this phenomenon, so it is not unique to the LT1965. The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations include immediately after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage has already been turned on. The load line for such a load may intersect the output current curve at two points. If this happens, there are two stable output operating points for the regulator. With this double intersection, the input power supply may need to be cycled down to zero and brought up again to make the output recover. Output Voltage Noise The LT1965 regulator’s design provides low output voltage noise over the 10Hz to 100kHz bandwidth while operating ⎯⎯ at full load. Output voltage noise is approximately 80nV/√Hz over this frequency bandwidth for the LT1965. For higher output voltages (generated by using a resistor divider), the output voltage noise gains up accordingly. Higher values of output voltage noise may be measured if care is not exercised with regard to circuit layout and testing. Crosstalk from nearby traces can induce unwanted noise onto the LT1965’s output. Power supply ripple rejection must also be considered; the LT1965 regulator does not have unlimited power supply rejection and will pass a small portion of the input noise through to the output. Thermal Considerations The LT1965’s maximum rated junction temperature of 125°C limits its power handling capability. Two components comprise the power dissipated by the device: 1. Output current multiplied by the input/output voltage differential: IOUT • (VIN – VOUT), and 2. GND pin current multiplied by the input voltage: IGND • VIN GND pin current is determined using the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation equals the sum of the two components listed. The LT1965 regulator has internal thermal limiting that protects the device during overload conditions. For continuous normal conditions, do not exceed the maximum junction temperature rating of 125°C. Carefully consider all sources of thermal resistance from junction to ambient including other heat sources mounted in proximity to the LT1965. The underside of the LT1965 DFN package has exposed metal (4mm2) from the lead frame to the die attachment. The underside of the LT1965 MSOP package also has exposed metal (2mm2). Both packages allow heat to directly transfer from the die junction to the printed circuit board metal to control maximum operating junction temperature. The dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of a PCB. Connect this metal to GND on the PCB. The multiple IN and OUT pins of the LT1965 also assist in spreading heat to the PCB. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. 1965f 10 LT1965 APPLICATIONS INFORMATION The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 1/16" FR-4 board with one ounce copper. Table 1. Measured Thermal Resistance for DFN Package Copper Area Topside* Backside 2500mm2 2500mm2 2 1000mm 2500mm2 2 225mm 2500mm2 100mm2 2500mm2 2 50mm 2500mm2 *Device is mounted on topside Board Area 2500mm2 2500mm2 2500mm2 2500mm2 2500mm2 Thermal Resistance (Junction-to-Ambient) 60°C/W 62°C/W 65°C/W 68°C/W 70°C/W Calculating Junction Temperature Example: Given an output voltage of 2.5V, an input voltage range of 3.3V ± 5%, an output current range of 0mA to 500mA and a maximum ambient temperature of 85°C, what will the maximum junction temperature be? The power dissipated by the device equals: IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX) where: IOUT(MAX) = 500mA VIN(MAX) = 3.465V IGND at (IOUT = 500mA, VIN = 3.465V) = 8.2mA So, P = 500mA(3.465V – 2.5V) + 8.2mA(3.465V) = 0.511W Using a DFN package, the thermal resistance will be in the range of 60°C/W to 70°C/W depending on the copper area. So the junction temperature rise above ambient approximately equals: 0.511W • 65°C/W = 33.22°C The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient or: TJMAX = 85°C + 33.22°C = 118.22°C Table 2. Measured Thermal Resistance for MSOP Package Copper Area Topside* Backside 2500mm2 2500mm2 2 1000mm 2500mm2 2 225mm 2500mm2 100mm2 2500mm2 2 50mm 2500mm2 *Device is mounted on topside Board Area 2500mm2 2500mm2 2500mm2 2500mm2 2500mm2 Thermal Resistance (Junction-to-Ambient) 55°C/W 57°C/W 60°C/W 65°C/W 68°C/W Table 3. Measured Thermal Resistance for DD-PAK Package Copper Area Topside* Backside 2500mm2 1000mm2 2500mm2 2500mm2 Board Area 2500mm2 2500mm2 2500mm2 Thermal Resistance (Junction-to-Ambient) 25°C/W 30°C/W 35°C/W 125mm2 2500mm2 *Device is mounted on topside Measured Thermal Resistance for TO-220 Package Thermal Resistance (Junction-to-Case) = 3°C/W 1965f 11 LT1965 APPLICATIONS INFORMATION Protection Features The LT1965 incorporates several protection features that make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device also protects against reverse input voltages, reverse output voltages and reverse output-to-input voltages. Current limit protection and thermal overload protection protect the device against current overload conditions at its output. For normal operation, do not exceed the maximum rated junction temperature of 125°C. The input of the device withstands reverse voltages of 22V. The LT1965 limits current flow to less than 1mA (typically less than 200μA) and no negative voltage appears at the output. The device protects both itself and the load against batteries that are plugged in backwards. The LT1965 incurs no damage if its output is pulled below ground. If the input is left open circuit or grounded, the output can be pulled below ground by 22V. For the adjustable version, the output acts like an open circuit and no current flows from the output. However, current flows in (but is limited by) the resistor divider that sets the output voltage. If the input is powered by a voltage source, the output sources current equal to its current limit capability and the LT1965 protects itself by thermal limiting. In this case, grounding the ⎯S⎯H⎯D⎯N pin turns off the device and stops the output from sourcing current. The LT1965 incurs no damage if the ADJ pin is pulled above or below ground by 9V. If the input is left open circuit or grounded, the ADJ pin performs like an open circuit when pulled below ground and like a large resistor (typically 5k up to 3V on the ADJ pin and then 1.5k up to 9V) in series with a diode when pulled above ground. In situations where the ADJ pin connects to a resistor divider that would pull the ADJ pin above its 9V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.20V reference when the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ pin is at 9V. The 11V difference between the OUT and ADJ pins divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 2.2k. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage, or is left open circuit. Current flow back into the output follows the curve shown in Figure 5. If the LT1965’s IN pin is forced below the OUT pin or the OUT pin is pulled above the IN pin, input current typically drops to less than 2μA. This occurs if the LT1965 input is connected to a discharged (low voltage) battery and either a backup battery or a second regulator holds up the output. The state of the ⎯S⎯H⎯D⎯N pin has no effect on the reverse output current if the output is pulled above the input. 6 REVERSE OUTPUT CURRENT (mA) 5 4 3 2 1 0 0 TJ = 25°C VIN = 0V CURRENT FLOWS INTO OUTPUT PIN VOUT = VADJ 2 4 6 8 OUTPUT VOLTAGE (V) 10 1965 F05 Figure 5. Reverse Output Current 1965f 12 LT1965 TYPICAL APPLICATIONS Paralleling of Regulators for Higher Output Current R1 0.01Ω + VIN > 3.7V IN C1 100μF LT1965 SHDN GND R2 0.01Ω IN LT1965 SHDN SHDN GND OUT ADJ R8 6.98k 1% R9 4.02k 1% + 3.3V 2.2A C2 22μF OUT R6 6.65k 1% R7 4.02k 1% R5 10k 1 C3 0.01μF 1965 TA03 ADJ R3 2.2k R4 2.2k 3 + – 8 1/2 LT1366 4 2 1965f 13 LT1965 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.675 ± 0.05 0.38 ± 0.10 8 3.5 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE PIN 1 TOP MARK (NOTE 6) 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD) DFN 1203 0.200 REF 0.75 ± 0.05 4 0.25 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE MS8E Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1662) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 ± 0.102 (.110 ± .004) 0.889 ± 0.127 (.035 ± .005) 1 2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 8 7 65 0.52 (.0205) REF 5.23 (.206) MIN 2.083 ± 0.102 3.20 – 3.45 (.082 ± .004) (.126 – .136) 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 8 1 23 4 RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 0° – 6° TYP DETAIL “A” 0.18 (.007) SEATING PLANE 0.53 ± 0.152 (.021 ± .006) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 1.10 (.043) MAX 0.86 (.034) REF 0.254 (.010) GAUGE PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS8E) 0603 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1965f 14 LT1965 PACKAGE DESCRIPTION Q Package 5-Lead Plastic DD Pak (Reference LTC DWG # 05-08-1461) .256 (6.502) .060 (1.524) .390 – .415 (9.906 – 10.541) 15° TYP .165 – .180 (4.191 – 4.572) .045 – .055 (1.143 – 1.397) .060 (1.524) .183 (4.648) .060 (1.524) TYP .330 – .370 (8.382 – 9.398) .059 (1.499) TYP ( +.008 .004 –.004 +0.203 0.102 –0.102 ) .075 (1.905) .300 (7.620) BOTTOM VIEW OF DD PAK HATCHED AREA IS SOLDER PLATED COPPER HEAT SINK +.012 .143 –.020 +0.305 3.632 –0.508 .067 (1.702) .028 – .038 BSC (0.711 – 0.965) TYP .013 – .023 (0.330 – 0.584) .095 – .115 (2.413 – 2.921) .050 ± .012 (1.270 ± 0.305) Q(DD5) 0502 ( ) .420 .080 .420 .276 .350 .205 .565 .325 .565 .320 .090 NOTE: 1. DIMENSIONS IN INCH/ (MILLIMETER) 2. DRAWING NOT TO SCALE .067 .042 .067 .090 .042 RECOMMENDED SOLDER PAD LAYOUT RECOMMENDED SOLDER PAD LAYOUT FOR THICKER SOLDER PASTE APPLICATIONS T Package 5-Lead Plastic TO-220 (Standard) (Reference LTC DWG # 05-08-1420) .390 – .415 (9.906 – 10.541) .147 – .155 (3.734 – 3.937) DIA .230 – .270 (5.842 – 6.858) .460 – .500 (11.684 – 12.700) .570 – .620 (14.478 – 15.748) .330 – .370 (8.382 – 9.398) .700 – .728 (17.78 – 18.491) .620 (15.75) TYP .165 – .180 (4.191 – 4.572) .045 – .055 (1.143 – 1.397) SEATING PLANE .260 – .320 (6.60 – 8.13) .152 – .202 (3.861 – 5.131) .095 – .115 (2.413 – 2.921) .155 – .195* (3.937 – 4.953) .013 – .023 (0.330 – 0.584) .067 BSC (1.70) .028 – .038 (0.711 – 0.965) .135 – .165 (3.429 – 4.191) * MEASURED AT THE SEATING PLANE T5 (TO-220) 0801 1965f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT1965 TYPICAL APPLICATION Adjustable Current Source R5, 0.01Ω IN LT1965 OUT LOAD + VIN > 2.7V C1 10μF R1 1k LT1004-1.2 R2 80.6k R4 2.2k R6 2.2k C3 1μF SHDN ADJ GND R8 100k + C4 10μF R3 2k 2 – 1/2 LT1366 8 1 1965 TA04 R7 470Ω 3 NOTE: ADJUST R1 FOR 0A TO 1.1A CONSTANT-CURRENT C2 3.3μF + 4 RELATED PARTS PART NUMBER LT1129 LT1761 LT1762 LT1763 LT1764/LT1764A LTC1844 LT1962 LT1963/LT1963A DESCRIPTION 700mA, Micropower, LDO 100mA, Low Noise Micropower, LDO 150mA, Low Noise Micropower, LDO 500mA, Low Noise Micropower, LDO 3A, Low Noise, Fast Transient Response, LDO 150mA, Very Low Drop-Out LDO 300mA, Low Noise Micropower, LDO COMMENTS VIN: 4.2V to 30V, VOUT(MIN) = 3.8V, VDO = 0.40V, IQ = 50μA, ISD = 16μA; DD, SOT-223, S8, TO220-5 and TSSOP20 Packages VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 20μA, ISD = < 1μA, Low Noise < 20μVRMS , Stable with 1μF Ceramic Capacitors, ThinSOT™ Package VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 25μA, ISD = < 1μA, Low Noise < 20μVRMS , MS8 Package VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 30μA, ISD = < 1μA, Low Noise < 20μVRMS , S8 Package VIN: 2.7V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD = < 1μA, Low Noise < 40μVRMS , “A” Version Stable with Ceramic Capacitors, DD and TO220-5 Packages VIN: 1.6V to 6.5V, VOUT(MIN) = 1.25V, VDO = 0.08V, IQ = 35μA, ISD = < 1μA, Low Noise < 60μVRMS , ThinSOT™ Package VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.27V, IQ = 30μA, ISD = < 1μA, Low Noise < 20μVRMS , MS8 Package 1.5A, Low Noise, Fast Transient Response, VIN: 2.1V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD = < 1μA, Low Noise < 40μVRMS , “A” Version Stable with Ceramic Capacitors; LDO DD, TO220-5, SOT-223 and S8 Packages 100mA, Low Voltage VDO , VIN(MIN) = 0.9V, LDO 500mA, Low Voltage VDO , VIN(MIN) = 0.9V, LDO Dual, 2x 100mA, Low Noise Micropower, LDO Dual, 100mA/500mA, Low Noise Micropower, LDO Dual, 2x 100mA, Low Noise Micropower, LDO with Independent Inputs VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.15V, IQ = 120μA, ISD = 3μA, DFN and MS8 Packages VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.16V, IQ = 120μA, ISD = 3μA, DFN and S8 Packages VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 40μA, ISD = < 1μA, DFN and MS10 Packages VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 60μA, ISD = < 1μA, DFN and TSSOP Packages VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 25μA, ISD = < 1μA, Low Noise < 20μVRMS , DFN and MS10 Packages LT3020 LT3021 LT3023 LT3024 LT3027 LT3028 Dual, 100mA/500mA, Low Noise VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 30μA, ISD = < 1μA, Micropower, LDO with Independent Inputs Low Noise < 20μVRMS , DFN and TSSOP Packages ThinSOT is a trademark of Linear Technology Corporation 1965f 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0807 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007