LT1794CSW

LT1794 Dual 500mA, 200MHz xDSL Line Driver Amplifier FEATURES s s s s s s s DESCRIPTIO s s s Exceeds All Requirements For Full Rate, Downstream ADSL Line Drivers ± 500mA Minimum IOUT ± 11.1V Output Swing, VS = ± 12V, RL = 100Ω ±10.9V Output Swing, VS = ± 12V, IL = 250mA Low Distortion: – 82dBc at 1MHz, 2VP-P Into 50Ω Power Saving Adjustable Supply Current Power Enhanced Small Footprint Packages: 20-Lead TSSOP and 20-Lead SW 200MHz Gain Bandwidth 500V/µs Slew Rate Specified at ±15V, ±12V and ± 5V The LT®1794 is a 500mA minimum output current, dual op amp with outstanding distortion performance. The amplifiers are gain-of-ten stable, but can be easily compensated for lower gains. The extended output swing allows for lower supply rails to reduce system power. Supply current is set with an external resistor to optimize power dissipation. The LT1794 features balanced, high impedance inputs with low input bias current and input offset voltage. Active termination is easily implemented for further system power reduction. Short-circuit protection and thermal shutdown insure the device’s ruggedness. The outputs drive a 100Ω load to ±11.1V with ±12V supplies, and ±10.9V with a 250mA load. The LT1794, with its increased swing on lower supplies, can be used to upgrade LT1795 line driver applications. The LT1794 is available in the very small, thermally enhanced, 20-lead TSSOP for maximum port density in line driver applications. The 20-lead SW is also available. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s High Density ADSL Central Office Line Drivers High Efficiency ADSL, HDSL2, G.lite, SHDSL Line Drivers Buffers Test Equipment Amplifiers Cable Drivers TYPICAL APPLICATIO High Efficiency ±12V Supply ADSL Central Office Line Driver 12V RBIAS 24.9k SHDN 12.7Ω +IN + 1/2 LT1794 – 1k 110Ω 1000pF 110Ω 1:2* • • 1k *COILCRAFT X8390-A OR EQUIVALENT ISUPPLY = 10mA PER AMPLIFIER WITH RBIAS = 24.9k 1794 TA01 – 1/2 LT1794 –IN 12.7Ω SHDNREF + –12V U 100Ω U U 1 LT1794 ABSOLUTE MAXIMUM RATINGS Supply Voltage (V + to V –) .................................... ±18V Input Current ..................................................... ± 10mA Output Short-Circuit Duration (Note 2) ........... Indefinite Operating Temperature Range ............... – 40°C to 85°C PACKAGE/ORDER INFORMATION TOP VIEW V– 1 NC 2 –IN 3 +IN 4 SHDN 5 SHDNREF 6 +IN 7 –IN 8 NC 9 V – 10 20 V – 19 NC 18 OUT 17 V + 16 NC 15 NC 14 V + 13 OUT 12 NC 11 V – ORDER PART NUMBER NC 1 LT1794CFE LT1794IFE FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4) UNDERSIDE METAL CONNECTED TO V– Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VOS PARAMETER Input Offset Voltage The q denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCM = 0V, pulse tested, ± 5V ≤ VS ≤ ± 15V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3) CONDITIONS q Input Offset Voltage Matching q Input Offset Voltage Drift IOS IB Input Offset Current Input Bias Current q Input Bias Current Matching q en in RIN Input Noise Voltage Density Input Noise Current Density Input Resistance f = 10kHz f = 10kHz VCM = 2V) to Differential (V + – (V –+ 2V) q 2 U U W WW U W (Note 1) Specified Temperature Range (Note 3) .. – 40°C to 85°C Junction Temperature .......................................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C TOP VIEW 20 NC 19 V + 18 OUT 17 V – 16 V – 15 V – 14 V – 13 –IN 12 +IN 11 SHDNREF SW PACKAGE 20-LEAD PLASTIC SO ORDER PART NUMBER LT1794CSW LT1794ISW V+ 2 OUT 3 V– 4 V– V– V– 5 6 7 –IN 8 +IN 9 SHDN 10 TJMAX = 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4) MIN TYP 1 0.3 MAX 5.0 7.5 5.0 7.5 500 800 ±4 ±6 500 800 UNITS mV mV mV mV µV/°C nA nA µA µA nA nA nV/√Hz pA/√Hz MΩ MΩ q q 10 100 ± 0.1 100 8 0.8 5 50 6.5 LT1794 ELECTRICAL CHARACTERISTICS SYMBOL CIN PARAMETER Input Capacitance Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR PSRR AVOL Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain (Note 5) (Note 5) VCM = (V + – 2V) to (V – + 2V) q q q The q denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCM = 0V, pulse tested, ± 5V ≤ VS ≤ ± 15V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3) CONDITIONS MIN V+ –2 TYP 3 V+ – V– + 83 88 82 76 70 14.0 13.9 11.1 10.9 4.0 3.9 720 13 10 8 6 4 q MAX UNITS pF V V dB dB dB dB dB dB dB dB dB dB ±V ±V ±V ±V ±V ±V ±V ±V ±V ±V ±V ±V mA 1 1 V– + 2 74 66 74 66 70 64 63 57 60 54 13.8 13.6 13.6 13.4 10.9 10.7 10.6 10.4 3.7 3.5 3.6 3.4 500 10 8 8.0 6.7 VS = ± 4V to ± 15V q VS = ± 15V, VOUT = ±13V, RL = 100Ω q VS = ±12V, VOUT = ±10V, RL = 40Ω q VS = ± 5V, VOUT = ±3V, RL = 25Ω q VOUT Output Swing VS = ± 15V, RL = 100Ω q VS = ± 15V, IL = 250mA q VS = ± 12V, RL = 100Ω q VS = ± 12V, IL = 250mA q VS = ±5V, RL = 25Ω q VS = ± 5V, IL = 250mA q IOUT IS Maximum Output Current Supply Current per Amplifier VS = ± 15V, RL = 1Ω VS = ± 15V, RBIAS = 24.9k (Note 6) q 18 20 13.5 15.0 mA mA mA mA mA mA mA mA mA mA mA dB dB V/µs V/µs dBc dBc MHz VS = ± 12V, RBIAS = 24.9k (Note 6) VS = ± 12V, RBIAS = 32.4k (Note 6) VS = ± 12V, RBIAS = 43.2k (Note 6) VS = ± 12V, RBIAS = 66.5k (Note 6) VS = ± 5V, RBIAS = 24.9k (Note 6) Supply Current in Shutdown Output Leakage in Shutdown Channel Separation SR HD2 HD3 GBW Slew Rate Differential 2nd Harmonic Distortion Differential 3rd Harmonic Distortion Gain Bandwidth VSHDN = 0.4V VSHDN = 0.4V VS = ±12V, VOUT = ±10V, RL = 40Ω q q 2.2 1.8 3.4 0.1 0.3 5.0 5.8 1 1 80 77 300 100 110 600 200 –85 – 82 200 VS = ± 15V, AV = – 10, (Note 7) VS = ± 5V, AV = – 10, (Note 7) VS = ± 12V, AV = 10, 2VP-P, RL = 50Ω, 1MHz VS = ± 12V, AV = 10, 2VP-P, RL = 50Ω, 1MHz f = 1MHz 3 LT1794 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Applies to short circuits to ground only. A short circuit between the output and either supply may permanently damage the part when operated on supplies greater than ± 10V. Note 3: The LT1794C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet these extended temperature limits, but is not tested at – 40°C and 85°C. The LT1794I is guaranteed to meet the extended temperature limits. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. Note 5: Guaranteed by the CMRR tests. Note 6: RBIAS is connected between V + and the SHDN pin. Note 7: Slew rate is measured at ± 5V on a ± 10V output signal while operating on ± 15V supplies and ±1V on a ± 3V output signal while operating on ± 5V supplies. TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Ambient Temperature VS = ±12V 14 RBIAS = 24.9k TO SHDN VSHDNREF = 0V 13 12 11 10 9 8 7 6 5 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 15 V+ –0.5 COMMON MODE RANGE (V) –1.0 –1.5 ± IBIAS (nA) –2.0 ISUPPLY PER AMPLIFIER (mA) Input Noise Spectral Density 100 TA = 25°C VS = ± 12V IS PER AMPLIFIER = 10mA en 100 OUTPUT SATURATION VOLTAGE (V) INPUT VOLTAGE NOISE (V/VHz) 10 ISC (mA) 1 in 0.1 1 10 100 1k FREQUENCY (Hz) 10k 4 UW 1794 G01 1794 G04 Input Common Mode Range vs Supply Voltage TA = 25°C ∆VOS > 1mV Input Bias Current vs Ambient Temperature 200 VS = ± 12V 180 IS PER AMPLIFIER = 10mA 160 140 120 100 80 60 40 20 2.0 1.5 1.0 0.5 V– 2 4 8 10 6 SUPPLY VOLTAGE (± V) 12 14 1794 G02 0 –50 –30 10 30 50 –10 TEMPERATURE (°C) 70 90 1794 G03 Output Short-Circuit Current vs Ambient Temperature 800 780 INPUT CURRENT NOISE (pA/VHz) Output Saturation Voltage vs Ambient Temperature V+ –0.5 –1.0 –1.5 ILOAD = 250mA VS = ± 12V RL = 100Ω VS = ± 12V IS PER AMPLIFIER = 10mA 760 740 720 700 680 660 640 620 SOURCING SINKING 10 1 1.5 1.0 0.5 V– – 50 –30 –10 ILOAD = 250mA RL = 100Ω 0.1 100k 600 –50 –30 30 –10 10 50 TEMPERATURE (°C) 70 90 50 30 10 TEMPERATURE (°C) 70 90 1794 G06 1794 G05 LT1794 TYPICAL PERFOR A CE CHARACTERISTICS Open-Loop Gain and Phase vs Frequency 120 100 80 60 GAIN (dB) 40 20 0 GAIN TA = 25°C VS = ±12V AV = – 10 RL = 100Ω IS PER AMPLIFIER = 10mA 1M 10M FREQUENCY (Hz) 100M 1794 G07 PHASE –3dB BANDWIDTH (MHz) 30 25 20 15 10 5 0 2 4 6 8 10 12 14 SUPPLY CURRENT PER AMPLIFIER (mA) 1794 G08 –40 –80 –120 –160 –200 –240 –280 SLEW RATE (V/µs) –20 –40 –60 –80 100k CMRR vs Frequency 100 COMMON MODE REJECTION RATIO (dB) 90 80 70 60 50 40 30 20 10 0 0.1 POWER SUPPLY REJECTION (dB) TA = 25°C VS = ±12V IS = 10mA PER AMPLIFIER GAIN (dB) 1 10 FREQUENCY (MHz) Output Impedance vs Frequency 1000 TA = 25°C VS ± 12V IS PER AMPLIFIER = 2mA 10 IS PER AMPLIFIER = 10mA IS PER AMPLIFIER = 15mA ISHDN (mA) 2.5 SUPPLY CURRENT PER AMPLIFIER (mA) 100 OUTPUT IMPEDANCE (Ω) 1 0.1 0.01 0.01 0.1 1 10 FREQUENCY (MHz) UW 1794 G10 1734 G13 –3dB Bandwidth vs Supply Current 120 80 40 0 PHASE (DEG) Slew Rate vs Supply Current 1000 900 800 700 600 500 400 300 200 100 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SUPPLY CURRENT PER AMPLIFIER (mA) 1794 G09 45 40 35 TA = 25°C VS = ±12V AV = 10 RL = 100Ω TA = 25°C VS = ±12V AV = – 10 RL = 1k RISING FALLING PSRR vs Frequency 100 90 80 70 60 50 40 (–) SUPPLY (+) SUPPLY VS = ±12V AV = 10 IS = 10mA PER AMPLIFIER Frequency Response vs Supply Current 30 25 20 15 10 5 0 –5 –10 –15 –20 2mA PER AMPLIFIER 10mA PER AMPLIFIER 15mA PER AMPLIFIER VS = ±12V AV = 10 30 20 10 0 –10 0.01 100 0.1 1 10 FREQUENCY (MHz) 100 1794 G11 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1794 G12 ISHDN vs VSHDN TA = 25°C VS = ± 12V VSHDNREF = 0V 35 30 25 20 15 10 5 0 Supply Current vs VSHDN TA = 25°C VS = ± 12V VSHDNREF = 0V 2.0 1.5 1.0 0.5 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V) 1794 G14 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V) 1794 G14 5 LT1794 TYPICAL PERFOR A CE CHARACTERISTICS Differential Harmonic Distortion vs Output Amplitude f = 1MHz TA = 25°C –50 VS = ±12V AV = 10 RL = 50Ω –60 I PER AMPLIFIER = 10mA S HD3 –70 –80 HD2 –90 –100 0 2 4 6 8 10 12 14 16 18 VOUT(P-P) 1794 G16 –40 DISTORTION (dBc) DISTORTION (dBc) Differential Harmonic Distortion vs Supply Current –40 –45 –50 VO = 10VP-P VS = ± 12V AV = 10 RL = 50Ω f = 1MHz, HD3 –60 –65 –70 –75 –80 –85 2 3 4 5 f = 1MHz, HD2 6 7 8 9 10 ISUPPLY PER AMPLIFIER (mA) 11 f = 100kHz, HD2 f = 100kHz, HD3 –55 OUTPUT VOLTAGE (VP-P) DISTORTION (dBc) 6 UW Differential Harmonic Distortion vs Frequency –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 HD2 HD3 VO = 10VP-P TA = 25°C VS = ±12V AV = 10 RL = 50Ω IS PER AMPLIFIER = 10mA –90 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1794 G17 Undistorted Output Swing vs Frequency 20 15 10 SFDR > 40dB TA = 25°C VS = ± 12V AV = 10 RL = 50Ω IS PER AMPLIFIER = 10mA 300k 1M 3M FREQUENCY (Hz) 10M 1794 G19 5 0 100k 1794 G18 LT1794 TEST CIRCUIT SUPPLY BYPASSING 12V RSHDN 9 2 0.1µF 0.1µF VOUT(P-P) + + 12V 4.7µF 4.7µF –12V + 4.7µF 0.1µF + A 19 10 (SHDN) 3 6 7 12.7Ω 1k RL ≈ 50Ω 0.01µF 1k 12.7Ω B 18 16 17 11 (SHDNREF) 1794 TC 8 10k – 4 –12V 5 1:2* OUT (+) EIN 49.9Ω MINICIRCUITS ZSC5-2-2 SPLITTER OUT (–) 110Ω 110Ω 10k 100 LINE LOAD 13 – + 15 14 –12V 12 *COILCRAFT X8390-A OR EQUIVALENT VOUTP-P AMPLITUDE SET AT EACH AMPLIFIER OUTPUT DISTORTION MEASURED ACROSS LINE LOAD APPLICATIO S I FOR ATIO The LT1794 is a high speed, 200MHz gain bandwidth product, dual voltage feedback amplifier with high output current drive capability, 500mA source and sink. The LT1794 is ideal for use as a line driver in xDSL data communication applications. The output voltage swing has been optimized to provide sufficient headroom when operating from ± 12V power supplies in full-rate ADSL applications. The LT1794 also allows for an adjustment of the operating current to minimize power consumption. In addition, the LT1794 is available in small footprint surface mount packages to minimize PCB area in multiport central office DSL cards. To minimize signal distortion, the LT1794 amplifiers are decompensated to provide very high open-loop gain at high frequency. As a result each amplifier is frequency stable with a closed-loop gain of 10 or more. If a closedloop gain of less than 10 is desired, external frequency compensating components can be used. U Setting the Quiescent Operating Current Power consumption and dissipation are critical concerns in multiport xDSL applications. Two pins, Shutdown (SHDN) and Shutdown Reference (SHDNREF), are provided to control quiescent power consumption and allow for the complete shutdown of the driver. The quiescent current should be set high enough to prevent distortion induced errors in a particular application, but not so high that power is wasted in the driver unnecessarily. A good starting point to evaluate the LT1794 is to set the quiescent current to 10mA per amplifier. The internal biasing circuitry is shown in Figure 1. Grounding the SHDNREF pin and directly driving the SHDN pin with a voltage can control the operating current as seen in the Typical Performance Characteristics. When the SHDN pin is less than SHDNREF + 0.4V, the driver is shut down and consumes typically only 100µA of supply current and the W UU 7 LT1794 APPLICATIO S I FOR ATIO SHDN 5I I 2k 2I 2I 1k TO START-UP CIRCUITRY SHDNREF IBIAS TO AMPLIFIERS BIAS CIRCUITRY 1794 F01 IBIAS = 2 ISHDN = ISHDNREF 5 ISUPPLY PER AMPLIFIER (mA) = 64 • IBIAS Figure 1. Internal Current Biasing Circuitry 30 25 20 15 VS = ± 12V ISUPPLY PER AMPLIFIER (mA) 10 SHDNREF 5 0 7 10 40 70 100 RBIAS (kΩ) 130 160 190 1794 F02 Figure 2. RBIAS to V+ Current Control 45 40 VS = ± 12V ISUPPLY PER AMPLIFIER (mA) 35 30 25 20 15 10 5 0 4 7 10 30 50 70 Figure 3. RBIAS to Ground Current Control 8 U outputs are in a high impedance state. Part to part variations however, will cause inconsistent control of the quiescent current if direct voltage drive of the SHDN pin is used. Using a single external resistor, RBIAS, connected in one of two ways provides a much more predictable control of the quiescent supply current. Figure 2 illustrates the effect on supply current per amplifier with RBIAS connected between the SHDN pin and the 12V V + supply of the LT1794 and the approximate design equations. Figure 3 illustrates the same control with RBIAS connected between the SHDNREF pin and ground while the SHDN pin is tied to V +. Either approach is equally effective. V + = 12V RBIAS SHDN IS PER AMPLIFIER (mA) ≈ V + – 1.2V • 25.6 RBIAS + 2k RBIAS = V + – 1.2V • 25.6 – 2k IS PER AMPLIFIER (mA) V + = 12V SHDN V + – 1.2V • 64 IS PER AMPLIFIER (mA) ≈ RBIAS + 5k V + – 1.2V • 64 – 5k IS PER AMPLIFIER (mA) RBIAS = SHDNREF RBIAS W UU 90 100 130 150 170 190 210 230 250 270 290 RBIAS (kΩ) 1794 F03 LT1794 APPLICATIO S I FOR ATIO Logic Controlled Operating Current The DSP controller in a typical xDSL application can have I/O pins assigned to provide logic control of the LT1794 line driver operating current. As shown in Figure 4 one or two logic control inputs can control two or four different operating modes. The logic inputs add or subtract current to the SHDN input to set the operating current. The one logic input example selects the supply current to be either full power, 10mA per amplifier or just 2mA per amplifier, which significantly reduces the driver power consumption while maintaining less than 2Ω output impedance to frequencies less than 1MHz. This low power mode retains termination impedance at the amplifier outputs and the line driving back termination resistors. With this termination, while a DSL port is not transmitting data, it can still sense a received signal from the line across the backtermination resistors and respond accordingly. The two logic input control provides two intermediate (approximately 7mA per amplifier and 5mA per amplifier) operating levels between full power and termination modes. These modes can be useful for overall system power management when full power transmissions are not necessary. Two Control Inputs VC1 H H L L RESISTOR VALUES (kΩ) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 RC1 11.5 13.0 21.5 8.66 10.7 20.5 19.1 22.1 36.5 14.3 17.8 34.0 RCO VC0 SUPPLY CURRENT PER AMPLIFIER (mA) H 10 10 10 10 10 10 L 7 7 7 7 7 7 H 5 5 5 5 5 5 L 2 2 2 2 2 2 One Control Input RESISTOR VALUES (kΩ) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 7.32 8.25 13.7 5.49 6.65 12.7 RC VC H L SUPPLY CURRENT PER AMPLIFIER (mA) 10 10 10 10 10 10 2 2 2 2 2 2 1794 F04 Figure 4. Providing Logic Input Control of Operating Current U Shutdown and Recovery The ultimate power saving action on a completely idle port is to fully shut down the line driver by pulling the SHDN pin to within 0.4V of the SHDNREF potential. As shown in Figure 5 complete shutdown occurs in less than 10µs and, more importantly, complete recovery from the shut down state to full operation occurs in less than 2µs. The biasing circuitry in the LT1794 reacts very quickly to bring the amplifiers back to normal operation. VSHDN SHDNREF = 0V AMPLIFIER OUTPUT 1794 F05 W UU Figure 5. Shutdown and Recovery Timing 12V OR VLOGIC VLOGIC VC1 0V VC0 RSHDN SHDN RC0 2k RC1 SHDNREF 12V OR VLOGIC VLOGIC 0V VC RSHDN SHDN 2k RC SHDNREF 9 LT1794 APPLICATIO S I FOR ATIO Power Dissipation and Heat Management xDSL applications require the line driver to dissipate a significant amount of power and heat compared to other components in the system. The large peak to RMS variations of DMT and CAP ADSL signals require high supply voltages to prevent clipping, and the use of a step-up transformer to couple the signal to the telephone line can require high peak current levels. These requirements result in the driver package having to dissipate on the order of 1W. Several multiport cards inserted into a rack in an enclosed central office box can add up to many, many watts of power dissipation in an elevated ambient temperature environment. The LT1794 has built-in thermal shutdown circuitry that will protect the amplifiers if operated at excessive temperatures, however data transmissions will be seriously impaired. It is important in the design of the PCB and card enclosure to take measures to spread the heat developed in the driver away to the ambient environment to prevent thermal shutdown (which occurs when the junction temperature of the LT1794 exceeds 165°C). 12V 24.9k – SETS IQ PER AMPLIFIER = 10mA 20mA DC +IN + A 2VRMS SHDN 17.4Ω – 1k 110Ω 1000pF 110Ω 1:1.7 • • ILOAD = 57mARMS 1k – B –IN + –12V SHDNREF Figure 6. Estimating Line Driver Power Dissipation 10 U Estimating Line Driver Power Dissipation Figure 6 is a typical ADSL application shown for the purpose of estimating the power dissipation in the line driver. Due to the complex nature of the DMT signal, which looks very much like noise, it is easiest to use the RMS values of voltages and currents for estimating the driver power dissipation. The voltage and current levels shown for this example are for a full-rate ADSL signal driving 20dBm or 100mWRMS of power on to the 100Ω telephone line and assuming a 0.5dBm insertion loss in the transformer. The quiescent current for the LT1794 is set to 10mA per amplifier. The power dissipated in the LT1794 is a combination of the quiescent power and the output stage power when driving a signal. The two amplifiers are configured to place a differential signal on to the line. The Class AB output stage in each amplifier will simultaneously dissipate power in the upper power transistor of one amplifier, while sourcing current, and the lower power transistor of the other amplifier, while sinking current. The total device power dissipation is then: PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER) PD = (V+ – V–) • IQ + (V+ – VOUTARMS) • ILOAD + (V – – VOUTBRMS) • ILOAD 100Ω 3.16VRMS 17.4Ω 1794 F06 W UU –2VRMS LT1794 APPLICATIO S I FOR ATIO With no signal being placed on the line and the amplifier biased for 10mA per amplifier supply current, the quiescent driver power dissipation is: PDQ = 24V • 20mA = 480mW This can be reduced in many applications by operating with a lower quiescent current value. When driving a load, a large percentage of the amplifier quiescent current is diverted to the output stage and becomes part of the load current. Figure 7 illustrates the total amount of biasing current flowing between the + and – power supplies through the amplifiers as a function of load current. As much as 60% of the quiescent no load operating current is diverted to the load. At full power to the line the driver power dissipation is: PD(FULL) = 24V • 8mA + (12V – 2VRMS) • 57mARMS + [|–12V – (– 2VRMS)|] • 57mARMS PD(FULL) = 192mW + 570mW + 570mW = 1.332W The junction temperature of the driver must be kept less than the thermal shutdown temperature when processing a signal. The junction temperature is determined from the following expression: TJ = TAMBIENT (°C) + PD(FULL) (W) • θJA (°C/W) θJA is the thermal resistance from the junction of the LT1794 to the ambient air, which can be minimized by 25 20 TOTAL IQ (mA) 15 10 5 0 –240 –200 –160 –120 U heat-spreading PCB metal and airflow through the enclosure as required. For the example given, assuming a maximum ambient temperature of 85°C and keeping the junction temperature of the LT1794 to 140°C maximum, the maximum thermal resistance from junction to ambient required is: θJA(MAX) = 140°C – 85°C = 41.3°C / W 1.332W Heat Sinking Using PCB Metal Designing a thermal management system is often a trial and error process as it is never certain how effective it is until it is manufactured and evaluated. As a general rule, the more copper area of a PCB used for spreading heat away from the driver package, the more the operating junction temperature of the driver will be reduced. The limit to this approach however is the need for very compact circuit layout to allow more ports to be implemented on any given size PCB. Fortunately xDSL circuit boards use multiple layers of metal for interconnection of components. Areas of metal beneath the LT1794 connected together through several small 13 mil vias can be effective in conducting heat away from the driver package. The use of inner layer metal can free up top and bottom layer PCB area for external component placement. –80 –40 0 40 ILOAD (mA) 80 120 160 200 240 1794 F07 W UU Figure 7. IQ vs ILOAD 11 LT1794 APPLICATIO S I FOR ATIO Figure 8 shows four examples of PCB metal being used for heat spreading. These are provided as a reference for what might be expected when using different combinations of metal area on different layers of a PCB. These examples are with a 4-layer board using 1oz copper on each. The most effective layers for spreading heat are those closest to the LT1794 junction. The LT1794IFE is used because the small TSSOP package is most effective for very compact line driver designs. This package also has an exposed metal heat sinking pad on the bottom side which, when soldered to the PCB top layer metal, directly conducts heat away from the IC junction. Soldering the thermal pad to the TOPOLOGY TOP LAYER 2nd LAYER EXAMPLE A θJA = 40°C/W 13MIL VIAS USED: 30 EXAMPLE B θJA = 47°C/W 13MIL VIAS USED: 35 EXAMPLE C θJA = 51°C/W 13MIL VIAS USED: 32 EXAMPLE D θJA = 60°C/W 13MIL VIAS USED: 22 SCALE: 1 INCH Figure 8. Examples of PCB Metal Used for Heat Dissipation. LT1794IFE Driver Mounted on Top Layer. Heat Sink Pad Soldered to Top Layer Metal. External Components Mounted on Bottom Layer 12 U board produces a thermal resistance from junction to case, θJC, of approximately 3°C/W. Example A utilizes the most total metal area and provides the lowest thermal resistance. Example B however uses less metal on the top and bottom layers and still achieves reasonable thermal performance. For the most compact board design, inner layer metal can be used for heat dissipation. This is shown in examples C and D where minimum metal is used on the top and none on the bottom layers, only the 2nd and 3rd layers have a heat-conducting plane. Example C, with the larger metal areas performs better. 3rd LAYER BOTTOM LAYER VIA PATTERN 1794 F08 W UU LT1794 APPLICATIO S I FOR ATIO Similar results can be obtained with the LT1794CSW in the wide SO-20 package. With this package heat is conducted primarily through the V – pins, Pins 4 to 7 and 14 to 17; these pins should be soldered directly to the PCB metal plane. Important Note: The metal planes used for heat sinking the LT1794 are electrically connected to the negative supply potential of the driver, typically – 12V. These planes must be isolated from any other power planes used in the board design. When PCB cards containing multiple ports are inserted into a rack in an enclosed cabinet, it is often necessary to provide airflow through the cabinet and over the cards. This is also very effective in reducing the junction-toambient thermal resistance of each line driver. To a limit, this thermal resistance can be reduced approximately 5°C/W for every 100lfpm of laminar airflow. Layout and Passive Components With a gain bandwidth product of 200MHz the LT1794 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and a combination of RF-quality supply bypass capacitors (i.e., 0.1µF). As the primary applications have high drive current, use low ESR supply bypass capacitors (1µF to 10µF). The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause frequency peaking. In general, use feedback resistors of 1k or less. Compensation The LT1794 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. VI RC CC (OPTIONAL) RG 1794 F10 Figure 10. Compensation for Noninverting Gains Vi RF RG VI RC CC (OPTIONAL) VO –RF = RG VI VO (RC || RG) ≤ RF/9 1 < 5MHz 2πRCCC 1794 F09 RF RG CC Figure 9. Compensation for Inverting Gains Figure 11. Alternate Noninverting Compensation – + – + U Figure 9 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by R C and CC should be less than 5MHz to minimize peaking. Figure 10 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the network is bootstrapped. This network can also be placed between the inverting input and an AC ground. Another compensation scheme for noninverting circuits is shown in Figure 11. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of Figures 10 and 11 can be combined as shown in Figure 12. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies. RF VO =1+ VI RG VO (RC || RG) ≤ RF/9 1 < 5MHz 2πRCCC RF VO VO = 1 (LOW FREQUENCIES) VI R = 1 + F (HIGH FREQUENCIES) RG RG ≤ RF/9 1 < 5MHz 2πRGCC 1794 F11 W UU + – 13 LT1794 APPLICATIO S I FOR ATIO VI RC CC VO VI RF RG CBIG VO = 1 AT LOW FREQUENCIES VI R = 1 + F AT MEDIUM FREQUENCIES RG =1+ RF AT HIGH FREQUENCIES (RC || RG) 1794 F12 RG Figure 12. Combination Compensation Figure 13. Standard Cable/Line Back Termination VI VP RG Line Driving Back-Termination The standard method of cable or line back-termination is shown in Figure 13. The cable/line is terminated in its characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.). A back-termination resistor also equal to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. An alternate method of back-termination is shown in Figure 14. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor Figure 14. Back Termination Using Postive Feedback of n. To analyze this circuit, first ground the input. As RBT = RL/n, and assuming RP2>>RL we require that: VA = VO (1 – 1/n) to increase the effective value of RBT by n. VP = VO (1 – 1/n)/(1 + RF/RG) VO = VP (1 + RP2/RP1) Eliminating VP, we get the following: (1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n) For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 = 12.3. 14 – + In differential driver applications, as shown on the first page of this data sheet, it is recommended that the gain setting resistor be comprised of two equal value resistors connected to a good AC ground at high frequencies. This ensures that the feedback factor of each amplifier remains less than 0.1 at any frequency. The midpoint of the resistors can be directly connected by ground, with the resulting DC gain to the VOS of the amplifiers, or just bypassed to ground with a 1000pF or larger capacitor. RP1 – + U CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL RBT VO RL RF RBT = RL VO 1 = (1 + RF/RG) VI 2 1794 F13 W UU – + RP2 VA RBT RL RF RL n VO 1794 F14 FOR RBT = ( )( 1+ VO = VI 1 RP1 RF =1– n RG RP1 + RP2 RP2/(RP2 + RP1) ) () R 1+ F RG 1 + 1/n – RP1 RP2 + RP1 LT1794 APPLICATIO S I FOR ATIO Note that the overall gain is increased: RP2 / (RP2 + RP1) VO = VI (1+ 1/n) / (1+ RF /RG ) − RP1/(RP2 + RP1) [ ][ A simpler method of using positive feedback to reduce the back-termination is shown in Figure 15. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of –RF/RP from –VO to VA VA = VO (RF/RP) and assuming RP >> RL, we require VA = VO (1 – 1/n) solving RF/RP = 1 – 1/n So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: VO/VI = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)] Using positive feedback is often referred to as active termination. VI + – RF RG RP RP RG RF VA RBT VO RL FOR RBT = n 1 n= R 1– F RP VO = VI RR 1+ F + F RG RP 2 1– RL RL RBT –VA –VO 1794 F15 –VI Figure 15. Back Termination Using Differential Postive Feedback U W UU ] Figure 17 shows a full-rate ADSL line driver incorporating positive feedback to reduce the power lost in the back termination resistors by 40% yet still maintains the proper impedance match to the100Ω characteristic line impedance. This circuit also reduces the transformer turns ratio over the standard line driving approach resulting in lower peak current requirements. With lower current and less power loss in the back termination resistors, this driver dissipates only 1W of power, a 30% reduction. While the power savings of positive feedback are attractive there is one important system consideration to be addressed, received signal sensitivity. The signal received from the line is sensed across the back termination resistors. With positive feedback, signals are present on both ends of the RBT resistors, reducing the sensed amplitude. Extra gain may be required in the receive channel to compensate, or a completely separate receive path may be implemented through a separate line coupling transformer. A demo board, DC306A, is available for the LT1794. This demo board is a complete line driver with an LT1361 receiver included. It allows the evaluation of both standard and active termination approaches. It also has circuitry built in to evaluate the effects of operating with reduced supply current. Considerations for Fault Protection The basic line driver design, shown on the front page of this data sheet, presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. If left unchecked, the high DC current can heat the LT1794 to thermal shutdown. () RF RP + – 15 LT1794 APPLICATIO S I FOR ATIO Using DC blocking capacitors, as shown in Figure 16, to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbs®, varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also +IN • • LINE LOAD 1k 110Ω 1000pF 110Ω –IN Figure 16. Protecting the Driver Against Load Faults and Line Transients 16 U create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT1794 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs. TransZorb is a registered trademark of General Instruments, GSI W UU 12V 12V –12V 24.9k + 1/2 LT1794 SHDN 12.7Ω 0.1µF BAV99 – 1k 1:2 – 1/2 LT1794 12.7Ω SHDNREF 0.1µF + –12V BAV99 12V –12V 1794 F16 LT1794 SI PLIFIED SCHE ATIC V+ Q9 Q10 Q13 Q17 Q3 –IN Q1 R1 Q2 Q4 Q8 Q16 Q12 Q11 V– 1794 SS W W (one amplifier shown) Q7 Q6 Q5 C1 +IN C2 Q14 OUT Q15 Q18 17 LT1794 PACKAGE DESCRIPTIO 4.95 (.195) 6.60 ± 0.10 4.50 ± 0.10 SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0 ° – 8° 0.65 (.0256) BSC 0.09 – 0.20 (.0036 – .0079) 0.45 – 0.75 (.018 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 18 U Dimensions in inches (millimeters) unless otherwise noted. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 6.40 – 6.60* (.252 – .260) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 2.74 (.108) 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX 2.74 6.40 (.108) BSC 0.195 – 0.30 (.0077 – .0118) 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0203 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE LT1794 PACKAGE DESCRIPTIO 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. SW Package 20-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 NOTE 1 0.394 – 0.419 (10.007 – 10.643) 1 0.093 – 0.104 (2.362 – 2.642) 2 3 4 5 6 7 8 9 10 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.050 (1.270) BSC 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) S20 (WIDE) 1098 19 LT1794 TYPICAL APPLICATIO +IN • • 182Ω 1000pF 182Ω –IN RELATED PARTS PART NUMBER LT1361 LTC 1563-2 LT1795 LT1813 LT1886 ® DESCRIPTION Dual 50MHz, 800V/µs Op Amp Low Cost Active RC Lowpass Filter Dual 500mA, 50MHz Current Feedback Amplifier Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp Dual 200mA, 700MHz Op Amp 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U 12V 24.9k + 1/2 LT1794 SHDN 13.7Ω – 1k 1.65k 1.65k 1k *COILCRAFT X8502-A OR EQUIVALENT 1W DRIVER POWER DISSIPATION 1.15W POWER CONSUMPTION 1794 F17 1:1.2* 100Ω LINE – 1/2 LT1794 13.7Ω SHDNREF + –12V Figure 17. ADSL Line Driver Using Active Termination COMMENTS ±15V Operation, 1mV VOS, 1µA IB fC Up to 360kHz, Differential Operation, ± 5V Supplies Shutdown/Current Set Function, ADSL CO Driver Low Noise, Low Power Differential Receiver, 4mA/Amplifier 12V Operation, 7mA/Amplifier, ADSL Modem Line Driver 1794fs, sn1794 LT/TP 0501 4K • PRINTED IN THE USA © LINEAR TECHNOLOGY CORPORATION 2001