LT1871IMS-7-TRPBF

FEATURES n n n n n n n n n n n n n n LTC1871-7 High Input Voltage, Current Mode Boost, Flyback and SEPIC Controller DESCRIPTION The LTC®1871-7 is a current mode, boost, flyback and SEPIC controller optimized for driving 6V-rated MOSFETs in high voltage applications. The LTC1871-7 works equally well in low or high power applications and requires few components to provide a complete power supply solution. The switching frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchronized to an external clock using the MODE/SYNC pin. Burst Mode operation at light loads, a low minimum operating supply voltage of 6V and a low shutdown quiescent current of 10μA make the LTC1871-7 well suited for battery-operated systems. For applications requiring constant frequency operation, Burst Mode operation can be defeated using the MODE/SYNC pin. The LTC1871-7 is available in the 10-lead MSOP package. PARAMETER INTVCC INTVCC UV + INTVCC UV– LTC1871-7 7.0V 5.6V 4.6V LTC1871 5.2V 2.1V 1.9V Optimized for High Input Voltage Applications Wide Chip Supply Voltage Range: 6V to 36V Internal 7V Low Dropout Voltage Regulator Optimized for 6V-Rated MOSFETs Current Mode Control Provides Excellent Transient Response High Maximum Duty Cycle (92% Typ) ± 2% RUN Pin Threshold with 100mV Hysteresis ±1% Internal Voltage Reference Micropower Shutdown: IQ = 10μA Programmable Operating Frequency (50kHz to 1MHz) with One External Resistor Synchronizable to an External Clock Up to 1.3 × fOSC User-Controlled Pulse Skip or Burst Mode® Operation Output Overvoltage Protection Can be Used in a No RSENSE™ Mode for VDS < 36V Small 10-Lead MSOP Package APPLICATIONS n n n n Telecom Power Supplies 42V Automotive Systems 24V Industrial Controls IP Phone Power Supplies L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION VIN 36V TO 72V 604k 26.7k 2.2μF 100V X7R 3:1 100k D1 9.1V 2.2nF 3.4k FB 12.4k FREQ MODE/SYNC 110k 120k RUN ITH LTC1871-7 INTVCC GATE GND 4.7μF X5R 0.1μF X5R SENSE VIN Q1 FMMT625 10Ω D3 10BQ060 VOUT 12V 0.4A 47μF 16V X5R Figure 1. Small, Nonisolated 12V Flyback Telecom Housekeeping Supply 18717fc • T1 VP1-0076 M1 FDC2512 0.12Ω • D2 4148 18717 F01 1 LTC1871-7 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW RUN ITH FB FREQ MODE/ SYNC 1 2 3 4 5 10 9 8 7 6 SENSE VIN INTVCC GATE GND VIN Voltage ............................................... – 0.3V to 36V INTVCC Voltage............................................ –0.3V to 9V INTVCC Output Current .......................................... 50mA GATE Voltage ............................ –0.3V to VINTVCC + 0.3V ITH, FB Voltages ....................................... –0.3V to 2.7V RUN Voltage ............................................... –0.3V to 7V MODE/SYNC Voltage.................................... –0.3V to 9V FREQ Voltage ............................................ –0.3V to 1.5V SENSE Pin Voltage .................................... –0.3V to 36V Operating Temperature Range (Note 2) LTC1871E-7 ......................................... –40°C to 85°C LTC1871I-7 ........................................ –40°C to 125°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W ORDER INFORMATION LEAD FREE FINISH LT1871EMS-7#PBF LT1871IMS-7#PBF LEAD BASED FINISH LT1871EMS-7 LT1871IMS-7 TAPE AND REEL LT1871EMS-7#TRPBF LT1871IMS-7#TRPBF TAPE AND REEL LT1871EMS-7#TR LT1871IMS-7#TR PART MARKING LTG4 LTBTR PART MARKING LTG4 LTBTR PACKAGE DESCRIPTION 10-Lead Plastic MSOP 10-Lead Plastic MSOP PACKAGE DESCRIPTION 10-Lead Plastic MSOP 10-Lead Plastic MSOP TEMPERATURE RANGE –40°C to 85°C –40°C to 125°C TEMPERATURE RANGE –40°C to 85°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL VIN(MIN) IQ PARAMETER Minimum Input Voltage I-Grade (Note 2) Input Voltage Supply Current Continuous Mode (Note 4) VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V, I-Grade (Note 2) Burst Mode Operation, No Load VMODE/SYNC = 0V, VITH = 0.2V (Note 5) VMODE/SYNC = 0V, VITH = 0.2V (Note 5), I-Grade (Note 2) Shutdown Mode VRUN = 0V VRUN = 0V, I-Grade (Note 2) ● ● ● ● ELECTRICAL CHARACTERISTICS CONDITIONS MIN 6 6 TYP MAX UNITS V V Main Control Loop 550 600 280 280 12 12 1000 1100 500 600 25 25 μA μA μA μA μA μA 18717fc 2 LTC1871-7 ELECTRICAL CHARACTERISTICS SYMBOL VRUN+ VRUN– VRUN(HYST) IRUN VFB PARAMETER Rising RUN Input Threshold Voltage Falling RUN Input Threshold Voltage ● The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. CONDITIONS MIN 1.223 1.198 50 I-Grade (Note 2) RUN Input Current Feedback Voltage VITH = 0.2V (Note 5) VITH = 0.2V (Note 5), I-Grade (Note 2) ● ● ● TYP 1.348 1.248 100 100 5 1.230 MAX 1.273 1.298 150 175 60 1.242 1.248 1.255 60 0.02 0.02 UNITS V V V mV mV nA V V V nA %/V %/V % % RUN Pin Input Threshold Hysteresis 35 1.218 1.212 1.205 IFB ΔVFB ΔVIN ΔVFB ΔVITH ΔVFB(OV) gm VITH(BURST) VSENSE(MAX) ISENSE(ON) ISENSE(OFF) Oscillator fOSC FB Pin Input Current Line Regulation Load Regulation VITH = 0.2V (Note 5) 6V ≤ VIN ≤ 30V 6V ≤ VIN ≤ 30V, I-Grade (Note 2) VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5) VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5) I-Grade (Note 2) ● ● ● 18 0.002 0.002 –1 –1 2.5 –0.1 –0.1 6 600 0.3 120 ● ΔFB Pin, Overvoltage Lockout Error Amplifier Transconductance Burst Mode Operation ITH Pin Voltage Maximum Current Sense Input Threshold SENSE Pin Current (GATE High) SENSE Pin Current (GATE Low) Oscillator Frequency Oscillator Frequency Range VFB(OV) – VFB(NOM) in Percent ITH Pin Load = ±5μA (Note 5) Falling ITH Voltage (Note 5) Duty Cycle < 20% Duty Cycle < 20%, I-Grade (Note 2) VSENSE = 0V VSENSE = 30V RFREQ = 80k RFREQ = 80k, I-Grade (Note 2) I-Grade (Note 2) ● ● ● ● 10 % μmho V 150 35 0.1 180 200 70 5 350 350 1000 1000 mV mV μA μA kHz kHz kHz kHz % % 100 250 250 50 50 87 300 300 DMAX fSYNC/fOSC tSYNC(MIN) tSYNC(MAX) VIL(MODE) VIH(MODE) RMODE/SYNC VFREQ VINTVCC Maximum Duty Cycle I-Grade (Note 2) Recommended Maximum Synchronized Frequency Ratio MODE/SYNC Minimum Input Pulse Width MODE/SYNC Maximum Input Pulse Width Low Level MODE/SYNC Input Voltage I-Grade (Note 2) High Level MODE/SYNC Input Voltage I-Grade (Note 2) MODE/SYNC Input Pull-Down Resistance Nominal FREQ Pin Voltage INTVCC Regulator Output Voltage VIN = 8V VIN = 8V, I-Grade (Note 2) ● ● ● 92 92 1.25 1.25 25 0.8/fOSC 97 98.5 1.30 1.30 87 fOSC = 300kHz (Note 6) fOSC = 300kHz (Note 6), I-Grade (Note 2) VSYNC = 0V to 5V VSYNC = 0V to 5V ns ns 0.3 0.3 V V V V 1.2 1.2 50 0.62 6.5 6.5 7 7 7.5 7.5 kΩ V V V 18717fc Low Dropout Regulator 3 LTC1871-7 ELECTRICAL CHARACTERISTICS SYMBOL UVLO PARAMETER INTVCC Undervoltage Lockout Threshold The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. CONDITIONS Rising INTVCC Falling INTVCC UVLO Hysteresis 8V ≤ VIN ≤ 15V 15V ≤ VIN ≤ 30V 0 ≤ IINTVCC ≤ 20mA, VIN = 8V VIN = 6V, INTVCC Load = 20mA CL = 3300pF (Note 7) CL = 3300pF (Note 7) –2 MIN TYP 5.6 4.6 1.0 8 70 –0.2 280 17 8 100 100 25 200 MAX UNITS V V V mV mV % mV ns ns ΔVINTVCC ΔVIN1 ΔVINTVCC ΔVIN2 VLDO(LOAD) VDROPOUT GATE Driver tr tf INTVCC Regulator Line Regulation INTVCC Regulator Line Regulation INTVCC Load Regulation INTVCC Regulator Dropout Voltage GATE Driver Output Rise Time GATE Driver Output Fall Time Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC1871E-7 is guaranteed to meet performance specifications from 0°C to 70°C junction temperature. Specifications over the – 40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC1871I-7 is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 120°C/W) Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (QG • fOSC). See Applications Information. Note 5: The LTC1871-7 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 0V and 1.4V (the no load to full load operating voltage range for the ITH pin is 0.3V to 1.23V). Note 6: In a synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. Note 7: Rise and fall times are measured at 10% and 90% levels. TYPICAL PERFORMANCE CHARACTERISTICS FB Voltage vs Temp 1.25 1.231 FB Voltage Line Regulation 60 50 FB PIN CURRENT (nA) 25 30 35 FB Pin Current vs Temperature 1.24 FB VOLTAGE (V) FB VOLTAGE (V) 40 30 20 10 1.23 1.230 1.22 1.21 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G01 1.229 0 5 10 15 20 VIN (V) 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G03 18717 G02 18717fc 4 LTC1871-7 TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Mode IQ vs VIN 30 20 Shutdown Mode IQ vs Temperature VIN = 8V 600 500 Burst Mode IQ vs VIN SHUTDOWN MODE IQ (μA) SHUTDOWN MODE IQ (μA) 15 Burst Mode IQ (μA) 400 300 200 100 20 10 10 5 0 0 10 20 VIN (V) 30 40 18717 G04 0 –50 –25 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G05 0 10 20 VIN (V) 30 40 18717 G06 Burst Mode IQ vs Temperature 500 18 16 400 Burst Mode IQ (μA) 14 12 Dynamic IQ vs Frequency CL = 3300pF IQ(TOT) = 600μA + Qg • f 60 50 40 TIME (ns) Gate Drive Rise and Fall Time vs CL IQ (mA) 300 10 8 6 RISE TIME 30 20 FALL TIME 10 200 100 4 2 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G07 0 0 200 400 800 600 FREQUENCY (kHz) 1000 1200 0 0 2000 4000 6000 8000 CL (pF) 10000 12000 18717 G09 18717 G08 RUN Thresholds vs VIN 1.5 1.40 RUN Thresholds vs Temperature 1000 RT vs Frequency RUN THRESHOLDS (V) 1.4 RUN THRESHOLDS (V) 1.35 RT (kΩ) 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G11 1.30 100 1.3 1.25 1.2 0 10 20 VIN (V) 30 40 18717 G10 1.20 –50 –25 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 18717 G12 18717fc 5 LTC1871-7 TYPICAL PERFORMANCE CHARACTERISTICS Frequency vs Temperature 325 320 GATE FREQUENCY (kHz) 155 SENSE PIN CURRENT (μA) 315 310 305 300 295 290 285 280 275 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G13 Maximum Sense Threshold vs Temperature 160 MAX SENSE THRESHOLD (mV) 35 SENSE Pin Current vs Temperature GATE HIGH VSENSE = 0V 150 30 145 140 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G14 25 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 18717 G15 INTVCC Load Regulation VIN = 8V 7.0 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) 7.1 7.2 INTVCC Line Regulation 500 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 INTVCC Dropout Voltage vs Current, Temperature 150°C 125°C 75°C 25°C 6.9 7.0 0°C –50°C 6.8 0 10 20 30 40 50 60 INTVCC LOAD (mA) 70 80 6.9 0 5 10 15 20 25 VIN (V) 30 35 40 0 0 5 10 15 INTVCC LOAD (mA) 20 18717 G18 18717 G16 18717 G17 PIN FUNCTIONS RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and programming the start-up threshold for the converter. The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the VIN supply current is kept to a low value (typ 10μA). The Absolute Maximum Rating for the voltage on this pin is 7V. ITH (Pin 2): Error Amplifier Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V. FB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulaton is 1.230V. FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.6V. 18717fc 6 LTC1871-7 PIN FUNCTIONS MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operation is enabled. If the MODE/SYNC pin is connected to INTVCC, or if an external logic-level synchronization signal is applied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode. GND (Pin 6): Ground Pin. GATE (Pin 7): Gate Driver Output. INTVCC (Pin 8): The Internal 7V Regulator Output. The gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum of 4.7μF low ESR tantalum or ceramic capacitor. This 7V regulator has an undervoltage lockout circuit with 5.6V and 4.6V rising and falling thresholds, respectively. VIN (Pin 9): Main Supply Pin. Must be closely decoupled to ground. SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to a resistor in the source of the power MOSFET. Alternatively, the SENSE pin may be connected to the drain of the power MOSFET, in applications where the maximum VDS is less than 36V. Internal leading edge blanking is provided for both sensing methods. BLOCK DIAGRAM RUN SLOPE COMPENSATION FREQ 4 0.6V MODE/SYNC 5 85mV 1.230V IOSC PWM LATCH LOGIC OV 50k S Q R BURST COMPARATOR CURRENT COMPARATOR C1 GND V-TO-I OSC INTVCC GATE 7 BIAS AND START-UP CONTROL + C2 1 – 1.248V VIN 9 0.30V FB 3 EA gm 1.230V ITH 2 INTVCC 8 7V LDO UV 1.230V + 5.6V UP 4.6V DOWN TO START-UP CONTROL + – + + – – – + SENSE + – 10 V-TO-I ILOOP SLOPE 1.230V GND BIAS VREF 6 18717 BD RLOOP VIN 18717fc 7 LTC1871-7 OPERATION Main Control Loop The LTC1871-7 is a constant frequency, current mode controller for DC/DC boost, SEPIC and flyback converter applications. With the LTC1871-7 the current control loop can be closed by sensing the voltage drop either across the power MOSFET switch or across a discrete sense resistor, as shown in Figure 2. L VIN VIN SENSE VSW GATE GND GND D VOUT + COUT The nominal operating frequency of the LTC1871-7 is programmed using a resistor from the FREQ pin to ground and can be controlled over a 50kHz to 1000kHz range. In addition, the internal oscillator can be synchronized to an external clock applied to the MODE/SYNC pin and can be locked to a frequency between 100% and 130% of its nominal value. When the MODE/SYNC pin is left open, it is pulled low by an internal 50k resistor and Burst Mode operation is enabled. If this pin is taken above 2V or an external clock is applied, Burst Mode operation is disabled and the IC operates in continuous mode. With no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. The RUN pin controls whether the IC is enabled or is in a low current shutdown state. A micropower 1.248V reference and comparator C2 allow the user to program the supply voltage at which the IC turns on and off (comparator C2 has 100mV of hysteresis for noise immunity). With the RUN pin below 1.248V, the chip is off and the input supply current is typically only 10μA. An overvoltage comparator OV senses when the FB pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main RS latch. Because this RS latch is reset-dominant, the power MOSFET is actively held off for the duration of an output overvoltage condition. The LTC1871-7 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET, as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36V). By connecting the SENSE pin to a resistor in the source of the power MOSFET, the user is able to program output voltages significantly greater than 36V. Programming the Operating Mode For applications where maximizing the efficiency at very light loads (e.g., 36V Figure 2. Using the SENSE Pin On the LTC1871-7 For circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. The divided-down output voltage is compared to an internal 1.230V reference by the error amplifier EA, which outputs an error signal at the ITH pin. The voltage on the ITH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage relative to the reference voltage causes the ITH pin to rise, which causes the current comparator C1 to trip at a higher peak inductor current value. The average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. 8 LTC1871-7 OPERATION In applications where fixed frequency operation is more critical than low current efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the MODE/SYNC pin should be connected to the INTVCC pin. This allows discontinuous conduction mode (DCM) operation down to near the limit defined by the chip’s minimum on-time (about 175ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Figures 3 and 4 show the light load switching waveforms for Burst Mode and pulse-skip mode operation for the converter in Figure 1. Burst Mode Operation Burst Mode operation is selected by leaving the MODE/ SYNC pin unconnected or by connecting it to ground. In normal operation, the range on the ITH pin corresponding to no load to full load is 0.30V to 1.2V. In Burst Mode operation, if the error amplifier EA drives the ITH voltage below 0.525V, the buffered ITH input to the current comparator C1 will be clamped at 0.525V (which corresponds to 25% of maximum load current). The inductor current peak is then held at approximately 30mV divided by the power MOSFET RDS(ON). If the ITH pin drops below 0.30V, the Burst Mode comparator B1 will turn off the power MOSFET and scale back the quiescent current of the IC to 250μA (sleep mode). In this condition, the load current will be supplied by the output capacitor until the ITH voltage rises above the 50mV hysteresis of the burst comparator. At light loads, short bursts of switching (where the average MODE/SYNC = 0V (Burst Mode OPERATION) VOUT 50mV/DIV inductor current is 20% of its maximum value) followed by long periods of sleep will be observed, thereby greatly improving converter efficiency. Oscilloscope waveforms illustrating Burst Mode operation are shown in Figure 3. Pulse-Skip Mode Operation With the MODE/SYNC pin tied to a DC voltage above 2V, Burst Mode operation is disabled. The internal, 0.525V buffered ITH burst clamp is removed, allowing the ITH pin to directly control the current comparator from no load to full load. With no load, the ITH pin is driven below 0.30V, the power MOSFET is turned off and sleep mode is invoked. Oscilloscope waveforms illustrating this mode of operation are shown in Figure 4. When an external clock signal drives the MODE/SYNC pin at a rate faster than the chip’s internal oscillator, the oscillator will synchronize to it. In this synchronized mode, Burst Mode operation is disabled. The constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads. When the oscillator’s internal logic circuitry detects a synchronizing signal on the MODE/SYNC pin, the internal oscillator ramp is terminated early and the slope compensation is increased by approximately 30%. As a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an MODE/SYNC = INTVCC (PULSE SKIP MODE) VOUT 50mV/DIV IL 5A/DIV IL 5A/DIV 18717 F03 10μs/DIV 2μs/DIV 18717 F04 Figure 3. LTC1871-7 Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current Figure 4. LTC1871-7 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTVCC) 18717fc 9 LTC1871-7 OPERATION external frequency (above 1.3fO) can result in inadequate slope compensation and possible subharmonic oscillation (or jitter). The external clock signal must exceed 2V for at least 25ns, and should have a maximum duty cycle of 80%, as shown in Figure 5. The MOSFET turn on will synchronize to the rising edge of the external clock signal. Programming the Operating Frequency The choice of operating frequency and inductor value is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET and diode switching losses. However, lower frequency operation requires more inductance for a given amount of load current. The LTC1871-7 uses a constant frequency architecture that can be programmed over a 50kHz to 1000kHz range with a single external resistor from the FREQ pin to ground, as shown in Figure 1. The nominal voltage on the FREQ pin is 0.6V, and the current that flows into the FREQ pin is used to charge and discharge an internal oscillator capacitor. A graph for selecting the value of RT for a given operating frequency is shown in Figure 6. INTVCC Regulator Bypassing and Operation An internal, P-channel low dropout voltage regulator produces the 7V supply which powers the gate driver and 2V TO 7V MODE/ SYNC tMIN = 25ns 0.8T T T = 1/fO RT (kΩ) 18717 F05 logic circuitry within the LTC1871-7, as shown in Figure 7. The INTVCC regulator can supply up to 50mA and must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7μF tantalum or ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. The LTC1871-7 contains an undervoltage lockout circuit which protects the external MOSFET from switching at low gate-to-source voltages. This undervoltage circuit senses the INTVCC voltage and has a 5.6V rising threshold and a 4.6V falling threshold. For input voltages that don’t exceed 8V (the absolute maximum rating for INTVCC is 9V), the internal low dropout regulator in the LTC1871-7 is redundant and the INTVCC pin can be shorted directly to the VIN pin. With the INTVCC pin shorted to VIN, however, the divider that programs the regulated INTVCC voltage will draw 14μA of current from the input supply, even in shutdown mode. For applications that require the lowest shutdown mode input supply current, do not connect the INTVCC pin to VIN. Regardless of whether the INTVCC pin is shorted to VIN or not, it is always necessary to have the driver circuitry bypassed with a 4.7μF ceramic capacitor to ground immediately adjacent to the INTVCC and GND pins. In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET. As a result, high input voltage applications in which a large power MOSFET is being driven at high frequencies 1000 GATE D = 40% 100 IL 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 18717 F06 Figure 5. MODE/SYNC Clock Input and Switching Waveforms for Synchronized Operation Figure 6. Timing Resistor (RT) Value 18717fc 10 LTC1871-7 OPERATION VIN INPUT SUPPLY 6V TO 30V 1.230V R2 Figure 7. Bypassing the LDO Regulator and Gate Driver Supply can cause the LTC1871-7 to exceed its maximum junction temperature rating. The junction temperature can be estimated using the following equations: IQ(TOT) ≈ IQ + f • QG PIC = VIN • (IQ + f • QG) TJ = TA + PIC • RTH(JA) The total quiescent current IQ(TOT) consists of the static supply current (IQ) and the current required to charge and discharge the gate of the power MOSFET. The 10-pin MSOP package has a thermal resistance of RTH(JA) = 120°C/W. As an example, consider a power supply with VIN =10V. The switching frequency is 200kHz, and the maximum ambient temperature is 70°C. The power MOSFET chosen is the FDS3670(Fairchild), which has a maximum RDS(ON) of 35mΩ (at room temperature) and a maximum total gate charge of 80nC (the temperature coefficient of the gate charge is low). IQ(TOT) = 600μA + 80nC • 200kHz = 16.6mA PIC = 10V • 16.6mA = 166mW TJ = 70°C + 120°C/W • 166mW = 89.9°C TJRISE = 19.9°C + R1 7V INTVCC CVCC 4.7μF X5R LOGIC DRIVER GATE GND 18717 F07 – P-CH CIN M1 6V-RATED POWER MOSFET GND PLACE AS CLOSE AS POSSIBLE TO DEVICE PINS This demonstrates how significant the gate charge current can be when compared to the static quiescent current in the IC. To prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high VIN. A tradeoff between the operating frequency and the size of the power MOSFET may need to be made in order to maintain a reliable IC junction temperature. Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their latest-and-greatest low QG, low RDS(ON) devices. Power MOSFET manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. Output Voltage Programming The output voltage is set by a resistor divider according to the following formula: VO = 1.230V • 1+ R2 R1 The external resistor divider is connected to the output as shown in Figure 1, allowing remote voltage sensing. 18717fc 11 LTC1871-7 OPERATION The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FB pin during normal operation is less than 1% (this translates to a maximum value of R1 of about 250k). Programming Turn-On and Turn-Off Thresholds with the RUN Pin The LTC1871-7 contains an independent, micropower voltage reference and comparator detection circuit that remains active even when the device is shut down, as shown in Figure 8. This allows users to accurately program an input voltage at which the converter will turn on and off. The falling threshold voltage on the RUN pin is equal to the internal reference voltage of 1.248V. The comparator has 100mV of hysteresis to increase noise immunity. The turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: R2 VIN(OFF) = 1.248V • 1+ R1 VIN(ON) = 1.348V • 1+ R2 R1 The resistor R1 is typically chosen to be less than 1M. For applications where the RUN pin is only to be used as a logic input, the user should be aware of the 7V Absolute Maximum Rating for this pin! The RUN pin can be connected to the input voltage through an external 1M resistor, as shown in Figure 8c, for “always on” operation. + R2 VIN RUN COMPARATOR BIAS AND START-UP CONTROL RUN 6V INPUT SUPPLY + – OPTIONAL FILTER CAPACITOR R1 1.248V μPOWER REFERENCE GND 18717 F8a – Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin + R2 1M RUN COMPARATOR RUN 6V EXTERNAL LOGIC CONTROL 1.248V INPUT SUPPLY VIN RUN COMPARATOR RUN 6V + – + – 18717 F08b – GND 1.248V 18717 F08c Figure 8b. On/Off Control Using External Logic Figure 8c. External Pull-Up Resistor On RUN Pin for “Always On” Operation 18717fc 12 LTC1871-7 APPLICATIONS INFORMATION Application Circuits A basic LTC1871-7 application circuit is shown in Figure 9. External component selection is driven by the characteristics of the load and the input supply. The first topology to be analyzed will be the boost converter, followed by SEPIC (single-ended primary inductance converter). Boost Converter: Duty Cycle Considerations For a boost converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: D= VO + VD – VIN VO + VD The maximum duty cycle capability of the LTC1871-7 is typically 92%. This allows the user to obtain high output voltages from low input supply voltages. Boost Converter: The Peak and Average Input Currents The control circuit in the LTC1871-7 is measuring the input current typically using a sense resistor in the MOSFET source, so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: IO(MAX) IIN(MAX) = 1– DMAX The peak input current is: IIN(PEAK) = 1+ 2 • IO(MAX) 1– DMAX where VD is the forward voltage of the boost diode. For converters where the input voltage is close to the output voltage, the duty cycle is low and for converters that develop a high output voltage from a low voltage input supply, the duty cycle is high. The maximum output voltage for a boost converter operating in CCM is: VO(MAX) = (1– DMAX ) VIN(MIN) – VD The maximum duty cycle, DMAX, should be calculated at minimum VIN. R3 1M 1 2 RC 24k CC1 2.2nF CC2 100pF RT 100k 1% f = 250kHz SENSE VIN LTC1871-7 10 9 CIN2 10μF 50V X5R ×2 + L1 6.8μH CIN1* 560μF 50V VIN 8V TO 28V RUN ITH D1 VOUT 42V 1.5A COUT2 10μF 50V X5R ×2 3 4 5 FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 CVCC 4.7μF X5R M1 RSENSE 0.005Ω 1W + COUT1 68μF 100V ×2 R1 12.4k 1% CIN1: CIN2: COUT1: COUT2: R2 412k 1% GND 18717 F09 SANYO 50MV560AXL (*RECOMMENDED FOR LAB EVALUATION FOR SUPPLY LEAD LENGTHS GREATER THAN A FEW INCHES) TDK C5750X5R1H106M SANYO 100CV68FS TDK C5750X5R1H106M D1: DIODES INC B360B L1: COOPER DR127-6R8 M1: SILICONIX/VISHAY Si7370DP Figure 9. A High Efficiency 42V, 1.5A Automotive Boost Converter 18717fc 13 LTC1871-7 APPLICATIONS INFORMATION Boost Converter: Ripple Current ΔIL and the ‘χ’ Factor The constant ‘χ’ in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30, and the peak current is 15% greater than the average. For a current mode boost regulator operating in CCM, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. For the LTC1871-7, this ramp compensation is internal. Having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. If too large an inductor is used, the resulting current ramp (ΔIL) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). If too small an inductor is used, but the converter is still operating in CCM (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. To ensure good current mode gain and avoid subharmonic oscillation, it is recommended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. For example, if the maximum average input current is 1A, choose a ΔIL between 0.2A and 0.4A, and a value ‘χ’ between 0.2 and 0.4. Boost Converter: Inductor Selection Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value can be determined using the following equation: VIN(MIN) L= • DMAX IL • f where: IL = • IO(MAX) 1– DMAX applications requiring a step-up converter that is shortcircuit protected, please refer to the applications section covering SEPIC converters. The minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: IL(SAT) 1+ 2 • IO(MAX) 1– DMAX The saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. Boost Converter: Operating in Discontinuous Mode Discontinuous mode operation occurs when the load current is low enough to allow the inductor current to run out during the off-time of the switch, as shown in Figure 10. Once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1MHz to 10MHz. If the off-time is long enough, the drain voltage will settle to the input voltage. Depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power MOSFET to go below ground where it is clamped by the body diode. This ringing is not harmful to the IC and it has not been shown to contribute significantly to EMI. Any attempt to damp it with a snubber will degrade the efficiency. OUTPUT VOLTAGE 200mV/DIV INDUCTOR CURRENT 1A/DIV MOSFET DRAIN VOLTAGE 20V/DIV 1μs/DIV 18717 F10 Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For Figure 10. Discontinuous Mode Waveforms for the Converter Shown in Figure 9 18717fc 14 LTC1871-7 APPLICATIONS INFORMATION Sense Resistor Selection During the switch on-time, the control circuit limits the maximum voltage drop across the sense resistor to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RSENSE. The relationship between the maximum load current, duty cycle and the sense resistor RSENSE is: 1– DMAX RSENSE VSENSE(MAX) • •I 1+ 2 O(MAX ) The VSENSE(MAX) term is typically 150mV at low duty cycle, and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 11. It is worth noting that the 1 – DMAX relationship between IO(MAX) and RSENSE can cause boost converters with a wide input range to experience a dramatic range of maximum input and output current. This should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply. MAXIMUM CURRENT SENSE VOLTAGE (mV) 200 The gate drive voltage is set by the 7V INTVCC low drop regulator. Consequently, 6V rated MOSFETs are required in most high voltage LTC1871-7 applications. Pay close attention to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. The switch node can ring during the turn-off of the MOSFET due to layout parasitics. Check the switching waveforms of the MOSFET directly across the drain and source terminals using the actual PC board layout (not just on a lab breadboard!) for excessive ringing. Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its RDS(ON)). As a result, some iterative calculation is normally required to determine a reasonably accurate value. Care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. The power dissipated by the MOSFET in a boost converter is: PFET = IO(MAX) 1– D 2 150 100 50 • RDS(ON) • D • IO(MAX) T 0 0 0.2 0.5 0.4 DUTY CYCLE 0.8 1.0 18717 F11 + k • VO2 • (1– D) • CRSS • f Figure 11. Maximum SENSE Threshold Votlage vs Duty Cycle Boost Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gateto-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The first term in the equation above represents the I2R losses in the device, and the second term, the switching losses. The constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The ρT term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/°C. Figure 12 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. 18717fc 15 LTC1871-7 APPLICATIONS INFORMATION 2.0 ρT NORMALIZED ON RESISTANCE 1.5 The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. Remember to keep the diode lead lengths short and to observe proper switch-node layout (see Board Layout Checklist) to avoid excessive ringing and increased dissipation. Boost Converter: Output Capacitor Selection 1.0 0.5 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 18717 F12 Figure 12. Normalized RDS(ON) vs Temperature From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(CA)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. The output diode in a boost converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage. The average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. ID(PEAK) = IL(PEAK) = 1+ 2 • IO(MAX) 1– DMAX Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform are illustrated in Figure 13 for a typical boost converter. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging ΔV. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging ΔV. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: ESRCOUT where: IIN(PEAK)= 1+ 2 • IO(MAX) 1– DMAX 0.01• VO IIN(PEAK ) The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RTH(JA) For the bulk C component, which also contributes 1% to the total ripple: IO(MAX) COUT 0.01• VO • f 18717fc 16 LTC1871-7 APPLICATIONS INFORMATION For some designs it may be possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 13. The RMS output capacitor ripple current is: IRMS(COUT) IO(MAX) • VO – VIN(MIN) VIN(MIN) L D VOUT VIN SW COUT RL 13a. Circuit Diagram IL IIN 13b. Inductor and Input Currents ISW tON 13c. Switch Current ID tOFF IO 13d. Diode and Output Currents ΔVCOUT VOUT (AC) RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 18717 F13 ΔVESR Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. 13e. Output Voltage Ripple Waveform Figure 13. Switching Waveforms for a Boost Converter Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous (see Figure 13b). The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10μF to 100μF A low ESR . capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: VIN(MIN) IRMS(CIN) = 0.3 • • DMAX L•f 18717fc 17 LTC1871-7 APPLICATIONS INFORMATION Table 1. Recommended Component Manufacturers VENDOR AVX BH Electronics Coilcraft Coiltronics Diodes, Inc Fairchild General Semiconductor International Rectifier IRC Kemet Magnetics Inc Microsemi Murata-Erie Nichicon On Semiconductor Panasonic Sanyo Sumida Taiyo Yuden TDK Thermalloy Tokin Toko United Chemicon Vishay/Dale Vishay/Siliconix Vishay/Sprague Zetex COMPONENTS Capacitors Inductors, Transformers Inductors Inductors Diodes MOSFETs Diodes MOSFETs, Diodes Sense Resistors Tantalum Capacitors Toroid Cores Diodes Inductors, Capacitors Capacitors Diodes Capacitors Capacitors Inductors Capacitors Capacitors, Inductors Heat Sinks Capacitors Inductors Capacitors Resistors MOSFETs Capacitors Small-Signal Discretes TELEPHONE (207) 282-5111 (952) 894-9590 (847) 639-6400 (407) 241-7876 (805) 446-4800 (408) 822-2126 (516) 847-3000 (310) 322-3331 (361) 992-7900 (408) 986-0424 (800) 245-3984 (617) 926-0404 (770) 436-1300 (847) 843-7500 (602) 244-6600 (714) 373-7334 (619) 661-6835 (847) 956-0667 (408) 573-4150 (562) 596-1212 (972) 243-4321 (408) 432-8020 (847) 699-3430 (847) 696-2000 (605) 665-9301 (800) 554-5565 (207) 324-4140 (631) 543-7100 WEB ADDRESS avxcorp.com bhelectronics.com coilcraft.com coiltronics.com diodes.com fairchildsemi.com generalsemiconductor.com irf.com irctt.com kemet.com mag-inc.com microsemi.com murata.co.jp nichicon.com onsemi.com panasonic.com sanyo.co.jp sumida.com t-yuden.com component.tdk.com aavidthermalloy.com nec-tokinamerica.com tokoam.com chemi-com.com vishay.com vishay.com vishay.com zetex.com Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! Burst Mode Operation and Considerations The choice of sense resistor and inductor value also determines the load current at which the LTC1871-7 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately: 30mV IBURST(PEAK) = RSENSE which represents about 20% of the maximum 150mV SENSE pin voltage. The corresponding average current depends upon the amount of ripple current. Lower inductor values (higher ΔIL) will reduce the load current at which Burst Mode operations begins, since it is the peak current that is being clamped. The output voltage ripple can increase during Burst Mode operation if ΔIL is substantially less than IBURST. This can occur if the input voltage is very low or if a very large inductor is chosen. At high duty cycles, a skipped cycle causes the inductor current to quickly decay to zero. However, because ΔIL is small, it takes multiple cycles for the current to ramp back up to IBURST(PEAK). 18717fc 18 LTC1871-7 APPLICATIONS INFORMATION During this inductor charging interval, the output capacitor must supply the load current and a significant droop in the output voltage can occur. Generally, it is a good idea to choose a value of inductor ΔIL between 25% and 40% of IIN(MAX). The alternative is to either increase the value of the output capacitor or disable Burst Mode operation using the MODE/SYNC pin. Burst Mode operation can be defeated by connecting the MODE/SYNC pin to a high logic-level voltage (either with a control input or by connecting this pin to INTVCC). In this mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduction mode (CCM) at full load, down into deep discontinuous conduction mode (DCM) at light load. Prior to skipping pulses at very light load (i.e., 1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with CO, causing a nearly instantaneous drop in VO. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. Boost Converter Design Example The design example given here will be for the circuit shown in Figure 9. The input voltage is 8V to 28V, and the output is 42V at a maximum load current of 1.5A. 1. The maximum duty cycle is: D= VO + VD – VIN 42 + 0.4 – 8 = = 81.1% 42 + 0.4 VO + VD 1.5A IOUT 0.5A/DIV 0.5A 2. Pulse-skip operation is chosen so the MODE/SYNC pin is shorted to INTVCC. 3. The operating frequency is chosen to be 250kHz to reduce the size of the inductor. From Figure 5, the resistor from the FREQ pin to ground is 100k. 4. An inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: IO(MAX) IIN(PEAK) = 1+ • 2 1– DMAX 1.5 = 1.2 • = 9.47A 1– 0. 81 The inductor ripple current is: IO(MAX) 1.5 IL = • = 0.4 • = 3.2A 1– DMAX 1– 0.81 18717 F14b 250μs/DIV 18717 F14a Figure 14a. Load Transient Response for the Circuit in Figure 9 VIN = 28V VOUT 500mV/DIV 1.5A IOUT 0.5A/DIV 0.5A 250μs/DIV Figure 14b. Load Transient Response for the Circuit in Figure 9 And so the inductor value is: VIN(MIN) L= • DMAX IL • f 8 = • 0.81= 8.1μH 3.2 • 250k 18717fc 20 LTC1871-7 APPLICATIONS INFORMATION The component chosen is a 6.8μH inductor made by Cooper (part number DR127-6R8) which has a saturation current of greater than 13.3A. 5. Because the duty cycle is 81%, the maximum SENSE pin threshold voltage is reduced from its low duty cycle typical value of 150mV to approximately 115mV. In addition, we need to apply a worst-case derating factor to this SENSE threshold to account for manufacturing tolerances within the IC. Finally, the nominal current limit value should exceed the maximum load current by some safety margin (in this case 50%). Therefore, the value of the sense resistor is: 1– DMAX RSENSE = 0.8 • VSENSE(MAX) • 0.4 • 1.5 •IO(MAX ) 1+ 2 1– 0.81 = 6.5m = 0.8 • 0.115 • 1.2 • 1.5 • 1.5 A 1W, 5mΩ resistor is used in this design. 6. The MOSFET chosen is a Vishay/Siliconix Si7370DP , which has a BVDSS of greater than 60V and an RDS(ON) of less than 13mΩ at a VGS of 6V. 7. The diode for this design must handle a maximum DC output current of 1.5A and be rated for a minimum reverse voltage of VOUT, or 42V. A 3A, 60V diode from Diodes Inc. (B360B) is chosen. 8. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 50mV, the bulk C needs to be greater than: IOUT(MAX) 1.5 COUT = = 14μF 0.01• VOUT • f 0.01• 42 • 250k The RMS ripple current rating for this capacitor needs to exceed: VO – VIN(MIN) IRMS(COUT) IO(MAX) • = VIN(MIN) 1.5 • 42 – 8 = 3.09A 8 To satisfy the low ESR, high frequency decoupling requirements, two 10μF 50V, X5R ceramic capacitors , are used (TDK part number C5750X5R1H106M). In parallel with these, two 68μF 100V electrolytic ca, pacitors are used (Sanyo part number 100CV68FS). Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents flow. 9. The choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup a 560μF 50V Sanyo electrolytic (50MV560AXL), in , parallel with two 10μF 100V TDK ceramic capacitors , (C5750X5R1H106M) is required (the input and return lead lengths are kept to a few inches, but the peak input current is close to 10A!). As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. VOUT 1V/DIV IL 2A/DIV MOSFET DRAIN VOLTAGE 20V/DIV VIN = 8V IOUT = 0.5A VOUT = 42V D = 81% 1μs/DIV 18717 F15 Figure 15. Switching Waveforms for the Converter in Figure 9 at Minimum VIN (8V) 18717fc 21 LTC1871-7 APPLICATIONS INFORMATION 100 VOUT 1V/DIV 95 IL 1A/DIV EFFICIENCY (%) VIN = 8V VIN = 12V VIN = 28V 90 85 MOSFET DRAIN VOLTAGE 20V/DIV VIN = 28V IOUT = 0.5A VOUT = 42V D = 27% 1μs/DIV 18717 F16 80 75 0.001 0.01 0.1 ILOAD (mA) 1 10 18717 F17 Figure 16. Switching Waveforms for the Converter in Figure 9 at Maximum VIN (28V) Figure 17. Efficiency vs Load Current and Input Voltage for the Converter in Figure 9 PC Board Layout Checklist 1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC1871-7 should be connected directly to 1) the negative terminal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to Pin 6. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and inductance. 2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground plane is to be used for high DC currents, choose a path away from the small-signal components. 3. Place the CVCC capacitor immediately adjacent to the INTVCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. A low ESR and ESL 4.7μF ceramic capacitor works well here. 4. The high di/dt loop from the bottom terminal of the output capacitor, through the power MOSFET, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive ringing. Excess inductance can cause increased stress on the power MOSFET and increase HF noise on the output. If low ESR ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum. 5. Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power MOSFET. Not all MOSFETs are created equal (some are more equal than others). 6. Place the small-signal components away from high frequency switching nodes. In the layout shown in Figure 18, all of the small-signal components have been placed on one side of the IC and all of the power components have been placed on the other. This also allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the INTVCC decoupling capacitor) and small-signal currents flow in the other direction. 18717fc 22 LTC1871-7 APPLICATIONS INFORMATION 7. Minimize the capacitance between the SENSE pin trace and any high frequency switching nodes. The LTC1871-7 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications. 8. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC1871-7 in order to keep the high impedance FB node short. VIN L1 R3 RC R2 R1 RT CC R4 PIN 1 LTC1871-7 CIN J1 JUMPER CVCC RS M1 SWITCH NODE IS ALSO THE HEAT SPREADER FOR L1, M1, D1 PSEUDO-KELVIN SIGNAL GROUND CONNECTION COUT COUT D1 VIAS TO GROUND PLANE TRUE REMOTE OUTPUT SENSING VOUT 1871 F18 Figure 18. LTC1871-7 Boost Converter Suggested Layout VIN R3 1 RC 2 R4 10 9 J1 L1 SENSE VIN SWITCH NODE CC RUN ITH LTC1871-7 R1 R2 RT 3 4 5 FB FREQ MODE/ SYNC INTVCC GATE GND 8 7 6 CVCC M1 D1 + CIN RS GND BOLD LINES INDICATE HIGH CURRENT PATHS Figure 19. LTC1871-7 Boost Converter Layout Diagram 18717fc + PSEUDO-KELVIN GROUND CONNECTION COUT VOUT 18717 F19 23 LTC1871-7 APPLICATIONS INFORMATION 9. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC1871-7 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the LTC1871-7. A few inches of PC trace or wire (L ≈ 100nH) between the CIN of the LTC1871-7 and the actual source VIN should be sufficient to prevent current sharing problems. SEPIC Converter Applications The LTC1871-7 is also well suited to SEPIC (single-ended primary inductance converter) converter applications. The SEPIC converter shown in Figure 20 uses two inductors. The advantage of the SEPIC converter is the input voltage may be higher or lower than the output voltage, and the output is short-circuit protected. The first inductor, L1, together with the main switch, resembles a boost converter. The second inductor, L2, together with the output diode D1, resembles a flyback or buck-boost converter. The two inductors L1 and L2 can be independent but can also be wound on the same core since identical voltages are applied to L1 and L2 throughout the switching cycle. By making L1 = L2 and winding them on the same core the input ripple is reduced along with cost L1 C1 D1 and size. All of the SEPIC applications information that follows assumes L1 = L2 = L. SEPIC Converter: Duty Cycle Considerations For a SEPIC converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: VO + VD D= VIN + VO + VD where VD is the forward voltage of the diode. For converters where the input voltage is close to the output voltage the duty cycle is near 50%. IIN SW ON SW OFF IL1 21a. Input Inductor Current IL2 IO 21b. Output Inductor Current IIN IC1 IO VIN SW 20a. SEPIC Topology VIN VIN 20b. Current Flow During Switch On-Time VIN D1 VIN 20c. Current Flow During Switch Off-Time Figure 20. SEPIC Topolgy and Current Flow 24 + + • + + • + L2 COUT + • VOUT + • 21c. DC Coupling Capacitor Current RL ID1 IO VOUT + • RL 21d. Diode Current VOUT (AC) ΔVCOUT 18717 F21 VOUT + • 18717 F20 ΔVESR RL RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 21e. Output Ripple Voltage Figure 21. SEPIC Converter Switching Waveforms 18717fc LTC1871-7 APPLICATIONS INFORMATION The maximum output voltage for a SEPIC converter is: D 1 VO(MAX) = ( VIN + VD ) MAX – VD 1– DMAX 1– DMAX The maximum duty cycle of the LTC1871-7 is typically 92%. SEPIC Converter: The Peak and Average Input Currents The control circuit in the LTC1871-7 is measuring the input current (using a sense resistor in the MOSFET source), so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum input current for a SEPIC converter is: D IIN(MAX) = IO(MAX) • MAX 1– DMAX The peak input current is: IIN(PEAK) = 1+ 2 • IO(MAX) • DMAX 1– DMAX Like the boost converter, the input current of the SEPIC converter is calculated at full load current and minimum input voltage. The peak inductor current can be significantly higher than the output current, especially with smaller inductors and lighter loads. The following formulas assume CCM operation and calculate the maximum peak inductor currents at minimum VIN: V +V IL1(PEAK) = 1+ • IO(MAX) • O D 2 VIN(MIN) IL2(PEAK) = 1+ 2 • IO(MAX) • VIN(MIN) + VD VIN(MIN) The ripple current in the inductor is typically 20% to 40% (i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum average input current occurring at VIN(MIN) and IO(MAX) and ΔIL1 = ΔIL2. Expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: VIN(MIN) L= • DMAX IL • f where IL = • IO(MAX) • DMAX 1– DMAX The maximum duty cycle, DMAX, should be calculated at minimum VIN. The constant ‘χ’ represents the fraction of ripple current in the inductor relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30 and the peak current is 15% greater than the average. It is worth noting here that SEPIC converters that operate at high duty cycles (i.e., that develop a high output voltage from a low input voltage) can have very high input currents, relative to the output current. Be sure to check that the maximum load current will not overload the input supply. SEPIC Converter: Inductor Selection For most SEPIC applications the equal inductor values will fall in the range of 10μH to 100μH. Higher values will reduce the input ripple voltage and reduce the core loss. Lower inductor values are chosen to reduce physical size and improve transient response. By making L1 = L2 and winding them on the same core, the value of inductance in the equation above is replace by 2L due to mutual inductance. Doing this maintains the same ripple current and energy storage in the inductors. For example, a Coiltronix CTX10-4 is a 10μH inductor with two windings. With the windings in parallel, 10μH inductance is obtained with a current rating of 4A (the number of turns hasn’t changed, but the wire diameter has doubled). Splitting the two windings creates two 10μH inductors with a current rating of 2A each. Therefore, substituting 2L yields the following equation for coupled inductors: VIN(MIN) L1= L2 = •D 2 • IL • f MAX Specify the maximum inductor current to safely handle IL(PK) specified in the equation above. The saturation current 18717fc 25 LTC1871-7 APPLICATIONS INFORMATION rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. SEPIC Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gateto-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 7V INTVCC low dropout regulator. Consequently, 6V rated threshold MOSFETs are required in most LTC1871-7 applications. The maximum voltage that the MOSFET switch must sustain during the off-time in a SEPIC converter is equal to the sum of the input and output voltages (VO + VIN). As a result, careful attention must be paid to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. Many logic-level devices are limited to 30V or less. Check the switching waveforms directly across the drain and source terminals of the power MOSFET to ensure the VDS remains below the maximum rating for the device. Sense Resistor Selection During the MOSFET’s on-time, the control circuit limits the maximum voltage drop across the power MOSFET to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RSENSE. The relationship between the maximum load current, duty cycle and the sense resistor is: RSENSE VSENSE(MAX) IO(MAX ) • 1 1+ 2 • 1 VO + VD +1 VIN(MIN) 92% due to slope compensation, as shown in Figure 11. The constant ‘χ’ in the denominator represents the ripple current in the inductors relative to their maximum current. For example, if 30% ripple current is chosen, then χ = 0.30. Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself. As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the controller is using the MOSFET as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (load, line and temperature) and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. The power dissipated by the MOSFET in a SEPIC converter is: D PFET = IO(MAX) • 1– D 2 2 • RDS(ON) • D • T + k • ( VIN + VO ) •IO(MAX) • D •C •f 1– D RSS The first term in the equation above represents the I2R losses in the device and the second term, the switching losses. The constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The ρT term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/°C. Figure 12 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. The VSENSE(MAX) term is typically 150mV at low duty cycle and is reduced to about 100mV at a duty cycle of 18717fc 26 LTC1871-7 APPLICATIONS INFORMATION From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET •RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. This value of TJ can then be used to check the original assumption for the junction temperature in the iterative calculation process. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast-switching diode with low forward drop and low reverse leakage is desired. The output diode in a SEPIC converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to VIN(MAX) + VO. The average forward current in normal operation is equal to the output current, and the peak current is equal to: V +V ID(PEAK) = 1+ • IO(MAX) • O D + 1 2 VIN(MIN) The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. SEPIC Converter: Output Capacitor Selection Because of the improved performance of today’s electrolytic, tantalum and ceramic capacitors, engineers need to consider the contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL, and bulk C) on the output voltage ripple waveform are illustrated in Figure 21 for a typical coupled-inductor SEPIC converter. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging ΔV. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging ΔV. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: 0.01• VO ESRCOUT ID(PEAK ) where: ID(PEAK) = 1+ 2 • IO(MAX) • VO + VD +1 VIN(MIN) For the bulk C component, which also contributes 1% to the total ripple: IO(MAX) COUT 0.01• VO • f For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic or tantalum capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform 18717fc 27 LTC1871-7 APPLICATIONS INFORMATION should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a SEPIC regulator experiences high RMS ripple currents, as shown in Figure 21. The RMS output capacitor ripple current is: IRMS(COUT) = IO(MAX) • VIN(MIN) VO The RMS input capacitor ripple current for a SEPIC converter is: 1 • IL IRMS(CIN) = 12 Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! SEPIC Converter: Selecting the DC Coupling Capacitor The coupling capacitor C1 in Figure 20 sees nearly a rectangular current waveform as shown in Figure 21. During the switch off-time the current through C1 is IO(VO/VIN) while approximately –IO flows during the on-time. This current waveform creates a triangular ripple voltage on C1: IO(MAX) VO VC1(P P) = • C1• f VIN + VO + VD The maximum voltage on C1 is then: VC1(P P) VC1(MAX) = VIN + 2 which is typically close to VIN(MAX). The ripple current through C1 is: VO + VD IRMS(C1) = IO(MAX) • VIN(MIN) The value chosen for the DC coupling capacitor normally starts with the minimum value that will satisfy 1) the RMS current requirement and 2) the peak voltage requirement (typically close to VIN). Low ESR ceramic and tantalum capacitors work well here. Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. SEPIC Converter: Input Capacitor Selection The input capacitor of a SEPIC converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. The input voltage source impedance determines the size of the input capacitor which is typically in the range of 10μF to 100μF A low ESR capacitor . is recommended, although it is not as critical as for the output capacitor. 18717fc 28 LTC1871-7 TYPICAL APPLICATIONS A 48V Input Flyback Converter Configurable to 3.3V or 5V Outputs VIN 36V TO 72V CTX-002-15242 100k R1 604k 100k 1 2 1nF 26.7k 82.5k 4 5 12.4k 3 R2* 21k *R2 = 38.3k FOR VOUT = 5V 18717 TA02a UPS840 100μF 6.3V ×3 • T1A 2.2μF 100V T1B MMBTA42 0.1μF 10V VOUT 3.3V 3A MAX • RUN ITH VIN GATE LTC1871-7 9 7 Q1 FDC2512 ALL CAPACITORS ARE CERAMIC X5R TYPE FREQ SENSE 10 8 6 4.7μF R3 0.1Ω MODE/SYNC INTVCC VFB GND Output Efficiency at 3.3V Output 90 85 36VIN EFFICIENCY (%) 80 72VIN 75 70 65 60 48VIN EFFICIENCY (%) 90 85 80 Output Efficiency at 5V Output 36VIN 48VIN 72VIN 75 70 65 60 0 1 2 3 ILOAD (A) 4 5 6 0 1 2 3 ILOAD (A) 4 5 18717 TA02c 18717 TA02b 18717fc 29 LTC1871-7 TYPICAL APPLICATIONS 1.2A Automotive LED Headlamp Boost Converter L1 VIN D3 IRF12CW10 C7 10μF 100V 10 9 TO LEDS + GND RUN INPUT C5 47μF 20V ×2 R6 1M 1% 1 RUN ITH R7 4.7M SENSE VIN LTC1871-7 R8 187k 1% 2 C8 100nF 3 4 FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 C9 4.7μF X5R R12 4.02k Q3 SILICONIX SUP75N08-9L R11 0.006Ω D6 5V R9 1k D4 USE 68V 33V OR 75V D5 SINGLE 33V ZENER R10 300k 5 0V TO 5V DIMMING INPUT R13 17.8k R15 0.20Ω 0.5W R14 1k C10 4.7μF C5: SANYO OS-CON 20SP47M C7: ITW PAKTRON 106K100CS4 L1: MAGNETICS INC 58206-A2 WITH 29T 18AWG 18717 TA01 FROM LEDS Dual Output Cell Phone Base Station Flyback Converter TAB GND LT1963 SHDN IN GND OUT ADJ L1 10μH C6 1μF 35V T1 VP4-0047 C7 3.3μF 50V 1 12 2 11 3 10 4 9 8 5 D3 UPS840 R9 33k LT1431 Q1 Si4482DY C15 4.7μF C17 1μF D4 BAT54 R13 0.082Ω C11 100μF 1 2 3 4 COL COMP V+ RTOP REF RMID GNDF GNDS 8 7 6 5 R10 64.9k C13A 470μF C10 330nF C12 15nF R8 20.5k 7 6 C9 R6 1nF 1Ω D1 1A 40V C3 100μF 1 2 3 4 5 5.5V 500mA C4 33μF R2 12.5k VIN 18V TO 33V + C5 22μF 50V R4 75Ω D2 10V C8 100pF 200V R3 43.2k R5 150k 3.3V 2A R7 33k 1 2 RUN ITH SENSE VIN LTC1871-7 10 9 3 4 SYNC SIGNAL 320kHz 0V TO 2.5V 5 R11 12.5k C14 1nF R12 80k FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 + + C13 470μF R1 33k C16 10nF 1kV ISO1 MOC207 R14 1k C3, C11: TDK C3225X5R0J107M C4: SANYO POSCAP 10 TPB33M C7: TDK C4532X7R1H335M C13, C13A: SANYO POSCAP 4TPB470M L1: COILCRAFT DO1608 103 T1: COILTRONICS VP4-0047 18717 TA03 18717fc 30 LTC1871-7 TYPICAL APPLICATIONS Automotive SEPIC Converter T1 VP5-0155 Q6 FMMT451 VBATT 8V TO 25V CR4 BZX84C15V R37 75k 1% 1 • 12 2 • 11 3 • 9 1 2 VIN RUN ITH LTC1871-7 R45 33.2k R47 133k 1% C47 6800pF 3 4 5 FB FREQ MODE/SYNC GND 6 GATE 7 INTVCC 8 SENSE 10 R43 13.3k 1% C50 C46 4μF 100pF X7R PACKAGE DESCRIPTION MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.497 ± 0.076 (.0196 ± .003) REF 0.889 ± 0.127 (.035 ± .005) GAUGE PLANE 0.254 (.010) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) DETAIL “A” 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.18 (.007) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. • • • R46 47k 4 9 5 8 6 7 10 C52 4.7μF X7R ×2 CR21 MBR10100 CR22 1N4148 L7 150Ω 3A BEAD 1B (OPTIONAL HF FILTER) VOUT 13.5V 3A Q9 Si4486EY SO-8 R59 0.005Ω 1W 1% R60 124k 1% + C53 22μF 16V X5R ×2 C55 4.7μF 16V X7R ×2 + C51 150μF 35V C57 10μF X5R (OPTIONAL HF FILTER) C49 4.7μF R61 12.4k 1% 18717 TA04 10 9 8 7 6 DETAIL “A” 0° – 6° TYP 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.53 ± 0.152 (.021 ± .006) 12345 1.10 (.043) MAX 0.86 (.034) REF 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS) 0307 REV E 18717fc 31 LTC1871-7 TYPICAL APPLICATION A Small, Nonisolated 12V Flyback Telecom Housekeeping Supply D3 36V VIN TO 72V R1 604k 1% C1 1nF OPTIONAL UV+ = 31.8V UV– = 29.5V RUN ITH LTC1871-7 RC 3.4k R4 110k 1% FB R3 12.4k 1% RT 120k FREQ MODE/SYNC f = 200kHz INTVCC GATE GND C2 4.7μF X5R C3 0.1μF X5R RS 0.12Ω M1 CIN 2.2μF 100V X7R R5 100k Q1 D1 9.1V R6 10Ω VOUT 12V 0.4A COUT 47μF X5R R2 26.7k 1% CC2 47pF T1 1, 2, 3 (SERIES) • 4, 5, 6 (PARALLEL) • SENSE VIN D2 CC1 2.2nF 18717 TA05 T1: COILTRONICS VP1-0076 M1: FAIRCHILD FDC2512 (150V, 0.5Ω) Q1: ZETEX FMMT625 (120V) D1: ON SEMICONDUCTOR MMBZ5239BLT1 (9.1V) D2: ON SEMICONDUCTOR MMSD4148T11 D3: INTERNATIONAL RECTIFIER 10BQ060 RELATED PARTS PART NUMBER LT 1619 LTC1624 LTC1700 LTC1871 LTC1872 LT1930 LT1931 LTC3401/LTC3402 LTC3803 LTC3806 ® DESCRIPTION Current Mode PWM Controller Current Mode DC/DC Controller No RSENSE Synchronous Step-Up Controller Wide Input Range, No RSENSE Controller SOT-23 Boost Controller 1.2MHz, SOT-23 Boost Converter Inverting 1.2MHz, SOT-23 Converter 1A/2A 3MHz Synchronous Boost Converters SOT-23 Flyback Controller Synchronous Flyback Controller COMMENTS 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V Up to 95% Efficiency, Operation as Low as 0.9V Input Operation as Low as 2.5V Input, Boost Flyback,SEPIC Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode Up to 34V Output, 2.6V ≤ VIN ≤ 16V, Miniature Design Positive-to-Negative DC/DC Conversion, Miniature Design Up to 97% Efficiency, Very Small Solution, 0.5V ≤ VIN ≤ 5V Adjustable Slope Compensation, Internal Soft-Start, Current Mode 200kHz Operation High Efficiency, Improves Cross Regulation in Multiple Output Designs, Current Mode, 3mm × 4mm 12-Pin DFN Package 18717fc 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0108 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2002