LT1947 Adjustable Output TFT-LCD Triple Switching Regulator
FEATURES
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
DESCRIPTIO
Complete Solution Under 1.2mm Develops Three Outputs from a 3.3V or 5V Supply Externally Programmable VON Delay Fixed Frequency Low Noise Outputs All Ceramic Capacitors 3MHz Switching Frequency Fast Transient Response Few External Components Required 2.7V to 8V Input Range Adjustable AVDD and VON Voltages Tiny 10-Lead MSOP and Thermally Enhanced 10-Lead MSOP Packages
APPLICATIO S
■ ■ ■ ■
TFT-LCD Notebook Display Panels TFT-LCD Desktop Monitor Display Panels Digital Cameras Handheld Computers
The LT®1947 is a highly integrated multiple output DC/DC converter designed for use in TFT-LCD panels. The device contains two independent switching regulators. The main regulator has an adjustable output voltage with an internal 1.1A switch that can generate a boosted voltage as high as 30V. The second regulator’s output is also adjustable up to 30V and can deliver 10mA for positive bias. A simple level-shift charge pump off the main switch node generates the negative bias voltage. An external capacitor sets the delay time from AVDD’s final value to the rising edge at the VON pin. The 3MHz switching frequency allows the use of tiny low profile chip inductors and capacitors throughout, providing a low noise, low cost total solution with all components under 1.2mm in height. The device operates from an input range of 2.7V to 8V and is available in 10-lead MSOP and thermally enhanced 10-lead MSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
D3
D4
L1 3.3µH VIN L2 4.7µH C1 2.2µF CERAMIC
C6 0.68µF
D1 VIN SW2 SW1 FB1
C4 0.68µF CERAMIC AVDD 8V 200mA R1 53.6k C2 3.3µF CERAMIC ×2
VSHDN 5V/DIV VON 20V/DIV
VOFF –8V 10mA
D2 VO2 C3 220nF R3 182k FB2 R4 10k SHDN CT C5 10nF D1: MBRM120LT3 D2: CMDSH-3 D3, D4: BAT54S DUAL DIODE L1: SUMIDA CLQ4D103R3 L2: TAIYO YUDEN LB2012B4R7M VON GND LT1947 R2 10k
VON 24V 10mA
AVDD 10V/DIV
SHUTDOWN
VOFF 10V/DIV
1947 F01
C1: TAIYO YUDEN LMK316BJ225MD C2: TAIYO YUDEN LMK325BJ335MD × 2 C3: AVX 0.22µF 25V X7R C4, C6: TAIYO YUDEN LMK107BJ684MA
Figure 1. 3.3V Powered TFT-LCD Bias Generator
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Start-Up Waveforms
2ms/DIV
1947 TA01.tif
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LT1947
ABSOLUTE
(Note 1)
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RATI GS
FB1, FB2 .................................................................... 3V SHDN......................................................................... 8V Operating Temperature Range (Note 2) .. – 40°C to 85°C Lead Temperature (Soldering, 10 sec).................. 300°C
VIN Voltage ................................................................ 8V CT Voltage.................................................................. 6V SW1, SW2 Voltage .................................................. 36V VON, VO2 Voltage ..................................................... 30V
PACKAGE/ORDER I FOR ATIO
TOP VIEW FB1 FB2 CT SW1 GND 1 2 3 4 5 10 9 8 7 6 VON V02 SHDN SW2 VIN
ORDER PART NUMBER LT1947EMSE
FB1 FB2 CT SW1 GND 1 2 3 4 5
11
MSE PACKAGE 10-LEAD PLASTIC MSOP EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB
MSE PART MARKING LTBQW
TJMAX = 125°C, θJA = 40°C/W
Order Options Tape and Reel: Add #TR, Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL Input Voltage Range Supply Current FB1 Voltage SHDN = 2.4V SHDN = 0V CONDITIONS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, VSHDN = 3.3V unless otherwise specified.
MIN 2.7 9.5 1.240 1.225 1.225 1.210 1.26 1.26 0.01 TYP MAX 8 12.5 1 1.280 1.295 1.295 1.310 0.05 UNITS V mA µA V V V V %/V
FB2 Voltage
●
Reference Line Regulation
VIN = 2.7V to 8V
2
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TOP VIEW 10 9 8 7 6 VON VO2 SHDN SW2 VIN
ORDER PART NUMBER LT1947EMS
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W
MS PART MARKING LTUE
●
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LT1947
ELECTRICAL CHARACTERISTICS
SYMBOL Error Amplifier Voltage Gain CT Current Source CT Threshold to Turn On Q3 FB1 Voltage to Begin CT Charge SW1 Current Limit SW2 Current Limit SW1 Saturation Voltage SW2 Saturation Voltage SW1 Maximum Duty Cycle SW2 Maximum Duty Cycle Oscillator Frequency VON Switch Drop SW1 Leakage Current SW2 Leakage Current SHDN Pin Bias Current SHDN Pin High SHDN Pin Low IQ3 = 7mA (Note 3) (Note 3) ISW1 = 800mA ISW2 = 300mA CONDITIONS EA1 and EA2 VFB1 = 1.3V
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, VSHDN = 3.3V unless otherwise specified.
MIN 4 1.25 1.17 1.1 0.35 TYP 100 5.5 1.28 1.2 1.4 0.6 0.230 0.3 82 85
●
MAX 6.5 1.30 1.23 2 1 0.280 0.36
UNITS V/V µA V V A A V V % %
2.3
3 160 0.01 0.01 10
3.5 200 5 5 25 0.4
MHz mV µA µA µA V V
Switch Off, SW1 = 3.3V Switch Off, SW2 = 3.3V VSHDN = 2.4V Active Mode Shutdown Mode 2.4
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1947 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Switch current limit guaranteed by design and/or correlation to static tests.
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V TFT-LCD Converter Efficiency
85 80 75
EFFICIENCY (%)
VIN = 3.3V
SUPPLY CURRENT (mA)
65 60 55 50 45 40 35 0 25 50 75 100 125 150 175 200 AVDD LOAD CURRENT (mA)
1947 G01
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CT CURRENT (µA)
70
VIN = 3V
UW
VIN = 2.7V
Supply Current
12 SHDN = 2.4V 10 –4 –2
CT Current Source
–6
6
–8
4 –50
–25
0 25 50 TEMPERATURE (°C)
75
100
1947 G02
–10 –50
–25
0 25 50 TEMPERATURE (°C)
75
100
1947 G03
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LT1947 TYPICAL PERFOR A CE CHARACTERISTICS
SW1 Current Limit
1.8
1.6
SW1 CURRENT (A)
1.4
SW2 CURRENT (A)
–25 0 25 50 TEMPERATURE (°C) 75 100
1947 G04
1.2
1.0
0.8 –50
Switch 1 Saturation Voltage
500
SWITCH 1 SATURATION VOLTAGE (mV)
SWITCH 2 SATURATION VOLTAGE (mV)
400 25°C 300 90°C 200 –45°C 100
0 0 0.2 0.4 0.6 0.8 1 SWITCH CURRENT (A) 1.2 1.4
SW1 Maximum Duty Cycle
100 3.2
90
OSCILLATOR FREQUENCY (MHz)
SW1 DUTY CYCLE (%)
80
70
60
50 –50
–25
0 25 50 TEMPERATURE (°C)
4
UW
SW2 Current Limit
1.0
0.8
0.6
0.4
0.2
0 –50
–25
0 25 50 TEMPERATURE (°C)
75
100
1947 G05
Switch 2 Saturation Voltage
800 25°C 600 90°C 400 –45°C 200
0 0 0.1 0.2 0.3 0.4 SWITCH CURRENT (A) 0.5 0.6
1947 G07
1947 G06
Oscillator Frequency
3.0
2.8
2.6
2.4
75
100
1947 G08
2.2 –50
–25
0 25 50 TEMPERATURE (°C)
75
100
1947 G09
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LT1947
PI FU CTIO S
FB1 (Pin 1): Feedback Pin for First Switcher. Connect resistor divider tap here. Set AV DD according to: AVDD = 1.26V(1 + R1/R2). FB2 (Pin 2): Feedback Pin for Second Switcher. Connect resistor divider 2 here and set V ON u sing: VON = 1.26V (1 + R3/R4) – 160mV. CT (Pin 3): Timing Capacitor Pin. Connect a 10nF capacitor from CT to ground to program a 2.3ms delay from FB1 reaching 1.26V to VON turning on. SW1 (Pin 4): AVDD Switch Node. Connect L1 and D1 here (see Figure 1). Minimize trace area at this pin to keep EMI down. GND (Pin 5): Ground. Connect directly to local ground plane. VIN (Pin 6): Input Supply Pin. Must be bypassed with a ceramic capacitor close to the pin. SW2 (Pin 7): VO2 Switch Node. Connect L2 and D2 here. Minimize trace area at this pin to keep EMI down. SHDN (Pin 8): Pull this pin low for shutdown mode. For normal operation, tie to a voltage between 2.4V and 8V. VO2 (Pin 9): SW2 Output. This node is also internally connected to the emitter of Q3 (see Block Diagram), the high side switch between VO2 and VON. VON (Pin 10): This is the delayed output for second Switcher. VON reaches its programmed voltage after the internal timer times out. Exposed Pad (Pin 11): Ground (MSE package only). The exposed pad must be soldered to the PCB and electrically connected to ground.
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LT1947
BLOCK DIAGRA
CT VON Q4
Q3
VO2
OSC 3MHz OSCILLATOR SLOPE 1 SLOPE 2
6
W
VIN VIN FB1 5.5µA 28mV GND SHDN SHUTDOWN OSC SW1
– – + +
REF R
S Q Q1
+–
– +
REF REF
– +
∑
+ +
0.01Ω
SLOPE 1 OSC SW2
FB2
– – +
R
S Q Q2
1.26V REFERENCE AND UNDERVOLTAGE LOCKOUT
+
REF REF
∑
+ +
0.03Ω
SLOPE 2
1947BD
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LT1947
OPERATIO
To best understand operation of the LT1947, please refer to the LT1947 Block Diagram. The device contains two switching regulators, a timer and a high side switch. Three outputs can be generated: an adjustable AVDD output, a charge-pumped inversion of the AVDD output called VOFF, and a time delayed adjustable output called VON. Q3 keeps VON off for an externally set time interval, set by a capacitor connected to the CT pin. The switching frequency of both switchers is 3MHz, set internally. The switchers are current mode and are internally compensated. The main AVDD switcher is current limited at 1.1A, while the second VON switcher is limited to 350mA. They share the same 1.26V reference voltage. When the input voltage is below approximately 2.7V, an undervoltage lockout circuit disables switching. When AVDD is less than its final voltage, Q4 is turned on, holding the CT pin at ground. When AVDD reaches final value, Q4 lets go of the CT pin, allowing the 5.5µA current source to charge the external capacitor, CT. When the voltage on the CT pin reaches 1.28V, Q3 turns on, connecting VO2 to VON. Capacitor value can be calculated using the following formula:
R3 GND R1 1 C5 LT1947 2 3 L1 4 5 C1 VIN C6 R4 R2
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C = (5.5µA • tDELAY)/1.28V A 10nF capacitor results in approximately 2.3ms of delay. Layout Hints The high speed operation of the LT1947 mandates careful attention to layout for proper performance. Be sure to keep input capacitor C1 as close as possible to the IC and minimize trace area and length at the SW and FB pins. Always use a ground plane under the switching regulator to minimize interplane coupling. Figure 2 shows the recommended component placement. The exposed pad of the MSE package must be soldered to the PCB and electrically connected to ground. Thermal vias to a large ground plane will lower the thermal resistance. Soft-Start For applications requiring soft-start, a circuit consisting of RSS and CSS tied to the SHDN pin can be used, as shown in Figure 3. For a combination of 33.2k/33nF, AVDD rises to its final value in approximately 3ms.
VON 10 9 8 7 6 SHDN L2 D2 C3 VIN D1 D3 C4 AVDD C2 D4 GND VOFF
1947 F02
Figure 2. Recommended Component Placement
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LT1947
OPERATIO
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D3 D4 L1 3.3µH VIN L2 4.7µH C1 2.2µF CERAMIC D1 VIN SW2 D2 VO2 C3 220nF RSS 33.2k VSS CSS 33nF VOFF C1: TAIYO YUDEN LMK316BJ225MD C2: TAIYO YUDEN LMK325BJ335MD × 2 C3: AVX 0.22µF 25V X7R C4, C6: TAIYO YUDEN LMK107BJ684MA D1: MBRM120LT3 D2: CMDSH-3 D3, D4: BAT54S DUAL DIODE L1: SUMIDA CLQ4D103R3 L2: TAIYO YUDEN LB2012B4R7M R3 182k FB2 R4 10k SHDN CT C5 10nF
1947 F03
C6 0.68µF
C4 0.68µF CERAMIC AVDD 8V 200mA R1 53.6k C2 3.3µF CERAMIC ×2
VOFF –8V 10mA
SW1 FB1
LT1947
R2 10k VON GND VON 24V 10mA
Figure 3. RSS and CSS at SHDN Pin Provide Soft-Start
VSS 5V/DIV VON 20V/DIV
AVDD 10V/DIV
VOFF 10V/DIV 5ms/DIV
1947 F04.tif
Figure 4. Start-Up Waveforms with Soft-Start Circuit Added
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LT1947
TYPICAL APPLICATIO S
TFT-LCD Bias Generator: 12V, 20V, – 6V Output
VIN 3.3V L2 4.7µH VIN SW2 C1 4.7µF D2 VO2 C3 0.22µF SHUTDOWN R3 147k FB2 R4 10k
C1: TAIYO YUDEN JMK316BJ475MD 4.7µF 6.3V X7R C2: TAIYO YUDEN LMK325BJ335MD 3.3µF 10V X7R × 2 C3: AVX 0.22µF 25V X7R C4, C6: TAIYO YUDEN LMK107BJ684MA 0.68µF 10V X7R
VIN 3.3V L2 4.7µH C1 2.2µF CERAMIC VIN SW2 D2 VO2 C3 220nF SHUTDOWN R3 182k FB2 R4 10k
C1: TAIYO YUDEN LMK316BJ225MD 2.2µF X7R C2: TAIYO YUDEN LMK325BJ335MD 3.3µF X5R C3, C6: AVX 0.22µF CERAMIC X7R C4: TAIYO YUDEN EMK212BJ684MD
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34k Q1 BAT54S D3 D4 34k Q2
VOFF –6V 20mA
L1 4.7µH
C4 C6 AVDD 12V 120mA R1 86.6k C2 3.3µF CERAMIC ×2
D1 SW1 FB1
LT1947
R2 10k VON GND VON 20V 10mA
SHDN CT C5 10nF
D1: MBRM120 D2: CMDSH-3 L1: SUMIDA CLQ4DI04R7 L2: TAIYO YUDEN LB2012B4R7M Q1: MMBT3904 NPN Q2: MMBT3906 PNP
1947 TA02
TFT-LCD Bias Generator: 10V, 24V, – 6V Output
BAT54S D3 D4 VOFF –6V 10mA C4 0.68µF AVDD 10V 150mA R1 69.8k C2 3.3µF CERAMIC ×2
L1 3.3µH
C6 220nF
D1 SW1 FB1
LT1947
R2 10k VON GND VON 24V 10mA
SHDN CT C5 10nF
1947 TA04 D1: MBRM120 D2: CMDSH-3 L1: SUMIDA CLQ4DI03R3 L2: TAIYO YUDEN LB2012B-4R7M
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LT1947
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.127 ± 0.076 (.005 ± .003)
MSOP (MS) 0603
0.50 (.0197) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
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MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127 (.035 ± .005) 3.20 – 3.45 (.126 – .136)
3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF
DETAIL “A” 0° – 6° TYP
4.90 ± 0.152 (.193 ± .006)
3.00 ± 0.102 (.118 ± .004) (NOTE 4)
12345 0.53 ± 0.152 (.021 ± .006)
DETAIL “A” 1.10 (.043) MAX
0.86 (.034) REF
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LT1947
PACKAGE DESCRIPTIO
2.794 ± 0.102 (.110 ± .004)
5.23 (.206) MIN
0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010)
GAUGE PLANE
0.18 (.007)
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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MSE Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF EXPOSED PAD OPTION
0.889 ± 0.127 (.035 ± .005)
1
2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004)
2.083 ± 0.102 3.20 – 3.45 (.082 ± .004) (.126 – .136)
10 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6
0.497 ± 0.076 (.0196 ± .003) REF
4.90 ± 0.152 (.193 ± .006)
DETAIL “A” 0° – 6° TYP
3.00 ± 0.102 (.118 ± .004) (NOTE 4)
12345 0.53 ± 0.152 (.021 ± .006)
DETAIL “A” SEATING PLANE
1.10 (.043) MAX
0.86 (.034) REF
0.17 – 0.27 (.007 – .011) TYP
0.50 (.0197) BSC
0.127 ± 0.076 (.005 ± .003)
MSOP (MSE) 0603
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LT1947
TYPICAL APPLICATIO U
TFT-LCD Bias Generator: 7.5V, 15V, – 10V Output
L1 3.3µH L2 4.7µH C1 1µ F CERAMIC ×2 D1 VIN SW2 D2 VO2 C3 0.68µF SHUTDOWN R3 105k FB2 R4 10k SHDN CT C5 10nF D1: MBRM120 1947 TA03 D2: CMDSH-3 D7: MMBZ5240 10V ZENER L1: SUMIDA CLQ4D103R3 L2: TAIYO YUDEN LB2012B-4R7M Q1: MMBT3906 PNP VON GND LT1947 R2 10k VON 15V 10mA SW1 FB1 AVDD 7.5V 200mA R1 49.9k C2 3.3µF CERAMIC ×2 C7 0.68µF C8 D3 D4 C4 0.68µF D5 D6 34k D7 34k Q1 VOFF –10V 20mA VIN 3.3V BAT54S C1: TAIYO YUDEN JMK107BJ105MA 1µF 6.3V X7R × 2 C2: TAIYO YUDEN LMK325BJ335MD 3.3µF 10V X7R × 2 C3, C7, C8: TAIYO YUDEN EMK212BJ684MD 0.68µF 16V X7R C4, C6: TAIYO YUDEN LMK107BJ684MA 0.68µF 10V X5R
C6 0.68µF
BAT54S
RELATED PARTS
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