LT1970

LT1970 500mA Power Op Amp with Adjustable Precision Current Limit FEATURES s s DESCRIPTIO s s s s s s s s s ± 500mA Minimum Output Current Independent Adjustment of Source and Sink Current Limits 2% Current Limit Accuracy Operates with Single or Split Supplies Shutdown/Enable Control Input Open Collector Status Flags: Sink Current Limit Source Current Limit Thermal Shutdown Fail Safe Current Limit and Thermal Shutdown 1.6V/µs Slew Rate 3.6MHz Gain Bandwidth Product Fast Current Limit Response: 2MHz Bandwidth Specified Temperature Range: – 40°C to 85°C The LT®1970 is a ± 500mA power op amp with precise externally controlled current limiting. Separate control voltages program the sourcing and sinking current limit sense thresholds with 2% accuracy. Output current may be boosted by adding external power transistors. The circuit operates with single or split power supplies from 5V to 36V total supply voltage. In normal operation, the input stage supplies and the output stage supplies are connected (VCC to V+ and VEE to V–). To reduce power dissipation it is possible to power the output stage (V+, V–) from independent, lower voltage rails. The amplifier is unity-gain stable with a 3.6MHz gain bandwidth product and slews at 1.6V/µs. The current limit circuits operate with a 2MHz response between the VCSRC or VCSNK control inputs and the amplifier output. Open collector status flags signal current limit circuit activation, as well as thermal shutdown of the amplifier. An enable logic input puts the amplifier into a low power, high impedance output state when pulled low. Thermal shutdown and a ±800mA fixed current limit protect the chip under fault conditions. The LT1970 is packaged in a 20-lead TSSOP package with a thermally conductive copper bottom plate to facilitate heat sinking. APPLICATIO S s s s s Automatic Test Equipment Laboratory Power Supplies Motor Drivers Thermoelectric Cooler Driver , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO VLIMIT 0V TO 5V V IOUT(LIMIT) = ± LIMIT 10 • RCS AV = 2 Amplifier with Adjustable ± 500mA Full-Scale Current Limit and Fault indication 15V 15V 3k V VCSRC +IN VCSNK ISNK ISRC TSD OUT LT1970 SENSE+ SENSE– V– –IN VEE COMMON VCC Current Limited Sinewave Into 10Ω Load 4V + VIN VLOAD IOUT RCS 1Ω 1/4W 2V 0V – 2V R1 10k R2 10k 1970 TA01 LOAD –15V VCSRC = 4V VCSNK = 2V RCS = 1Ω U 20µs/DIV 1970 TA02 U U 1970f 1 LT1970 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW VEE V– OUT SENSE+ FILTER SENSE– VCC –IN +IN 1 2 3 4 5 6 7 8 9 20 VEE 19 V+ 18 TSD 17 ISNK 16 ISRC VEE 10 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 40°C/ W (NOTE 6) UNDERSIDE METAL CONNECTED TO VEE Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VOS PARAMETER Input Offset Voltage Power Op Amp Characteristics The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions. CONDITIONS MIN TYP 200 0°C < TA < 70°C –40°C < TA < 85°C Input Offset Voltage Drift (Note 4) IOS IB en in RIN CIN VCM CMRR PSRR Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Input Resistance Input Capacitance Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio VCM = 0V VCM = 0V 0.1Hz to 10Hz 1kHz 1kHz Common Mode Differential Mode Pin 8 and Pin 9 to Ground Typical Guaranteed by CMRR Test –12V < VCM < 12V VEE CC VEE = V– = – 5V, VCC = 30V, V+ = 2.5V to 30V VEE = V– = – 3V to – 30V, VCC = V+ = 5V VEE = – 30V, V– = – 2.5V to –30V, VCC = V+ = 5V = V– = – 5V, V = V+ = 3V to 30V q q q q q q q q q q q 2 +– Supply Voltage (VCC to VEE).................................... 36V Positive High Current Supply (V+) .................. V– to VCC Negative High Current Supply(V–) ................... VEE to V+ Amplifier Output (OUT) ..................................... V – to V+ Current Sense Pins (SENSE+, SENSE–, FILTER) .......................... V – to V+ Logic Outputs (ISRC, ISNK, TSD) ....... COMMON to VCC Input Voltage (–IN, +IN) .......... VEE – 0.3V to VEE + 36V Input Current ....................................................... 10mA Current Control Inputs (VCSRC, VCSNK) ............. COMMON to COMMON + 7V Enable Logic Input .............................. COMMON to VCC COMMON ..................................................... VEE to VCC Output Short-Circuit Duration ......................... Indefinite Operating Temperature Range (Note 2) .. – 40°C to 85°C Specified Temperature Range (Note 3) ... – 40°C to 85°C Maximum Junction Temperature ......................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LT1970CFE 15 ENABLE 14 COMMON 13 VCSRC 12 VCSNK 11 VEE MAX 600 800 1000 10 100 UNITS µV µV µV µV/°C nA nA µVP-P nV/√Hz pA/√Hz kΩ kΩ pF –10 –100 –600 –4 –160 3 15 3 500 100 6 –14.5 –12.0 92 90 110 90 110 105 100 130 100 130 13.6 12.0 U V V dB dB dB dB dB 1970f W U U WW W LT1970 ELECTRICAL CHARACTERISTICS SYMBOL AVOL PARAMETER Large-Signal Voltage Gain The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions. CONDITIONS RL = 1k, –12.5V < VOUT < 12.5V q MIN 100 75 80 40 20 5 TYP 150 120 60 MAX UNITS V/mV V/mV V/mV V/mV V/mV V/mV RL = 100Ω, –12.5V < VOUT < 12.5V q RL = 10Ω, –5V < VOUT < 5V, V+ = – V– = 8V q VOL Output Sat Voltage Low VOL = VOUT – V– RL = 100, VCC = V+ = 15V, VEE = V– = –15V RL = 10, VCC = – VEE = 15V, V+ = – V– = 5V VOH = V+ – VOUT RL = 100, VCC = V+ = 15V, VEE = V– = –15V RL = 10, VCC = – VEE = 15V, V+ = – V– = 5V Output Low, RSENSE = 0Ω Output High, RSENSE = 0Ω –10V < VOUT < 10V, RL = 1k VOUT = 10VPEAK (Note 5) f = 10kHz 0.01%, VOUT = 0V to 10V, AV = – 1, RL = 1k VCSRC = VCSNK = 0V q 1.9 0.8 1.7 1.0 500 –1000 0.7 11 3.6 8 0.1 0.1 15 45 490 480 –1 – 200 – 200 –500 200 –300 –25 – 0.1 ±0.05 ±0.01 ±0.05 ±0.01 2 250 –250 4 20 50 500 500 –0.2 800 – 800 1.6 2.4 V V V V mA mA V/µs kHz MHz µs VOH Output Sat Voltage High q 2.2 1200 – 500 ISC SR FPBW GBW tS VSENSE(MIN) VSENSE(4%) VSENSE(10%) VSENSE(FS) IBI ISENSE– IFILTER ISENSE+ Output Short-Circuit Current Slew Rate Full Power Bandwidth Gain Bandwidth Product Settling Time Minimum Current Sense Voltage Current Sense Voltage 4% of Full Scale Current Sense Voltage 10% of Full Scale Current Sense Voltage 100% of Full Scale Current Limit Control Input Bias Current SENSE– Input Current FILTER Input Current SENSE+ Input Current Current Sense Characteristics q 7 10 25 55 510 520 0.1 200 200 500 300 –200 25 0.1 mV mV mV mV mV mV µA nA nA nA µA µA µA % % % % % MHz VCSRC = VCSNK = 0.2V VCSRC = VCSNK = 0.5V VCSRC = VCSNK = 5V q q q VCSRC, VCSNK Pins 0V < (VCSRC, VCSNK) < 5V 0V < (VCSRC, VCSNK) < 5V VCSRC= VCSNK = 0V VCSRC = 5V, VCSNK = 0V VCSRC= 0V, VCSNK = 5V VCSRC = VCSNK = 5V VCSRC = VCSNK = 5V, 6V < (VCC, V+) < 18V 2.5V < V+ < 18V, VCC = 18V –18V < (VEE, V–) < –2.5V –18V < V– < – 2.5V, VEE = – 18V q q q q q q q q Current Sense Change with Output Voltage VCSRC = VCSNK = 5V, –12.5V < VOUT < 12.5V Current Sense Change with Supply Voltage Current Sense Bandwidth RCSF Resistance FILTER to SENSE– Logic Output Leakage ISRC, ISNK, TSD Logic Low Output Level Logic Output Current Limit VENABLE IENABLE Enable Logic Threshold Enable Pin Bias Current V = 15V I = 5mA q 750 1000 1250 1 Ω µA V mA V µA 1970f Logic I/O Characteristics q q q q q 0.2 25 0.8 –1 1.6 0.4 2.4 1 3 LT1970 ELECTRICAL CHARACTERISTICS SYMBOL ISUPPLY ICC ICC(STBY) tON tOFF PARAMETER Total Supply Current VCC Supply Current Supply Current Disabled Turn-On Delay Turn-Off Delay VCC, V+ VCC, V+ VCC, V+ The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions. CONDITIONS and V–, VEE Connected and V–, VEE Separate and V–, VEE Connected, VENABLE q q MIN TYP 7 3 0.6 10 10 MAX 13 7 1.5 UNITS mA mA mA µs µs ≤ 0.8V q (Note 7) (Note 7) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1970C is guaranteed functional over the operating temperature range of – 40°C and 85°C. Note 3: The LT1970C is guaranteed to meet specified performance from 0°C to 70°C. The LT1970C is designed, characterized and expected to meet specified performance from – 40°C to 85°C but is not tested or QA sampled at these temperatures. Note 4: This parameter is not 100% tested. Note 5: Full power bandwidth is calculated from slew rate measurements: FPBW = SR/(2 • π • VP) Note 6: Thermal resistance varies depending upon the amount of PC board metal attached to the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. Note 7: Turn-on and turn-off delay are measured from VENABLE crossing 1.6V to the OUT pin at 90% of normal output voltage. TYPICAL PERFOR A CE CHARACTERISTICS Warm-Up Drift VIO vs Time –100 VOS • 1000 (50mV/DIV) TOTAL SUPPLY CURRENT (mA) INPUT BIAS CURRENT (nA) TIME (100ms/DIV) 4 UW 0V 1970 G04 Input Bias Current vs VCM VS = ±15V –120 –140 –IBIAS –160 +IBIAS –180 –200 – 220 –240 –260 –15 –12 –9 –6 –3 0 3 6 9 12 15 COMMON MODE INPUT VOLTAGE (V) 1970 G05 Total Supply Current vs Supply Voltage 14 12 10 8 6 4 2 0 –2 –4 –6 –8 –10 –12 –14 0 ICC + IV + 125°C 25°C –55°C IEE + IV – –55°C 25°C 125°C 2 4 6 8 10 12 14 SUPPLY VOLTAGE (± V) 16 18 1970 G15 1970f LT1970 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 4.5 4.0 SUPPLY CURRENT (mA) IV+ IV– OPEN-LOOP GAIN (dB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (± V) TA = 25°C VCC = V + = –VEE = –V – IVEE IVCC 40 30 20 10 0 –10 –20 70 60 50 40 30 20 10 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 100M PHASE MARGIN (DEG) Slew Rate vs Supply Voltage 1.8 1.7 FALLING 1.6 SLEW RATE (V/µs) 1.5 1.4 1.3 1.2 1.1 1.0 4 AV = –1 RF = RG = 1k TA = 25°C 6 14 12 10 SUPPLY VOLTAGE (± V) 8 16 18 1970 G23 SLEW RATE (V/µs) RISING Large-Signal Response, AV = – 1 10V 0V –10V R L = 1k CL = 1000pF 20µs/DIV UW 18 1870 G16 Open-Loop Gain and Phase vs Frequency 70 60 50 GAIN PHASE 100 90 80 60 58 56 Phase Margin vs Supply Voltage AV = –1 RF = RG = 1k TA = 25°C VOUT = VS/2 PHASE MARGIN (DEG) 54 52 50 48 46 44 42 40 0 4 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) 36 20 –30 100 1970 G18 1970 G21 Slew Rate vs Temperature 2.5 VS = ±15V FALLING 10V Large-Signal Response, AV = 1 2.0 RISING 1.5 0V 1.0 –10V 0.5 R L = 1k 20µs/DIV 1970 G39 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1970 G24 Small-Signal Response, AV = 1 Small-Signal Response, AV = – 1 1970 G40 RL = 1k 500ns/DIV 1970 G41 RL = 1k CL = 1000pF 2µs/DIV 1970 G42 1970f 5 LT1970 TYPICAL PERFOR A CE CHARACTERISTICS % Overshoot vs CLOAD 60 50 OUTPUT SWING (VP-P) AV = 1 VS = ± 15V 30 25 20 VSENSE (mV) OVERSHOOT (%) 40 30 AV = – 1 20 10 0 10 100 CLOAD (pF) 1970 G44 1k Low Level Current Sense Transfer Curve 25 20 OUTPUT STAGE CURRENT (mA) 10 8 6 4 2 0 –2 –4 –6 –8 –10 15 10 VSENSE (mV) 5 0 –5 –10 –15 –20 –25 0 25 50 75 100 125 150 175 200 225 250 VCSNK = VCSRR (mV) 1970 G51 Control Stage Quiescent Current vs Supply Voltage 5 4 3 SUPPLY CURRENT (mA) 2 1 0 –1 –2 –3 –4 –5 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (± V) 16 18 IEE 800 125°C 25°C –55°C TOTAL SUPPLY CURRENT, ICC + IV+ (µA) ICC 6 UW Undistorted Output Swing vs Frequency 500 400 300 200 100 0 –100 –200 Full Range Current Sense Transfer Curve SOURCING CURRENT 15 10 5 VS = ±15V AV = –5 1% THD 1k 10k FREQUENCY (Hz) 100k 1970 G47 SINKING CURRENT –300 –400 –500 0 1 3 2 VCSNK = VCSRC (V) 4 5 1970 G50 10k 0 100 Output Stage Quiescent Current vs Supply Voltage IV+ 125°C 25°C –55°C IV – SOURCING CURRENT –55°C 25°C 125°C SINKING CURRENT 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (± V) 16 18 1970 G80 Supply Current vs Supply Voltage in Shutdown VENABLE = 0V 700 600 500 400 300 200 100 0 0 2 4 8 10 12 14 6 SUPPLY VOLTAGE (V) 16 18 85°C 25°C –55°C –55°C 25°C 125°C 1970 G81 1970 G82 1970f LT1970 PI FU CTIO S VEE (Pins 1, 10, 11, 20, Package Base): Minus Supply Voltage. VEE connects to the substrate of the integrated circuit die, and therefore must always be the most negative voltage applied to the part. Decouple VEE to ground with a low ESR capacitor. VEE may be a negative voltage or it may equal ground potential. Any or all of the VEE pins may be used. Unused VEE pins must remain open. V– (Pin 2): Output Stage Negative Supply. V– may equal VEE or may be smaller in magnitude. Only output stage current flows out of V–, all other current flows out of VEE. V– may be used to drive the base/gate of an external power device to boost the amplifier’s output current to levels above the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V– should be decoupled to ground with a low ESR capacitor. OUT (Pin 3): Amplifier Output. The OUT pin provides the force function as part of a Kelvin sensed load connection. OUT is normally connected directly to an external load current sense resistor and the SENSE+ pin. Amplifier feedback is directly connected to the load and the other end of the current sense resistor. The load connection is also wired directly to the SENSE– pin to monitor the load current. The OUT pin is current limited to ± 800mA typical. This current limit protects the output transistor in the event that connections to the external sense resistor are opened or shorted which disables the precision current limit function. SENSE + (Pin 4): Positive Current Sense Pin. This lead is normally connected to the driven end of the external sense resistor. Positive current limit operation is activated when the voltage VSENSE (VSENSE + – VSENSE –) equals 1/10 of the programming control voltage at VCSRC (Pin 13). Negative current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12). FILTER (Pin 5): Current Sense Filter Pin. This pin is normally not used and should be left open in most applications. When very large capacitive loads are driven, a filter capacitor connected between FILTER and SENSE+ will reduce overshoot as the amplifier enters current limiting mode. The filter time constant is set by an internal 1k resistor and the external filter capacitor. Capacitor values of 1nF to 100nF are most effective at reducing overshoot. SENSE – (Pin 6): Negative Current Sense Pin. This pin is normally connected to the load end of the external sense resistor. Positive current limit operation is activated when the voltage VSENSE (VSENSE + – VSENSE –) equals 1/10 of the programming control voltage at VCSRC (Pin 13). Negative current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12). VCC (Pin 7): Positive Supply Voltage. All circuitry except the output transistors draw power from VCC. Total supply voltage from VCC to VEE must be between 3.5V and 36V. VCC must always be greater than or equal to V+. VCC should always be decoupled to ground with a low ESR capacitor. – IN (Pin 8): Inverting Input of Amplifier. – IN may be any voltage from VEE – 0.3V to VEE + 36V. – IN and + IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to insure that – IN or + IN can never go to a voltage below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to – IN can provide clamping if other elements in the circuit can allow – IN to go below VEE. + IN (Pin 9): Noninverting Input of Amplifier. + IN may be any voltage from VEE – 0.3V to VEE + 36V. – IN and + IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to insure that – IN or + IN can never go to a voltage below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to +IN can provide clamping if other elements in the circuit can allow + IN to go below VEE. U U U 1970f 7 LT1970 PI FU CTIO S VCSNK (Pin 12): Sink Current Limit Control Voltage Input. The current sink limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals –1.0 • VVCSNK/10. VCSNK may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSNK and VSENSE is linear except for very small input voltages at VCSNK < 60mV. VSENSE limits at a minimum set point of 4mV typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low. VCSRC (Pin 13): Source Current Limit Control Voltage Input. The current source limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals VVCSRC/10. VCSRC may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSRC and VSENSE is linear except for very small input voltages at VCSRC < 60mV. VSENSE limits at a minimum set point of 4mV typical to insure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low. COMMON (Pin 14): Control and ENABLE inputs and flag outputs are referenced to the COMMON pin. COMMON may be at any potential between VEE and VCC – 3V. In typical applications, COMMON is connected to ground. ENABLE (Pin 15): ENABLE Digital Input Control. When taken low this TTL-level digital input turns off the amplifier output and drops supply current to less than 1mA. Use the ENABLE pin to force zero output current. Setting VCSNK = VCSRC = 0V allows IOUT = ± 4mV/RSENSE to flow in or out of VOUT. ISRC (Pin 16): Sourcing Current Limit Digital Output Flag. ISRC is an open collector digital output. ISRC pulls low whenever the sourcing current limit amplifier assumes control of the output. This pin can sink up to 10mA of current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISRC may be left open if this function is not monitored. ISNK (Pin 17): Sinking Current Limit Digital Output Flag. ISNK is an open collector digital output. ISNK pulls low whenever the sinking current limit amplifier assumes control of the output. This pin can sink up to 10mA of current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISNK may be left open if this function is not monitored. TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD is an open collector digital output. TSD pulls low whenever the internal thermal shutdown circuit activates, typically at a die temperature of 160°C. This pin can sink up to 10mA of output current. The TSD flag is off when the die temperature is within normal operating temperatures. ISRC, ISNK and TSD may be wired “OR” together if desired. ISNK may be left open if this function is not monitored. Thermal shutdown activation should prompt the user to evaluate electrical loading or thermal environmental conditions. V+ (Pin 19): Output Stage Positive Supply. V + may equal VCC or may be smaller in magnitude. Only output stage current flows through V +, all other current flows into VCC. V + may be used to drive the base/gate of an external power device to boost the amplifier’s output current to levels above the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V + should be decoupled to ground with a low ESR capacitor. Package Base: The exposed backside of the package is electrically connected to the VEE pins on the IC die. The package base should be soldered to a heat spreading pad on the PC board that is electrically connected to VEE. 8 U U U 1970f LT1970 BLOCK DIAGRA RFB 1k 9 +IN + – RG 1k VIN 8 10k 17 16 10k 10k –IN ISNK D1 ISINK 15 5V 12 ENABLE VCSNK VCSRC ENABLE D2 13 VCSRC ISRC 14 COMMON APPLICATIO S I FOR ATIO The LT1970 power op amp with precision controllable current limit is a flexible voltage and current source module. The drawing on the front page of this data sheet is representative of the basic application of the circuit, however many alternate uses are possible with proper understanding of the subcircuit capabilities. CIRCUIT DESCRIPTION Main Operational Amplifier Subcircuit block GM1, the 1X unity-gain current buffer and output transistors Q1 and Q2 form a standard operational amplifier. This amplifier has ± 500mA current output capability and a 3.6MHz gain bandwidth product. Most applications of the LT1970 will use this op amp in the main signal path. All conventional op amp circuit configurations are supported. Inverting, noninverting, filter, summation or nonlinear circuits may be implemented in a conventional manner. The output stage includes current limiting at ± 800mA to protect against fault conditions. The input stage has high differential breakdown of 36V minimum between – IN and + IN. No current will flow at the inputs when differential input voltage is present. This feature is important when the precision current sense amplifiers “ISINK” and “ISRC” become active. Current Limit Amplifiers Amplifier stages “ISINK” and “ISRC” are very high transconductance amplifier stages with independently controlled offset voltages. These amplifiers monitor the voltage between input pins SENSE+ and SENSE– which usually sense the voltage across a small external current sense resistor. The transconductance amplifiers outputs connect to the same high impedance node as the main input stage GM1 amplifier. Small voltage differences between SENSE+ and SENSE–, smaller than the user set VCSNK/10 and VCSRC/10 in magnitude, cause the current limit amplifiers to decouple from the signal path. This is functionally indicated by diodes D1 and D2 in the Block Diagram. When the voltage VSENSE increases in magnitude sufficient to equal or overcome one of the offset voltages VCSNK/10 or VCSRC/10, the appropriate current limit amplifier becomes 1970f – VCSNK + 15V 18 TSD – ISRC + U W UW + – A D TEST CIRCUIT VCC V+ 19 Q1 GM1 1× Q2 PS1 OUT 3 15V 7 + – + – VSNK SENSE+ FILTER SENSE – RFIL 1k RCS 1Ω 4 5 6 RLOAD 1k VSRC V– 2 VEE 2, 10, 11, 20 –15V 1970TC UU 9 LT1970 APPLICATIO S I FOR ATIO active and because of its very high transconductance, takes control from the input stage, GM1. The output current is regulated to a value of IOUT = VSENSE /RSENSE = (VCSRC or VCSNK)/(10 • RSENSE). Most applications will connect pins SENSE+ and OUT together, with the load on the opposite side of the external sense resistor and pin SENSE–. Feedback to the inverting input of GM1 should be connected from SENSE– to – IN. The common mode range of stages “ISINK” and “ISRC” allow other connections. Ground side sensing of load current may be employed by connecting the load between pins OUT and SENSE+. Pin SENSE– would be connected to ground in this instance. Load current would be regulated in exactly the same way as the conventional connection. However, voltage mode accuracy would be degraded in this case due to the voltage across RSENSE. Creative applications are possible where pins SENSE+ and SENSE– monitor a parameter other than load current. The operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from GM1, can be used for many different signals. Current Limit Threshold Control Buffers Input pins VCSNK and VCSRC are used to set the response thresholds of current limit amplifiers “ISINK” and “ISRC”. Each of these inputs may be independently driven by a voltage of 0V to 5V above the COMMON reference pin. The 0V to 5V input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit amplifier. AC signals may be applied to these pins. The AC bandwidth from a VC pin to the output is typically 2MHz. The transfer function from VC to the associated VOS is linear from about 0.1V to 5V in, or 10mV to 500mV at the current limit amplifier inputs. An intentional nonlinearity is built into the transfer functions at low levels. This nonlinearity insures that both the sink and source limit amplifiers cannot become active simultaneously. Simultaneous activation of the limit amplifiers could result in uncontrolled outputs. As shown in the Typical Performance Characteristics curves, the control inputs have a “hockey stick” shape, to keep the minimum limit threshold at 4mV for each limit amplifier. 10 U ENABLE Control The ENABLE input pin puts the LT1970 into a low supply current, high impedance output state. The ENABLE pin responds to TTL threshold levels with respect to the COMMON pin. Pulling the ENABLE pin low is the best way to force zero current at the output. Setting VCSNK = VCSRC = 0V allows the output current to remain as high as ± 4mV/RSENSE. Operating Status Flags The LT1970 has three digital output indicators; TSD, ISRC and ISNK. These outputs are open collector drivers referred to the COMMON pin. The outputs have 36V capabilities and can sink in excess of 10mA. ISRC and ISNK indicate activation of the associated current limit amplifier. The TSD output indicates excessive die temperature has caused the circuit to enter thermal shutdown. The three digital outputs may be wire “OR’d” together, monitored individually or left open. These outputs do not affect circuit operation, but provide an indication of the present operational status of the chip. THERMAL MANAGEMENT Minimizing Power Dissipation The LT1970 can operate with up to 36V total supply voltage with output currents up to ± 500mA. The amount of power dissipated in the chip could approach 18W under worst-case conditions. This amount of power will cause die temperature to rise until the circuit enters thermal shutdown. While the thermal shutdown feature prevents damage to the circuit, normal operation is impaired. Thermal design of the LT1970 operating environment is essential to getting maximum utility from the circuit. The first concern for thermal management is minimizing the heat which must be dissipated. The separate power pins V+ and V– can be a great aid in minimizing on-chip power. The output pin can swing to within 1.0V of V+ or V– even under maximum output current conditions. Using separate power supplies, or off chip dissipative elements, to set V+ and V– to their minimum values for the required output swing will minimize power dissipation. The supplies VCC and VEE may also be reduced to a minimal value, 1970f W UU LT1970 APPLICATIO S I FOR ATIO but these supply pins do not carry high currents, and the power saving is much less. VCC and VEE must be greater than the maximum output swing by 2V or more. When V – and V+ are provided separately from VCC and VEE, care must be taken to insure that V– and V+ are always less than or equal to the main supplies in magnitude. Protection Schottky diodes may be required to insure this in all cases, including power on/off transients. Operation with reduced V + and V – supplies does not affect any performance parameters except maximum output swing. All DC accuracy and AC performance specifications guaranteed with VCC = V + and VEE = V – are still valid within the reduced signal swing range. Heat Sinking The power dissipated in the LT1970 die must have a path to the environment. With 100°C/W thermal resistance in free air with no heat sink, the package power dissipation is limited to only 1W. The 20-pin TSSOP package with exposed copper underside is an efficient heat conductor if it is effectively mounted on a PC board. Thermal resistances as low as 40°C/W can be obtained by soldering the bottom of the package to a large copper pattern on the PC board. For operation at 85°C, this allows up to 1.625W of power to be dissipated on the LT1970. At 25°C operation, up to 3.125W of power dissipation can be achieved. The PC board heat spreading copper area must be connected to VEE. DRIVING REACTIVE LOADS Capacitive Loads The LT1970 is much more tolerant of capacitive loading than most operational amplifiers. In a worst-case configuration as a voltage follower, the circuit is stable for capacitive loads less than 2.5nF. Higher gain configurations improve the CLOAD handling. If very large capacitive loads are to be driven, a resistive decoupling of the amplifier from the capacitive load is effective in maintaining stability Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U and reducing peaking. The current sense resistor, usually connected between the output pin and the load can serve as a part of the decoupling resistance. Very large capacitive loads above 1µF can also cause transient overshoots when the current limiting circuits activate. The FILTER pin is provided to assist in controlling this problem. Should load capacitance cause transient overshoot, a 1nF to 100nF capacitor between the FILTER and SENSE– pins will minimize the overshoot. The best value of capacitor to use in this situation will likely require some empirical evaluation, as the optimum is a complex function of output current, load resistance, sense resistor and load capacitance. Inductive Loads Load inductance is usually not a problem at the outputs of operational amplifiers, but the LT1970 can be used as a high output impedance current source. This condition may be the main operating mode, or when the circuit enters a protective current limit mode. Just as load capacitance degrades the phase margin of normal op amps, load inductance causes a peaking in the loop response of the feedback controlled current source. The inductive load may be caused by long lead lengths at the amplifier output. If the amplifier will be driving inductive loads or long lead lengths (greater than 4 inches) a 500pF capacitor from the SENSE– pin to the ground plane will cancel the inductive load and insure stability. Supply Bypassing The LT1970 can supply large currents from the power supplies to a load at frequencies up to 4MHz. Power supply impedance must be kept low enough to deliver these currents without causing supply rails to droop. Low ESR capacitors, such as 0.1µF or 1µF ceramics, located close to the pins are essential in all applications. When large, high speed transient currents are present additional capacitance may be needed near the chip. Check supply rails with a scope and if signal related ripple is seen on the supply rail, increase the decoupling capacitor as needed. 1970f W UU 11 LT1970 TYPICAL APPLICATIO AV = – 1 Amplifier with Discrete Power Devices to Boost Output Current to 5A CURRENT LIMIT CONTROL VOLTAGE 0V TO 5V VCC 15V 100Ω IRF9640 1k VCC ENABLE VCSRC +IN VCSNK V+ SENSE+ SENSE– COMMON V– LT1970 OUT 100Ω RCS 0.1Ω 5W LOAD 2.2k VIN IRF9540 100Ω VEE –15V 10µF 0.1µF 1970 TA03 PACKAGE DESCRIPTIO 6.60 ± 0.10 4.50 ± 0.10 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC RECOMMENDED SOLDER PAD 4.30 – 4.48* (.169 – .176) 0° – 8° 0.65 (.0256) BSC EXPOSED PAD HEAT SINK ON BOTTOM OF 0.05 – 0.15 PACKAGE (.002 – .006) 1.15 (.0453) MAX 6.40 – 6.60* (.252 – .260) 5.2 (.205) 20 1918 17 16 15 14 13 12 11 0.105 – 0.180 (.0041 – .0071) 0.50 – 0.70 (.020 – .028) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .150mm (.006") PER SIDE RELATED PARTS PART NUMBER LT1010 LT1206 LT1210 DESCRIPTION Fast ±150mA Power Buffer 250mA/60MHz Current Feedback Amplifier 1.1A/35MHz Current Feedback Amplifier COMMENTS Shutdown Mode, Adjustable Supply Current Stable with CL = 10,000pF 1970f LT/TP 0102 2K • PRINTED IN USA 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U U 10µF 0.1µF 100Ω –IN VEE 2.2k FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663, Exposed Pad Variation CA) 0.195 – 0.30 (.0077 – .0118) 3.0 6.25 – 6.50 (.118) (.246 – .256) 1 2 3 4 5 6 7 8 9 10 FE20 TSSOP 1101 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2002