LT3028EDHC

LT3028 Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulators with Independent Inputs FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Noise: 20µVRMS (10Hz to 100kHz) Low Quiescent Current: 30µA/Output Independent Inputs Wide Input Voltage Range: 1.8V to 20V Output Current: 100mA/500mA Very Low Shutdown Current: 3300pF Figure 2. Output 2 Stability 20 0 CHANGE IN VALUE (%) BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF CHANGE IN VALUE (%) X5R –20 –40 –60 Y5V –80 –100 0 2 4 8 6 10 12 DC BIAS VOLTAGE (V) 14 16 3028 F04 Figure 4. Ceramic Capacitor DC Bias Characteristics 12 U Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and temperature coefficients as shown in Figures 4 and 5. When used with a 5V regulator, a 10µF Y5V capacitor can exhibit an effective value as low as 1µF to 2µF over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. 4.0 3.5 3.0 STABLE REGION 2.5 2.0 1.5 1.0 0.5 0 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (µF) 3028 F03 W UU CBYP = 0 CBYP = 100pF CBYP = 330pF CBYP ≥ 1000pF Figure 3. Output 1 Stability 40 20 0 –20 –40 –60 –80 Y5V X5R BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF –100 50 25 75 –50 –25 0 TEMPERATURE (°C) 100 125 3028 F05 Figure 5. Ceramic Capacitor Temperature Characteristics 3028f LT3028 APPLICATIO S I FOR ATIO Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 6’s trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise. COUT = 10µF CBYP = 0.01µF ILOAD = 100mA VOUT 500µV/DIV 100ms/DIV 3028 F05 Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125°C). The power dissipated by the device will be made up of two components for each output: 1. Output current multiplied by the input/output voltage differential: (IOUT)(VIN – VOUT), and 2. GND pin current multiplied by the input voltage: (IGND)(VIN). The ground pin current can be found by examining the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation will be equal to the sum of the two components listed above. The LT3028 regulator has internal thermal limiting designed to protect the device during overload conditions. U For continuous normal conditions, the maximum junction temperature rating of 125°C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper. Table 1. FE Package, 16-Lead TSSOP COPPER AREA TOPSIDE* BACKSIDE 2500mm2 1000mm 225mm 2 2 W UU BOARD AREA 2500mm2 2500mm 2500mm 2 2 THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 38°C/W 43°C/W 48°C/W 60°C/W 2500mm2 2500mm 2500mm 2 2 100mm2 2500mm2 2500mm2 *Device is mounted on topside. Table 2. DHC Package, 16-Lead DFN COPPER AREA TOPSIDE* BACKSIDE 2500mm2 1000mm 225mm 100mm 2 2 2 BOARD AREA 2500mm2 2500mm2 2500mm 2500mm 2 2 THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 40°C/W 45°C/W 50°C/W 62°C/W 2500mm2 2500mm 2500mm 2500mm 2 2 2 *Device is mounted on topside. The thermal resistance junction-to-case (θJC), measured at the Exposed Pad on the back of the die is 10°C/W for the DFN package and 8°C/W for the TSSOP package. Calculating Junction Temperature Example: Given Output 1 set for an output voltage of 3.3V, Output 2 set for an output voltage of 2.5V, an input voltage range of 3.8V to 5V, an output current range of 0mA to 500mA for Output 1, an output current range of 0mA to 100mA for Output 2 and a maximum ambient temperature of 50°C, what will the maximum junction temperature be? 3028f 13 LT3028 APPLICATIONS INFORMATION The power dissipated by each output will be equal to: IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX)) Where for Output 1: IOUT(MAX) = 500mA VIN(MAX) = 5V IGND at (IOUT = 500mA, VIN = 5V) = 9mA For Output 2: IOUT(MAX) = 100mA VIN(MAX) = 5V IGND at (IOUT = 100mA, VIN = 5V) = 2mA So for Output 1: P = 500mA (5V – 3.3V) + 9mA (5V) = 0.90W For Output 2: P = 100mA (5V – 2.5V) + 2mA (5V) = 0.26W The thermal resistance will be in the range of 35°C/W to 55°C/W depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: (0.90W + 0.26W) 50°C/W = 57.8°C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 50°C + 57.8°C = 107.8°C Protection Features The LT3028 regulator incorporates several protection features which make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input voltages and reverse voltages from output to input. The two regulators have common inputs and GND pins and are thermally coupled, however, the two outputs of the LT3028 operate independently. They can be shut down independently and a fault condition on one output will not affect the other output electrically. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C. The input of the device will withstand reverse voltages of 20V. Current flow into the device will be limited to less than 1mA (typically less than 100µA) and no negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries which can be plugged in backward. The output of the LT3028 can be pulled below ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by 20V. The output will act like an open circuit; no current will flow out of the pin. If the input is powered by a voltage source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. In this case, grounding the SHDN1/SHDN2 pins will turn off the device and stop the output from sourcing the short-circuit current. The ADJ pins can be pulled above or below ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. In situations where the ADJ pins are connected to a resistor divider that would pull the pins above their 7V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ pin is at 7V. The 13V difference between output and ADJ pin divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 2.6k. 14 U W U U 3028f LT3028 APPLICATIONS INFORMATION In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. When the IN pin of the LT3028 is forced below either OUT pin or either OUT pin is pulled above the IN pin, input current for the corresponding regulator will typically drop to less than 2µA. This can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN1/SHDN2 pin will have no effect on the reverse output current when the output is pulled above the input. PACKAGE DESCRIPTIO FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) 3.58 (.141) 6.60 ± 0.10 4.50 ± 0.10 SEE NOTE 4 2.94 (.116) 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC 2.94 6.40 (.116) (.252) BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U W U U Exposed Pad Variation BB 4.90 – 5.10* (.193 – .201) 3.58 (.141) 16 1514 13 12 1110 9 12345678 1.10 (.0433) MAX 0° – 8° 0.25 REF 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE16 (BB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3028f 15 LT3028 PACKAGE DESCRIPTIO 3.50 ± 0.05 1.65 ± 0.05 (2 SIDES) 2.20 ± 0.05 0.25 ± 0.05 0.50 BSC 4.40 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS RELATED PARTS PART NUMBER LT1129 LT1175 DESCRIPTION 700mA, Micropower, LDO 500mA, Micropower Negative LDO COMMENTS VIN: 4.2V to 30V, VOUT(MIN) = 3.75V, IQ = 50µA, ISD < 16µA, DD, SOT-223, S8,TO220, TSSOP20 Packages Guaranteed Voltage Tolerance and Line/Load Regulation VIN: –20V to –4.3V, VOUT(MIN) = – 3.8V, IQ = 45µA, ISD < 10µA, DD,SOT-223, S8 Packages Accurate Programmable Current Limit, Remote Sense VIN: –35V to –4.2V, VOUT(MIN) = – 2.40V, IQ = 2.5mA, ISD < 1µA, TO220-5 Package Low Noise < 20µVRMS, Stable with 1µF Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 20µA, ISD < 1µA, ThinSOT Package Low Noise < 20µVRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 25µA, ISD < 1µA, MS8 Package Low Noise < 20µVRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30µA, ISD < 1µA, S8 Package Low Noise < 40µVRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.7V to 20V, VOUT(MIN) = 1.21V, IQ = 1mA, ISD < 1µA, DD, TO220 Packages Low Noise < 30µVRMS, Stable with 1µF Ceramic Capacitors, VIN: 1.6V to 6.5V, VOUT(MIN) = 1.25V, IQ = 40µA, ISD < 1µA, ThinSOT Package Low Noise < 20µVRMS, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30µA, ISD < 1µA, MS8 Package Low Noise < 40µVRMS, "A" Version Stable with Ceramic Capacitors, VIN: 2.1V to 20V, VOUT(MIN) = 1.21V, IQ = 1mA, ISD < 1µA, DD, TO220, SOT-223, S8 Packages Low Noise < 30µVRMS, Stable with Ceramic Capacitors, VIN: –0.9V to –20V, VOUT(MIN) = – 1.21V, IQ = 30µA, ISD < 3µA, ThinSOT Package Low Noise < 20µVRMS, Stable with 1µF Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 40µA, ISD < 1µA, MS10E, DFN Packages Low Noise < 20µVRMS, Stable with 1µF Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, IQ = 30µA, ISD < 1µA, DFN, TSSOP Packages 3028f LT1185 LT1761 LT1762 LT1763 LT1764/LT1764A LTC1844 LT1962 LT1963/LT1963A 3A, Negative LDO 100mA, Low Noise Micropower, LDO 150mA, Low Noise Micropower, LDO 500mA, Low Noise Micropower, LDO 3A, Low Noise, Fast Transient Response, LDO 150mA, Very Low Drop-Out LDO 300mA, Low Noise Micropower, LDO 1.5A, Low Noise, Fast Transient Response, LDO LT1964 LT3023 LT3024 200mA, Low Noise Micropower, Negative LDO Dual 100mA, Low Noise, Micropower LDO Dual 100mA/500mA, Low Noise, Micropower LDO 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 5.00 ± 0.10 (2 SIDES) 0.65 ± 0.05 3.00 ± 0.10 (2 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH (DHC16) DFN 1103 R = 0.115 TYP R = 0.20 TYP 9 16 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 8 0.200 REF 0.75 ± 0.05 4.40 ± 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD 1 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE LT/TP 0904 1K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004