LT3070IUFDPBF

Electrical Specifications Subject to Change LT3070 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator FEATURES n n n n n n n n n n n n n n n n DESCRIPTION The LT®3070 is a low voltage, UltraFast™ transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01μF reference bypass capacitor decreases output voltage noise to 25μVRMS. The LT3070’s high bandwidth permits the use of low ESR ceramic capacitors, saving bulk capacitance and cost. The LT3070’s features make it ideal for high performance FPGAs, microprocessors or sensitive communication supply applications. Output voltage is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to tolerance system output voltage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function to control a buck regulator powering the LT3070’s input. This tracking function drives the buck regulator to maintain the LT3070’s input voltage to VOUT + 300mV, minimizing power dissipation. Internal protection includes UVLO, reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3070 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. UltraFast is a trade mark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Output Current: 5A Dropout Voltage: 85mV Typical Digitally Programmable VOUT : 0.8V to 1.8V Digital Output Margining: ±1%, ±3% or ±5% Low Output Noise: 25μVRMS (10Hz to 100kHz) Parallelable: Use Two for a 10A Output Precision Current Limit: ±10% ±1% Accuracy Over Line, Load and Temperature Stable with Low ESR Ceramic Output Capacitors (15μF Minimum) High Frequency PSRR: 35dB at 1MHz Enable Function Turns Output On/Off VIOC Pin Controls Buck Converter to Maintain Low Power Dissipation and Optimize Efficiency PWRGD/UVLO Flag Current Limit Foldback Protection Thermal Shutdown 28-Lead (4mm × 5mm) QFN Package APPLICATIONS n n n n FPGA and DSP Supplies ASIC and Microprocessor Supplies Servers and Storage Devices Post Buck Regulation and Supply Isolation TYPICAL APPLICATION 0.9V, 5A Regulator VBIAS 2.2V TO 3.6V 50k PWRGD 2.2μF 4 Dropout Voltage VIN 1.2V BIAS IN 330μF EN VO0 VO1 VO2 MARGSEL MARGTOL VIOC 1nF REF/BYP GND 0.01μF 3070 TA01a PWRGD SENSE LT3070 OUT 2.2μF 4.7μF 10μF VOUT 0.9V 5A 3 XXX 2 PLACE HOLDER 1 0 0 10 20 XXX 30 40 LTXXXX • TPCXX 3070p 1 LT3070 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW BIAS GND VO2 VO1 GND VO0 22 MARGTOL 21 MARGSEL 20 GND 29 19 SENSE 18 OUT 17 OUT 16 OUT 15 OUT 9 10 11 12 13 14 GND GND GND GND GND EN VIOC 1 PWRGD 2 REF/BYP 3 GND 4 IN 5 IN 6 IN 7 IN 8 28 27 26 25 24 23 IN, OUT ......................................................... 3.3V, –0.3V BIAS ................................................................. 4V, –0.3V VO2, VO1, VO0 Inputs ........................................ 4V, –0.3V MARGSEL, MARGTOL Input ............................ 4V, –0.3V EN Input ........................................................... 4V, –0.3V SENSE Input .................................................... 4V, –0.3V VIOC, PWRGD Outputs .................................... 4V, –0.3V REF/BYP Output ............................................... 4V, –0.3V Output Short-Circuit Duration……...................Indefinite Operating Junction Temperature (Note 2) LT3070E/LT3070I .............................. –40°C to 125°C LT3070MP......................................... –55°C to 125°C Storage Temperature Range................... –65°C to 150°C UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 30°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LT3070EUFD#PBF LT3070IUFD#PBF LT3070MPUFD#PBF LEAD BASED FINISH LT3070EUFD LT3070IUFD LT3070MPUFD TAPE AND REEL LT3070EUFD#TRPBF LT3070IUFD#TRPBF LT3070MPUFD#TRPBF TAPE AND REEL LT3070EUFD#TR LT3070IUFD#TR LT3070MPUFD#TR PART MARKING* 3070 3070 070MP PART MARKING* 3070 3070 070MP PACKAGE DESCRIPTION 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN PACKAGE DESCRIPTION 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –55°C to 125°C TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3070p 2 LT3070 ELECTRICAL CHARACTERISTICS PARAMETER Minimum IN Pin Voltage Minimum BIAS Pin Voltage (Note 3) Regulated Output Voltage VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1V ≤ VIN ≤ 1.25V VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.1V ≤ VIN ≤ 1.35V VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.2V ≤ VIN ≤ 1.45V VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.3V ≤ VIN ≤ 1.55V VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.4V ≤ VIN ≤ 1.65V VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.7V ≤ VIN ≤ 1.95V VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.0V ≤ VIN ≤ 2.25V MARGTOL = 0V, MARGSEL = VBIAS MARGTOL = 0V, MARGSEL = 0V, IOUT = 10mA MARGTOL = FLOAT, MARGSEL = VBIAS MARGTOL = FLOAT, MARGSEL = 0V, IOUT = 10mA MARGTOL = VBIAS, MARGSEL= VBIAS MARGTOL = VBIAS, MARGSEL = 0V, IOUT = 10mA Line Regulation to VIN Line Regulation to VBIAS Load Regulation, ΔIOUT = 10mA to 5A VOUT = 0.8V, ΔVIN = 1.1V to 3.0V, VBIAS = 3.3V, IOUT = 10mA VOUT = 1.8V, ΔVIN = 2.1V to 3.0V, VBIAS = 3.3V, IOUT = 10mA VOUT = 0.8V, ΔVBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA VOUT = 1.8V, ΔVBIAS = 3.1V to 3.6V, VIN = 2.1V, IOUT = 10mA VBIAS = 3.3V, VIN = 1.1V, VOUT = 0.8V VBIAS = 3.3V, VIN = 1.3V, VOUT = 1.0V VBIAS = 3.3V, VIN = 1.5V, VOUT = 1.2V VBIAS = 3.3V, VIN = 1.8V, VOUT = 1.5V VBIAS = 3.3V, VIN = 2.1V, VOUT = 1.8V Dropout Voltage, VIN = VOUT(NOMINAL) (Note 6) IOUT = 1A IOUT = 2.5A IOUT = 5A SENSE Pin Current Ground Pin Current, VIN = 1.3V, VOUT = 1V VBIAS = 3.3V, VIN = 1.1V, VOUT = 0.8 VBIAS = 3.3V, VIN = 2.1V, VOUT = 1.8V IOUT = 10mA IOUT = 5A CONDITIONS VIN ≥ VOUT + 150mV, IOUT= 5A l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. MIN 0.95 2.2 0.792 0.891 0.990 1.089 1.189 1.485 1.782 0.7 –1.3 2.7 –3.3 4.7 –5.3 0.800 0.900 1.000 1.100 1.200 1.500 1.800 1 –1 3 –3 5 –5 TYP MAX 3.0 3.6 0.808 0.909 1.010 1.111 1.212 1.515 1.818 1.3 –0.7 3.3 –2.7 5.3 –4.7 1.0 1.0 2.0 1.0 –1.5 –1.5 –1.8 –2.3 –2.7 –3.0 –5.0 –3.0 –5.0 –3.6 –6.0 –4.5 –7.5 –5.4 –9.0 20 45 85 35 210 0.45 0.62 50 300 0.72 0.88 55 63 105 150 65 390 1.15 1.45 UNITS V V V V V V V V V % % % % % % mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV μA μA mA mA Regulated Output Voltage Margining (Note 3) 3070p 3 LT3070 ELECTRICAL CHARACTERISTICS PARAMETER BIAS Pin Current in Nap Mode BIAS Pin Current, VIN = 1.3V, VOUT = 1V CONDITIONS EN = Low (After POR Completed) IOUT = 10mA IOUT = 100mA IOUT = 500mA IOUT = 1A IOUT = 2.5A IOUT = 5A VIN – VOUT < 0.5V VIN – VOUT = 0.6V VIN – VOUT = 1.0V VIN – VOUT = 1.5V VIN = 0V, VOUT = 3V Percentage of VOUT(NOMINAL), VOUT Rising Percentage of VOUT(NOMINAL), VOUT Falling IPWRGD = 200μA (Fault Condition) EN = 3.3V, VBIAS Rising EN = 3.3V, VBIAS Falling VIN = VOUT(NOMINAL) + 150mV, Sourcing VIN = VOUT(NOMINAL) + 450mV, Sinking Input Falling l l l l l l l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. MIN 300 1.20 2.05 2.75 3.40 4.85 5.20 5.2 4.8 3.4 1.0 200 87.5 83.5 1.11 0.96 250 175 175 0.22 0.75 2.00 40 52 27 26 90 86 1.50 1.30 300 256 256 0.42 1.76 2.25 70 43 38 1.35 0.94 3.8 5.0 7.1 0.1 TYP 420 1.80 2.60 3.70 4.60 6.40 7.25 MAX 650 2.40 3.70 5.45 6.80 9.40 11.45 6 5.2 4.4 1.8 400 92.5 88.5 100 2.03 1.62 350 335 335 UNITS μA mA mA mA mA mA mA A A A A μA % % mV V V mV μA μA V V V mV μA μA V V μA μA Current Limit (Note 5) Reverse Output Current (Note 8) PWRGD VOUT Threshold PWRGD VOL VBIAS Undervoltage Lockout VIN-VOUT Servo Voltage by VIOC VIOC Output Current VIL Input Threshold (Logic-0 State), VO2, VO1, VO0, MARGSEL, MARGTOL VIZ Input Range (Logic-Z State), VO2, VO1, VO0, MARGSEL, MARGTOL VIH Input Threshold (Logic-1 State), VO2, VO1, VO0, MARGSEL, MARGTOL Input Hysteresis (Both Thresholds), VO2, VO1, VO0, MARGSEL, MARGTOL Input Current High, VO2, VO1, VO0, MARGSEL, MARGTOL Input Current Low, VO2, VO1, VO0, MARGSEL, MARGTOL EN Pin Threshold EN Pin Logic High Current EN Pin Logic Low Current Input Rising l l VIH = VBIAS = 2.5V, Current Flows Into Pin VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin VOUT = Off to On VOUT = On to Off VEN = VBIAS = 2.5V VEN = 0V l l l l l l 3070p 4 LT3070 ELECTRICAL CHARACTERISTICS PARAMETER VBIAS Ripple Rejection VIN Ripple Rejection (Notes 3, 4, 5) Reference Voltage Noise (REF/BYP Pin) Output Voltage Noise CONDITIONS VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz, VIN – VOUT = 300mV, IOUT = 2.5A VBIAS = 2.5V, VIN – VOUT = 300mV, IOUT = 2.5A, VRIPPLE = 50mVP-P , fRIPPLE = 120Hz , CREF/BYP = 10nF BW = 10Hz to 100kHz VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF COUT = 15μF , , BW = 10Hz to 100kHz The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. MIN 60 60 TYP 72 68 10 25 MAX UNITS dB dB μVRMS μVRMS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3070 regulators are tested and specified under pulse load conditions such that TJ ≅ TA. The LT3070E is 100% tested at TA = 25°C. Performance at –40°C and 125°C is assured by design, characterization and correlation with statistical process controls. The LT3070I is guaranteed over the –40°C to 125°C operating junction temperature range. The LT3070MP is 100% tested and guaranteed over the –55°C to 125°C operating junction temperature range. Note 3: To maintain proper performance and regulation, the BIAS supply voltage must be higher than the IN supply voltage. For a given VOUT , the BIAS voltage must be in the range: (1.2 • VOUT + 935mV) ≤ VBIAS ≤ 3.6V. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. When operating at maximum output current, limit the input voltage range to: VIN < VOUT + 500mV. Note 5: The LT3070 incorporates safe operating area protection circuitry. Current limit decreases as the VIN-VOUT voltage increases. Current limit foldback starts at VIN – VOUT > 500mV. See the Typical Performance Characteristics for a graph of Current Limit vs VIN – VOUT voltage. The current limit foldback feature is independent of the thermal shutdown circuity. Note 6: Dropout voltage, VDO, is the minimum input to output voltage differential at a specified output current. In dropout, the output voltage equals VIN – VDO. Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a current source load. VIOC is a buffered output determined by the value of VOUT as programmed by the VO2-VO0 pins. VIOC’s output is independent of the margining function. Note 8: Reverse output current is tested with the IN pins grounded and the OUT + SENSE pins forced to the rated output voltage. This is measured as current into the OUT + SENSE pins. Note 9: Frequency Compensation: The LTC3070 must be frequency compensated at its OUT pins with a minimum COUT of 15μF configured as a cluster of (15×) 1μF ceramic capacitors or as a graduated cluster of 10μF/4.7μF/2.2μF ceramic capacitors of the same case size. Linear Technology only recommends X5R or X7R dielectric capacitors. 3070p 5 LT3070 TYPICAL PERFORMANCE CHARACTERISTICS VOUT Distribution VOUT vs Temperature Load Regulation Dropout Voltage vs VIN Dropout Voltage vs VBIAS Load Transient Response Current Limit vs VIN Output Voltage Noise 3070p 6 LT3070 TYPICAL PERFORMANCE CHARACTERISTICS Ripple Rejection vs VIN Ripple Rejection vs VBIAS Minimum VIN vs Temperature Line Transient Response vs VIN Line Transient Response vs VBIAS Noise vs Output Voltage BIAS Pin Current vs Load GND Pin Current vs Load 3070p 7 LT3070 PIN FUNCTIONS VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck regulator powering the LT3070’s input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3070’s input voltage at VOUT + 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information section for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that is active low if any one of these fault modes is detected: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT • VOUT drops below 85% of VOUT(NOMINAL) for more than 25μs • Junction temperature exceeds 145°C See the Applications Information section for more information on PWRGD fault modes. REF/BYP (Pin 3): Reference Filter. The pin is the output of the bandgap reference and has an impedance of approximately 19kΩ. This pin must not be externally loaded. Bypassing the REF/BYP pin to GND with a 10nF capacitor decreases output voltage noise and provides a soft-start function to the reference. See the Applications Information section for more information on noise and output voltage margining considerations. GND (Pins 4, 9-14, 20, 26): Ground. All GND pins must be tied together and to Pin 29, the exposed backside of the package for proper thermal performance. These GND pins are fused to the internal die attach paddle and exposed package backside to optimize heat sinking and thermal resistance performance. IN (Pins 5, 6, 7, 8): Input Supply. These pins supply power to the high current pass transistor. Tie all IN pins together for proper performance. The LT3070 requires a bypass capacitor at IN to maintain stability and low input impedance over frequency. A 47μF input bypass capacitor suffices for most battery and power plane impedances. Minimizing input trace inductance optimizes performance. Applications that operate with low VIN-VOUT differential voltages and that have large, fast load transients may require much higher input capacitor requirements to prevent the input supply from drooping and allowing the regulator to enter dropout. See the Applications Information section for more information on input capacitor requirements. OUT (Pins 15, 16, 17, 18): Output. These pins supply power to the load. Tie all OUT pins together for proper performance. A minimum output capacitance of 15μF is required for stability. LTC recommends low ESR, X5R or X7R dielectric ceramic capacitors for best performance. A parallel ceramic capacitor combination of 10μF + 4.7μF + 2.2μF provides excellent stability and load transient response. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitor requirements. SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is the inverting input to the error amplifier. Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of the regulator. In critical applications, the resistance (RP) of PCB traces between the regulator and the load cause small voltage drops, creating a load regulation error at the point of load. Connecting the SENSE pin at the load instead of directly to OUT eliminates this voltage error. Figure 1 illustrates this Kelvin-Sense connection method. Note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50μA typically at VOUT = 0.8V to 300μA typically at VOUT = 1.8V. + VBIAS IN EN VO2 VO1 LT3070 PWRGD LOAD BIAS SENSE OUT RP + VIN VO0 MARGSEL MARGTOL VIOC REF/BYP GND RP 3070 F01 Figure 1. Kelvin Sense Connection 3070p 8 LT3070 PIN FUNCTIONS MARGSEL (Pin 21): Margining Enable and Polarity Selection. This three-state pin determines both the polarity and the active state of the margining function. The logic low threshold is less than 220mV referenced to GND and enables negative voltage margining. The logic “high” threshold is greater than VBIAS – 500mV and enables positive voltage margining. The voltage range between these two logic thresholds defines the logic Hi-Z state and disables the margining function. MARGTOL (Pin 22): Margining Tolerance. This threestate pin selects the absolute value of margining (1%, 3% or 5%) if enabled by the MARGSEL input. The logic low threshold is less than 220mV referenced to GND and enables either ±1% change in VOUT depending on the state of the MARGSEL pin. The logic high threshold is greater than VBIAS – 500mV and enables either ±5% change in VOUT depending on the state of the MARGSEL pin. The voltage range between these two logic thresholds defines the logic Hi-Z state and enables either ±3% change in VOUT depending on the state of the MARGSEL pin. VO2, VO1 and VO0 (Pins 23, 24, 25): Output Voltage Select. These three-state pins combine to select a nominal output voltage from 0.8V to 1.8V in increments of 50mV. Output voltage is limited to 1.8V maximum by an internal override of VO1 when VO2 = “1”. The input logic “0” threshold is less than 220mV referenced to GND and the logic “1” threshold is greater than VBIAS – 500mV. The range between these two thresholds defines the logic Hi-Z state. See Table 1 in the Applications Information section that defines the VO2, VO1 and VO0 settings versus VOUT . BIAS (Pin 27): Bias Supply. This pin supplies current to most of the internal control circuitry and the output stage driving the pass transistor. The LT3070 requires a minimum 2.2μF bypass capacitor for stability and proper operation. To ensure proper operation, the BIAS voltage must conform to the equation: (1.2 • VOUT) + 935mV ≤ VBIAS ≤ 3.6V EN (Pin 28): Enable. This pin starts the internal reference, enables all outputs and enables all support functions. After start-up, pulling the EN pin low keeps the reference circuit active, but disables the output transistor and puts the LT3070 into a lower power “nap” mode. Drive the EN pin with either a digital logic port or an open-collector NPN or open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be no larger than 35k to meet the VIH condition of the EN pin. If unused, connect the EN pin to VBIAS. Exposed Pad (Pin 29): GND. Tie the Exposed Pad to all GND pins and directly to the PCB GND. This Exposed Pad provides enhanced thermal performance with its connection to the PCB GND. See the Applications Information section for thermal considerations and calculating junction temperature. 3070p 9 LT3070 BLOCK DIAGRAM 27 BIAS IN 5-8 UVLO AND THERMAL SHUTDOWN + ISENSE REF/BYP + EAMP – – LDO CORE BUF OUT 15-18 SENSE PWRGD 19 2 DETECT 1 VIOC GND 4,9-14,20,26,29 PROGRAM CONTROL EN 28 10 + – VOUT(NOM) + 300mV VREF REF/BYP 3 VO2 VO1 VO0 MARGSEL MARGTOL 25 24 23 21 22 3070 BD 3070p LT3070 APPLICATIONS INFORMATION Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement. Some ASIC processors require only a single output voltage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power supply voltages for the processor core, the I/O, and the transceivers. Often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. These requirements mandate the need for very accurate, low noise, high current, very high speed regulator circuits that operate at low input and output voltages. The LT3070 is a low voltage, UltraFast transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01μF reference bypass capacitor decreases output voltage noise to 25μVRMS (BW = 10Hz to 100kHz). The LT3070’s high bandwidth provides UltraFast transient response using low ESR ceramic output capacitors (15μF minimum), saving bulk capacitance, PCB area and cost. The LT3070’s features permit state-of-the-art linear regulator performance. The LT3070 is ideal for high performance FPGAs, microprocessors, sensitive communication supplies, and high current logic applications that also operate over low input and output voltages. Output voltage for the LT3070 is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to tolerance system output voltage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function, which if enabled by the user, controls an upsteam regulator powering the LT3070’s input (see Figure 8). This tracking function drives the buck regulator to maintain the LT3070’s input voltage to VOUT + 300mV. This input-to-output voltage control allows the user to change the regulator output voltage, and have the switching regulator powering the LT3070’s input to track to the optimum input voltage with no component changes. This combines the efficiency of a switching regulator with superior linear regulator response. It also permits thermal management of the system even with a maximum 5A output load. LT3070 internal protection includes input undervoltage lockout (UVLO), reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3070 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. The LT3070’s architecture drives an internal N-channel power MOSFET as a source follower. This configuration permits a user to realize an extremely low dropout, UltraFast transient response regulator with excellent high frequency PSRR performance. The LT3070 achieves superior regulator bandwidth and transient load performance by eliminating expensive bulk tantalum or electrolytic capacitors in the most modern and demanding microprocessor applications. Users realize significant cost savings as all additional bulk capacitance is removed. The additional savings of insertion cost, purchasing/inventory cost and board space are readily apparent. Precision incremental output voltage control accommodates legacy and future microprocessor power supply voltages. Output capacitor networks simplify to direct parallel combinations of ceramic capacitors. Often, the high frequency ceramic decoupling capacitors required by these various FPGA and ASIC processors are sufficient to stabilize the system (see Stability and Output Capacitance section). This regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. The LT3070 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection. The LT3070’s unique design combines the benefits of low dropout voltage, high functional integration, precision performance and UltraFast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the LT3070 offers superior regulation and an appreciable 3070p 11 LT3070 APPLICATIONS INFORMATION component cost savings. The LT3070 steps to the next level of performance for the latest generation FPGAs, DSPs and microprocessors. The simple versatility and benefits derived from these circuits exceed the power supply needs of today’s high performance microprocessors. Programming Output Voltage Three tri-level input pins, VO2, VO1 and VO0, select the value of output voltage. Table 1 illustrates the 3-bit digital word to output voltage table resulting from setting these pins high, low or allowing them to float. These pins may be tied high or tied low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has Hi-Z output capability. This allows output voltage to be dynamically changed if necessary. Output voltage is selectable from a minimum of 0.8V to a maximum of 1.8V in increments of 50mV. The MSB, VO2, sets the pedestal voltage, and the LSB’s, VO1 and VO0 increment VOUT . Output voltage is limited to 1.8V maximum by an internal override of VO1 (default to “0”) when VO2 = “1”. Table 1: VO2-VO0 Settings vs Output Voltage VO2 0 0 0 0 0 0 0 0 0 Z Z VO1 0 0 0 Z Z Z 1 1 1 0 0 VO0 0 Z 1 0 Z 1 0 Z 1 0 Z VOUT(NOM) 0.80V 0.85V 0.90V 0.95V 1.00V 1.05V 1.10V 1.15V 1.20V 1.25V 1.30V VO2 Z Z Z Z Z Z Z 1 1 1 VO1 0 Z Z Z 1 1 1 X X X VO0 1 0 Z 1 0 Z 1 0 Z 1 VOUT(NOM) 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V REF/BYP—Voltage Reference This pin is the buffered output of the internal bandgap reference and has an output impedance of ≅19kΩ. The design includes an internal compensation pole at fC = 4kHz. A 10nF REF/BYP capacitor to GND creates a lowpass pole at fLP = 840Hz. The 10nF capacitor decreases reference voltage noise to about 10μVRMS and soft-starts the reference. The LT3070 only soft-starts the reference voltage during an initial turn-on sequence. If the EN pin is toggled low after initial turn-on, the reference remains powered-up. Therefore, toggling the EN pin from low to high does not soft-start the reference. Only by turning the BIAS supply voltage on and off will the reference be soft-started. Output voltage noise is the RMS sum of the reference voltage noise in addition to the amplifier noise. The REF/BYP pin must not be DC loaded by anything except for applications that parallel other LT3070 regulators for higher output currents. Consult the Applications Section on Paralleling for further details. Output Voltage Margining Two tri-level input pins, MARGSEL (polarity) and MARGTOL (scale), select the polarity and amount of output voltage margining. Margining is programmable in increments of ±1%, ±3% and ±5%. Margining is internally implemented as a scaling of the reference voltage. Table 2 illustrates the 2-bit digital word to output voltage margining resulting from setting these pins high, low or allowing them to float. These pins may be set high or set low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has “Hi-Z” output capability. This allows output voltage to be dynamically margined if necessary. The MARGSEL pin determines both the polarity and the active state of the margining function. The logic “low” threshold is less than 220mV referenced to GND and enables negative voltage margining. The logic “high” threshold is greater than VBIAS – 500mV and enables X = Don’t Care, 0 = GND, Z = Float, 1 = VBIAS The input logic “0” threshold is less than 220mV referenced to GND and the logic “1” threshold is greater than VBIAS – 500mV. The range between these two thresholds defines the logic Hi-Z state. 3070p 12 LT3070 APPLICATIONS INFORMATION positive voltage margining. The voltage range between these two logic thresholds defines the logic Hi-Z state and disables the margining function. The MARGTOL pin selects the absolute value of margining (1%, 3% or 5%) if enabled by the MARGSEL input. The logic “low” threshold is less than 220mV referenced to GND and enables either ±1% change in VOUT depending on the state of the MARGSEL pin. The logic “high” threshold is greater than VBIAS – 500mV and enables either ±5% change in VOUT depending on the state of the MARGSEL pin. The voltage range between these two logic thresholds defines the logic Hi-Z state and enables either ±3% change in VOUT depending on the state of the MARGSEL pin. Table 2: Programming Margining MARGSEL 0 0 0 Z Z Z 1 1 1 MARGTOL 0 Z 1 0 Z 1 0 Z 1 % of VOUT(NOM) –1 –3 –5 0 0 0 1 3 5 gated off and output current falls to zero. The typical BIAS pin UVLO threshold is 1.55V on the rising edge of VBIAS. The UVLO circuit incorporates about 250mV of hysteresis on the falling edge of VBIAS. High Efficiency Linear Regulator—Input-to-Output Voltage Control The VIOC (voltage input to output control) pin is a function to control a switching regulator and facilitate a design solution that maximizes system efficiency at high load currents and still provides low dropout voltage performance. The VIOC pin is the output of an integrated transconductance amplifier that sources and sinks 250μA of current. It typically regulates the output of most LTC® switching regulators or LTM® power modules, by sinking current from the ITH compensation node. The VIOC function controls a buck regulator powering the LT3070’s input by maintaining the LT3070’s input voltage to VOUT + 300mV. This 300mV VIN-VOUT differential voltage is chosen to provide fast transient response and good high frequency PSRR while minimizing power dissipation and maximizing efficiency. For example, 1.5V to 1.2V conversion and 1.3V to 1V conversion yield 1.5W maximum power dissipation at 5A full output current. Figure 2 depicts that the switcher’s feedback resistor network sets the maximum switching regulator output voltage if the linear regulator is disabled. However, once the LT3070 is enabled, the VIOC feedback loop decreases the switching regulator output voltage back to VOUT + 300mV. Using the VIOC function creates a feedback loop between the LT3070 and the switching regulator. As such, the feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many LTC ITH pins represents a high impedance characteristic which is the optimum circuit node to frequency compensate the feedback loop. Figure 2 illustrates the typical frequency compensation network used at the VIOC node to GND. The VIOC amplifier characteristics are: gm = 3.2mS, IOUT = ±250μA, BW = 10MHz. If the VIOC is not used, terminate the VIOC pin to GND with a small capacitor (1000pF) to prevent oscillations. 3070p Enable Function—Turning On and Off The first rising edge of the EN enable pin starts the LT3070 reference and all support functions while enabling the output. After start-up, pulling the EN pin low places the regulator into nap mode. In nap mode, the reference circuit remains active, but the output is disabled and quiescent current decreases. Drive the EN pin with either a digital logic port or an opencollector NPN or open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be no larger than 35k to meet the VIH condition of the EN pin. If unused, connect the EN pin to VBIAS. Input Undervoltage Lockout on BIAS Pin An internal undervoltage lockout (UVLO) comparator monitors the BIAS rail. If VBIAS drops below the UVLO threshold, all functions shut down, the pass transistor is 13 LT3070 APPLICATIONS INFORMATION IN SWITCHING REGULATOR REF LT3070 OUT LOAD + – PWM FB VOUT + VREF 300mV REFERENCE ITH 3070 F02 VIOC Figure 2. VIOC Control Block Diagram PWRGD—Power Good PWRGD is an open-drain digital output pin that pulls “low” if it detects any one of several fault modes including: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT • VOUT decreases below 85% of VOUT(NOMINAL) for more than 25μs • VIN decreases below VOUT • Junction temperature exceeds 145°C typically* *The junction temperature detector is an early warning indicator that trips approximately 20°C before thermal shutdown engages. Stability and Output Capacitance The LT3070’s feedback loop requires an output capacitor for stability. Choose COUT carefully and mount it in close proximity to the LT3070’s OUT and GND pins. Include wide routing planes for OUT and GND to minimize inductance. If possible, mount the regulator immediately adjacent to the application load to minimize distributed inductance for optimal load transient performance. Point-of-Load applications present the best case layout scenario for extracting full LT3070 performance. Low ESR, X5R or X7R ceramic chip capacitors are the LTC recommended choice for stabilizing the LT3070. Additional bulk capacitors distributed beyond the immediate decoupling capacitors are acceptable as their parasitic ESL and ESR, combined with the distributed PCB inductance isolates them from the primary compensation pole provided by the local surface mount ceramic capacitors. The LT3070 requires a minimum output capacitance of 15μF for stability. LTC strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. Why Do Multiple, Small-Value Output Capacitors Connected in Parallel Work Better? The LT3070’s unity-gain bandwidth with COUT of 15μF is about 1MHz at its full-load current of 5A. Surface mounted MLCC capacitors have a self-resonance frequency of fR = 1/(2π√LC), which must be pushed to a frequency higher than the regulator bandwidth. Standard MLCC capacitors are acceptable. To keep the resonant frequency greater than 1MHz, the product 1/(2π√LC) must be greater than 1MHz. At this bandwidth, PCB vias can add significant inductance, thus the fundamental decoupling capacitors must be mounted on the same plane as the LT3070. Typical 0603 or 0805 case-size capacitors have an ESL of ~800pH and PCB mounting can contribute up to ~200pH. Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, fR, will form a tank circuit that can induce ringing of their own accord. Small amounts of ESR (5mΩ to 20mΩ) have some benefit in dampening the resonant loop, but higher ESRs degrade 3070p 14 LT3070 APPLICATIONS INFORMATION the capacitor response to transient load steps with rise/ fall times less than 1μs. The most area efficient parallel capacitor combination is a graduated 4/2/1 scale of fR of the same case size. Under these conditions, the individual ESLs are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. The recommended parallel combination that approximates 15μF is 10μF + 4.7μF + 2.2μF Capacitors with case sizes . larger than 0805 have higher ESL and lower ESR (