LT3071EUFD-TRPBF

LT3071 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining FeAtures Output Current: 5A n Dropout Voltage: 85mV Typical n Digitally Programmable V OUT : 0.8V to 1.8V n Analog Output Margining: ±10% Range n Low Output Noise: 25µV RMS (10Hz to 100kHz) n Parallel Multiple Devices for 10A or More n Precision Current Limit: ±20% n Output Current Monitor: I MON = IOUT/2500 n ±1% Accuracy Over Line, Load and Temperature n Stable with Low ESR Ceramic Output Capacitors (15µF Minimum) n High Frequency PSRR: 30dB at 1MHz n Enable Function Turns Output On/Off n VIOC Pin Controls Buck Converter to Maintain Low Power Dissipation and Optimize Efficiency n PWRGD/UVLO/Thermal Shutdown Flag n Current Limit with Foldback Protection n Thermal Shutdown n 28-Lead (4mm × 5mm × 0.75mm) QFN Package n Description The LT®3071 is a low voltage, UltraFast™ transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µVRMS. The LT3071’s high bandwidth permits the use of low ESR ceramic capacitors, saving bulk capacitance and cost. The LT3071’s features make it ideal for high performance FPGAs, microprocessors or sensitive communication supply applications. Output voltage is digitally selectable in 50mV increments over a 0.8V to 1.8V range. An analog margining function allows the user to adjust system output voltage over a continuous ±10% range. The IC incorporates a unique tracking function to control a buck regulator powering the LT3071’s input. This tracking function drives the buck regulator to maintain the LT3071’s input voltage to VOUT + 300mV, minimizing power dissipation. Internal protection includes UVLO, reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3071 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. UltraFast and VLDO are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents pending. ApplicAtions n n n n FPGA and DSP Supplies ASIC and Microprocessor Supplies Servers and Storage Devices Post Buck Regulation and Supply Isolation typicAl ApplicAtion 0.9V, 5A Regulator DROPOUT VOLTAGE (mV) 150 Dropout Voltage VIN = VOUT(NOMINAL) VBIAS 2.2V TO 3.6V VIN 1.2V 50k 2.2µF IN 330µF EN VO0 VO1 VO2 NC 1nF MARGA VIOC IMON REF/BYP GND LT3071 BIAS PWRGD SENSE OUT PWRGD 120 90 2.2µF* 4.7µF* VOUT 0.9V 10µF* 5A VOUT = 1.8V VBIAS = 3.3V VOUT = 0.8V VBIAS = 2.5V 60 30 *X5R OR X7R CAPACITORS VMON 2V AT 5A FULL SCALE 0.01µF 1k 3071 TA01a 0 0 1 3 4 2 OUTPUT CURRENT (A) 5 3071 TA01b 3071f  LT3071 Absolute mAximum rAtings (Note 1) pin conFigurAtion TOP VIEW BIAS GND VO2 VO1 GND VO0 22 MARGA 21 IMON 20 GND 29 GND 19 SENSE 18 OUT 17 OUT 16 OUT 15 OUT 9 10 11 12 13 14 GND GND GND GND GND EN VIOC 1 PWRGD 2 REF/BYP 3 GND 4 IN 5 IN 6 IN 7 IN 8 28 27 26 25 24 23 IN, OUT ..................................................... –0.3V to 3.3V BIAS ............................................................. –0.3V to 4V VO2, VO1, VO0 Inputs .................................... –0.3V to 4V MARGA Input ............................................... –0.3V to 4V EN Input ....................................................... –0.3V to 4V SENSE Input................................................. –0.3V to 4V VIOC, PWRGD, IMON Outputs ....................... –0.3V to 4V REF/BYP Output ........................................... –0.3V to 4V Output Short-Circuit Duration .......................... Indefinite Operating Junction Temperature (Note 2) LT3071E/LT3071I .............................. – 40°C to 125°C LT3071MP ......................................... –55°C to 125°C Storage Temperature Range .................. –65°C to 150°C TJMAX = 125°C, θJA = 30°C/W TO 35°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN orDer inFormAtion LEAD FREE FINISH LT3071EUFD#PBF LT3071IUFD#PBF LT3071MPUFD#PBF LEAD BASED FINISH LT3071EUFD LT3071IUFD LT3071MPUFD TAPE AND REEL LT3071EUFD#TRPBF LT3071IUFD#TRPBF LT3071MPUFD#TRPBF TAPE AND REEL LT3071EUFD#TR LT3071IUFD#TR LT3071MPUFD#TR PART MARKING* 3071 3071 3071 PART MARKING* 3071 3071 3071 PACKAGE DESCRIPTION 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN PACKAGE DESCRIPTION 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –55°C to 125°C TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3071f  LT3071 electricAl chArActeristics PARAMETER IN Pin Voltage Range BIAS Pin Voltage Range (Note 3) Regulated Output Voltage VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1.05V ≤ VIN ≤ 1.25V VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.15V ≤ VIN ≤ 1.35V VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.25V ≤ VIN ≤ 1.45V VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.35V ≤ VIN ≤ 1.55V VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.45V ≤ VIN ≤ 1.65V, VBIAS = 3.3V VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.75V ≤ VIN ≤ 1.95V, VBIAS = 3.3V VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.05V ≤ VIN ≤ 2.25V, VBIAS = 3.3V MARGA = 1.2V MARGA = 0V VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA VOUT = 1.8V, ∆VIN = 2.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA VOUT = 0.8V, ∆VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA VOUT = 1.8V, ∆VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. CONDITIONS VIN ≥ VOUT + 150mV, IOUT= 5A l l l l l l l l l l l l l l l MIN 0.95 2.2 0.792 0.891 0.990 1.089 1.188 1.485 1.782 9.5 –10.5 TYP MAX 3.0 3.6 UNITS V V V V V V V V V % % mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV µA µA mA mA µA mA mA mA mA mA mA A A A mA µA/A µA % % mV 3071f 0.800 0.900 1.000 1.100 1.200 1.500 1.800 10 –10 0.808 0.909 1.010 1.111 1.212 1.515 1.818 10.5 –9.5 1.0 1.0 2.0 1.0 Regulated Output Voltage Margining (Note 3) Line Regulation to VIN Line Regulation to VBIAS Load Regulation, ∆IOUT = 10mA to 5A –1.5 –2 l –3.0 –5.5 –4.0 –7.5 –4.0 –7.5 –5.0 –9.0 –7.0 –13 35 65 85 120 150 65 400 1.8 2.3 320 1.5 2.4 4.0 5.0 7.0 10.0 7.7 5.8 4.3 2.4 460 450 93 88 150 VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V VBIAS = 3.3V, VIN = 1.45V, VOUT = 1.2V l –2 –2.5 l VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V l –3 l l Dropout Voltage, VIN = VOUT(NOMINAL) (Note 6) IOUT = 1A, VOUT = 1V IOUT = 2.5A, VOUT = 1V IOUT = 5A, VOUT = 1V 20 50 85 l SENSE Pin Current Ground Pin Current, VIN = 1.3V, VOUT = 1V BIAS Pin Current in Nap Mode BIAS Pin Current, VIN = 1.3V, VOUT = 1V VIN = 1.1V, VSENSE = 0.8V VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V IOUT = 10mA IOUT = 5A EN = Low (After POR Completed) IOUT = 10mA IOUT = 100mA IOUT = 500mA IOUT = 1A IOUT = 2.5A IOUT = 5A VIN – VOUT < 0.3V, VBIAS = 3.3V VIN – VOUT = 1.0V, VBIAS = 3.3V VIN – VOUT = 1.7V, VBIAS = 3.3V IOUT = 5A, VIN – VOUT = 0.3V, VOUT = 0.8V, 1.8V 1A ≤ IOUT ≤ 5A, VIN – VOUT = 0.3V, VOUT = 0.8V, 1.8V VIN = 0V, VOUT = 1.8V Percentage of VOUT(NOMINAL), VOUT Rising Percentage of VOUT(NOMINAL), VOUT Falling IPWRGD = 200µA (Fault Condition) l l l l l l l l l l l l l l l l l l l l 35 200 0.65 0.9 120 0.75 1.25 2.0 2.6 3.5 4.5 5.1 3.2 1.2 1.6 340 87 82 50 300 1.1 1.35 200 1.08 1.8 3.0 3.8 5.2 6.9 6.4 4.5 2.5 2.0 400 300 90 85 50 Current Limit (Note 5) IMON Full-Scale Output Current IMON/IOUT Scale Reverse Output Current (Note 8) PWRGD VOUT Threshold PWRGD VOL  LT3071 electricAl chArActeristics PARAMETER VBIAS Undervoltage Lockout VIN-VOUT Servo Voltage by VIOC VIOC Output Current VIL Input Threshold (Logic-0 State), VO2, VO1, VO0, MARGSEL, MARGTOL VIZ Input Range (Logic-Z State), VO2, VO1, VO0, MARGSEL, MARGTOL VIH Input Threshold (Logic-1 State), VO2, VO1, VO0, MARGSEL, MARGTOL Input Hysteresis (Both Thresholds), VO2, VO1, VO0, MARGSEL, MARGTOL Input Current High, VIH = VBIAS = 2.5V, Current Flows Into Pin VO2, VO1, VO0, MARGSEL, MARGTOL Input Current Low, VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin VO2, VO1, VO0, MARGSEL, MARGTOL EN Pin Threshold EN Pin Logic High Current EN Pin Logic Low Current VBIAS Ripple Rejection VIN Ripple Rejection (Notes 3, 4, 5) Reference Voltage Noise (REF/BYP Pin) Output Voltage Noise VOUT = Off to On VOUT = On to Off VEN = VBIAS = 2.5V VEN = 0V VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz, VIN – VOUT = 300mV, IOUT = 2.5A VBIAS = 2.5V, VRIPPLE = 50mVP-P , fRIPPLE = 120Hz, VIN – VOUT = 300mV, IOUT = 2.5A CREF/BYP = 10nF , BW = 10Hz to 100kHz VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF OUT = 15µF , C , BW = 10Hz to 100kHz l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. CONDITIONS VBIAS Rising VBIAS Falling VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin Input Falling l l l l l l l MIN 1.1 0.9 250 160 170 TYP 1.55 1.4 300 235 255 MAX 2.1 1.7 350 310 340 0.25 UNITS V V mV µA µA V V V 0.75 VBIAS – 0.25 60 25 25 0.9 2.5 4.0 75 66 10 25 VBIAS – 0.9 Input Rising l mV 40 40 1.4 6.5 0.1 µA µA V V µA µA dB dB µVRMS µVRMS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3071 regulators are tested and specified under pulse load conditions such that TJ ≅ TA. The LT3071E is 100% tested at TA = 25°C. Performance at –40°C and 125°C is assured by design, characterization and correlation with statistical process controls. The LT3071I is guaranteed over the –40°C to 125°C operating junction temperature range. The LT3071MP is 100% tested and guaranteed over the –55°C to 125°C operating junction temperature range. Note 3: To maintain proper performance and regulation, the BIAS supply voltage must be higher than the IN supply voltage. For a given VOUT , the BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS voltage is limited to 2.2V. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. When operating at maximum output current, limit the input voltage range to VIN < VOUT + 500mV. Note 5: The LT3071 incorporates safe operating area protection circuitry. Current limit decreases as the VIN-VOUT voltage increases. Current limit foldback starts at VIN – VOUT > 500mV. See the Typical Performance Characteristics for a graph of Current Limit vs VIN – VOUT voltage. The current limit foldback feature is independent of the thermal shutdown circuity. Note 6: Dropout voltage, VDO, is the minimum input to output voltage differential at a specified output current. In dropout, the output voltage equals VIN – VDO. Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a current source load. VIOC is a buffered output determined by the value of VOUT as programmed by the VO2-VO0 pins. VIOC’s output is independent of the margining function. Note 8: Reverse output current is tested with the IN pins grounded and the OUT + SENSE pins forced to the rated output voltage. This is measured as current into the OUT + SENSE pins. Note 9: Frequency Compensation: The LT3071 must be frequency compensated at its OUT pins with a minimum COUT of 15µF configured as a cluster of (15×) 1µF ceramic capacitors or as a graduated cluster of 10µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear Technology only recommends X5R or X7R dielectric capacitors. 3071f  LT3071 typicAl perFormAnce chArActeristics Dropout Voltage vs IOUT 150 VIN = VOUT(NOMINAL) TJ = 25°C DROPOUT VOLTAGE (mV) Dropout Voltage vs Temperature 30 25 20 15 10 5 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V VIN = VOUT(NOMINAL) IOUT = 1A DROPOUT VOLTAGE (mV) 100 90 80 70 60 50 40 30 20 10 Dropout Voltage vs Temperature VIN = VOUT(NOMINAL) IOUT = 2.5A DROPOUT VOLTAGE (mV) 120 90 VOUT = 1.8V VBIAS = 3.3V VOUT = 0.8V VBIAS = 2.5V 60 30 0 0 1 3 4 2 OUTPUT CURRENT (A) 5 3071 G01 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G02 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G03 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V Dropout Voltage vs Temperature 150 VIN = VOUT(NOMINAL) IOUT = 5A DROPOUT VOLTAGE (mV) 200 Dropout Voltage vs VBIAS Output Voltage (0.8V) vs Temperature 0.808 0.806 OUTPUT VOLTAGE (V) 0.804 0.802 0.800 0.798 0.796 0.794 0.792 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G06 IOUT = 5A 180 TJ = 25°C 160 140 120 100 80 60 40 20 0 2.2 2.4 OUT = 1.8V OUT = 1.5V OUT = 0.8V 2.6 2.8 3.0 3.2 BIAS VOLTAGE (V) 3.4 3.6 ILOAD = 10mA DROPOUT VOLTAGE (mV) 120 90 60 30 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G04 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 3071 G05 Output Voltage (1V) vs Temperature 1.010 1.008 1.006 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.004 1.002 1.000 0.998 0.996 0.994 0.992 0.990 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G07 Output Voltage (1.2V) vs Temperature 1.212 1.208 1.204 1.200 1.196 1.192 1.188 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G08 Output Voltage (1.5V) vs Temperature 1.515 1.510 OUTPUT VOLTAGE (V) 1.505 1.500 1.495 1.490 1.485 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G09 ILOAD = 10mA ILOAD = 10mA ILOAD = 10mA 3071f  LT3071 typicAl perFormAnce chArActeristics Output Voltage (1.8V) vs Temperature 1.818 1.814 1.810 OUTPUT VOLTAGE (V) 1.806 1.802 1.798 1.794 1.790 1.786 1.782 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G10 GND Pin Current vs IOUT 3.0 2.5 GND PIN CURRENT (mA) 2.0 1.5 1.0 0.5 0 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V 0 1 2 3 4 OUTPUT CURRENT (A) 5 3071 G11 REF/BYP Pin Voltage vs Temperature 606 604 REF/BYP VOLTAGE (mV) 602 600 598 596 594 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G12 ILOAD = 10mA VIN = VOUT + 300mV TJ = 25°C CREF/BYP = 0.01µF BIAS Pin Current in Nap Mode 400 VBIAS = 2.5V 350 VEN = 0V BIAS PIN CURRENT (mA) BIAS PIN CURRENT (µA) 300 250 200 150 100 50 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G13 BIAS Pin Current vs IOUT 10 9 8 7 6 5 4 3 2 1 0 0 1 3 4 2 OUTPUT CURRENT (A) 5 3071 G14 BIAS Pin Undervoltage Lockout Threshold 2.5 UVLO THRESHOLD VOLTAGE (V) VIN = VOUT + 300mV TJ = 25°C 2.0 1.5 VBIAS RISING VBIAS FALLING VOUT = 1.8V VBIAS = 3.3V VOUT = 0.8V VBIAS = 2.5V 1.0 0.5 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G15 2.5 IMON vs IOUT PWRGD TRESHOLD VOLTAGE (V) PWRGD Threshold Voltage 1.00 VBIAS = 2.5V VOUT = 1V PWRGD VOL VOLTAGE (mV) 100 PWRGD VOL vs Temperature VBIAS = 2.5V IPWRGD = 200µA VBIAS = 3.3V VOUT = 0.8V TO 1.8V V – VOUT = 300mV 2.0 T IN= –55°C TO 125°C J 1.5 0.95 VOUT RISING 0.90 VOUT FALLING 80 60 IMON (mA) 1.0 40 20 0.5 0 0.85 0 1 2 3 4 OUTPUT CURRENT (A) 5 6 3071 G52 0.80 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G17 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G50 3071f  LT3071 typicAl perFormAnce chArActeristics EN Pin Thresholds 2.0 1.8 ENABLE PIN THRESHOLD (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G16 Logic Input Threshold Voltages Logic Low to Hi-Z State Transitions 0.8 LOGIC INPUT THRESHOLD VOLTAGE (V) LOGIC INPUT THRESHOLD VOLTAGE (V) SEE APPLICATIONS INFORMATION FOR MORE DETAILS INPUT RISING LOGIC LOW TO Hi-Z 3.0 Logic Input Threshold Voltages Logic Hi-Z to High State Transitions VBIAS = 3.3V LOGIC Hi-Z TO HIGH THRESHOLD IS RELATIVE TO VBIAS VOLTAGE SEE APPLICATIONS INFORMATION FOR MORE DETAILS INPUT RISING LOGIC Hi-Z TO HIGH 2.7 2.6 INPUT FALLING LOGIC HIGH TO Hi-Z VBIAS = 2.5V 0.7 0.6 2.9 2.8 EN PIN RISING EN PIN FALLING 0.5 0.4 INPUT FALLING LOGIC Hi-Z TO LOW 0.3 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G18 2.5 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G19 EN Pin Logic High Current 6.0 EN PIN LOGIC HIGH CURRENT (µA) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G20 Logic Pin Input Current, High State 40 LOGIC PIN INPUT CURRENT (µA) 35 30 25 20 15 10 5 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G21 Logic Pin Input Current, Low State 40 LOGIC PIN INPUT CURRENT (µA) VBIAS = 2.5V 35 VLOGIC = 0V CURRENT FLOWS OUT OF THE PIN 30 25 20 15 10 5 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G22 VEN = VBIAS = 2.5V VLOGIC = VBIAS = 2.5V CURRENT FLOWS INTO THE PIN SENSE Pin Current 65 VBIAS = 2.5V 60 VOUT = 0.8V CURRENT FLOWS INTO SENSE 55 50 45 40 35 30 25 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G23 SENSE Pin Current 400 VBIAS = 3.3V 375 VOUT = 1.8V CURRENT FLOWS INTO SENSE 350 325 300 275 250 225 200 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G24 Current Limit vs Temperature 7.50 7.25 7.00 CURRENT LIMIT (A) 6.75 6.50 6.25 6.00 5.75 5.50 5.25 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VIN = VOUT(NOMINAL) + 300mV SENSE PIN CURRENT (µA) SENSE PIN CURRENT (µA) 5.00 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G25 3071f  LT3071 typicAl perFormAnce chArActeristics Current Limit vs VIN – VOUT 8 7 CURRENT LIMIT (A) 6 5 4 3 2 1 0 0 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 IN-TO-OUT VOLTAGE DIFFERENTIAL (V) 3071 G26 BIAS Pin Ripple Rejection 100 90 BIAS PIN RIPPLE REJECTION (dB) 80 70 60 50 40 30 20 10 0 10 VBIAS = 2.5V + 500mVP-P VBIAS = 2.7V + 500mVP-P VBIAS = 3.3V + 500mVP-P 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3071 G27 IN Pin Ripple Rejection 80 70 IN PIN RIPPLE REJECTION (dB) 60 50 40 30 20 10 0 10 COUT = 117µF COUT = 16.9µF VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 1A 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3071 G28 VBIAS = 3.3V TJ = 25°C VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 10µF + 4.7µF + 2.2µF IN Pin Ripple Rejection 80 70 IN PIN RIPPLE REJECTION (dB) MINIMUM BIAS VOLTAGE (V) 60 50 40 30 20 10 0 10 COUT = 117µF COUT = 16.9µF VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 5A 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3071 G29 Minimum BIAS Voltage vs Temperature 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G30 Minimum BIAS Voltage vs IOUT VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 3.6 3.4 MINIMUM BIAS VOLTAGE (V) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 0 1 2 4 3 OUTPUT CURRENT (A) 5 3071 G31 IOUT = 5A VIN = VOUT(NOMINAL) + 300mV VOUT = –1%, TJ = 25°C VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 0.8V TO 1V Minimum BIAS Voltage vs VOUT 3.4 3.2 MINIMUM BIAS VOLTAGE (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 0.7 0.9 1.5 1.1 1.3 OUTPUT VOLTAGE (V) 1.7 1.9 3071 G51 Load Regulation 0 BIAS VOLTAGE LINE REGULATION (µV) 800 Bias Voltage Line Regulation VBIAS = 2.2V TO 3.6V 700 VIN = 1.1V VOUT = 0.8V 600 IOUT = 10mA 500 400 300 200 100 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G33 IOUT = 5A TJ = 25°C LOAD REGULATION (mV) –2 –4 –6 –8 VIN = VOUT(NOMINAL) + 300mV VBIAS = 3.3V IOUT = 100mA TO 5A VOUT = 0.8V VOUT = 1.2V VOUT = 1.8V –10 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G32 3071f  LT3071 typicAl perFormAnce chArActeristics Bias Voltage Line Regulation 400 BIAS VOLTAGE LINE REGULATION (µV) INPUT VOLTAGE LINE REGULATION (µV) VBIAS = 3.25V TO 3.6V 300 VIN = 2.1V VOUT = 1.8V 200 IOUT = 10mA 100 0 –100 –200 –300 –400 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G34 Input Voltage Line Regulation 300 250 200 150 100 50 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G35 Input Voltage Line Regulation 300 INPUT VOLTAGE LINE REGULATION (µV) 250 200 150 100 50 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G36 VBIAS = 3.3V VIN = 1.05V TO 2.7V VOUT = 0.8V IOUT = 10mA VBIAS = 3.3V VIN = 2.05V TO 2.7V VOUT = 1.8V IOUT = 10mA Output Voltage Start-Up Time vs CREF/BYP 20 OUTPUT VOLTAGE START-UP TIME (ms) 18 16 14 12 10 8 6 4 2 0 0 0.1 0.3 0.4 0.2 REF/BYP CAPACITANCE (µF) 0.5 3071 G37 Nap Mode Recovery Time vs IOUT 400 NAP MODE RECOVERY TIME (µs) 350 300 250 200 150 100 50 0 0 1 4 3 OUTPUT CURRENT (A) 2 5 3071 G38 Output Noise Spectral Density 1.0 NOISE SPECTRAL DENSITY (µV/√Hz) VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9µF CREF/BYP = 0.01µF VBIAS = 2.5V TO 3.3V IOUT = 10mA COUT = 10µF + 4.7µF + 2.2µF TJ = 25°C SEE APPLICATIONS INFORMATION FOR START-UP DETAILS VBIAS = 3.3V VIN = VOUT(NOM) + 300mV EN = LOW TO HIGH IOUT = 5A (SET BY A RESISTOR LOAD) TJ = 25°C VOUT = 1.8V, COUT = 117µF VOUT = 1.2V, COUT = 117µF VOUT = 0.8V, COUT = 117µF 0.1 0.01 0.001 10 100 1k 10k FREQUENCY (Hz) 100k 3071 G39 RMS Output Noise vs Output Current 80 70 OUTPUT NOISE (µVRMS) 60 50 40 30 20 10 0 0.01 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 0.1 1 OUTPUT CURRENT (A) 10 3071 G40 Output Noise (10Hz to 100kHz) Input Voltage Line Transient Response VIN = VOUT(NOMINAL) + 300mV VBIAS = 3.3V COUT = 16.9µF VOUT 1mV/DIV VOUT 100µV/DIV VIN 50mV/DIV VOUT = 1V IOUT = 5A COUT = 16.9µF 1ms/DIV 3071 G41 VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 16.9µF 20µs/DIV 3071 G42 3071f  LT3071 typicAl perFormAnce chArActeristics Bias Voltage Line Transient Response 350 VIOC IN-TO-OUT SERVO VOLTAGE (mV) VOUT 10mV/DIV 340 330 320 310 300 290 280 270 260 250 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G44 VIOC Amplifier IN-to-OUT Servo Voltage VIOC AMPLIFIER OUTPUT CURRENT (µA) VBIAS = 2.5V 300 275 VIOC Amplifier Output Current vs Temperature IVIOC SOURCING 250 IVIOC SINKING 225 200 175 150 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3071 G45 VBIAS 200mV/DIV 3071 G43 VIN = 1.3V VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9µF 20µs/DIV Transient Load Response Transient Load Response VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV ∆I = 500mA TO 5A VOUT = 1V 20µs/DIV COUT = 10µF + 4.7µF + 2.2µF IOUT tRISE/tFALL = 100ns 3071 G46 IOUT 2A/DIV ∆I = 500mA TO 5A VOUT = 1V 20µs/DIV COUT = 117µF IOUT tRISE/tFALL = 100ns 3071 G47 Transient Load Response Transient Load Response VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV ∆I = 500mA TO 5A VOUT = 1V 20µs/DIV COUT = 10µF + 4.7µF + 2.2µF IOUT tRISE/tFALL = 1µs 3071 G48 IOUT 2A/DIV ∆I = 500mA TO 5A VOUT = 1V 20µs/DIV COUT = 117µF IOUT tRISE/tFALL = 1µs 3071 G49 3071f 0 LT3071 pin Functions VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck regulator powering the LT3071’s input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3071’s input voltage at VOUT + 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information section for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that actively pulls low if any one of these fault modes is detected: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . • VOUT drops below 85% of VOUT(NOMINAL) for more than 25µs. • Junction temperature typically exceeds 145°C. • VBIAS is less than its undervoltage lockout threshold. • The OUT-to-IN reverse-current detector activates. See the Applications Information section for more information on PWRGD fault modes. REF/BYP (Pin 3): Reference Filter. The pin is the output of the bandgap reference and has an impedance of approximately 19kΩ. This pin must not be externally loaded. Bypassing the REF/BYP pin to GND with a 10nF capacitor decreases output voltage noise and provides a soft-start function to the reference. LTC recommends the use of a high quality, low leakage capacitor. See the Applications Information section for more information on noise and output voltage margining considerations. GND (Pins 4, 9-14, 20, 26, Exposed Pad Pin 29): Ground. The exposed pad of the QFN package is an electrical connection to GND. To ensure proper electrical and thermal performance, solder Pin 29 to the PCB ground and tie to all GND pins of the package. These GND pins are fused to the internal die attach paddle and the exposed pad to optimize heat sinking and thermal resistance characteristics. See the Applications Information section for thermal considerations and calculating junction temperature. IN (Pins 5, 6, 7, 8): Input Supply. These pins supply power to the high current pass transistor. Tie all IN pins together for proper performance. The LT3071 requires a bypass capacitor at IN to maintain stability and low input impedance over frequency. A 47µF input bypass capacitor suffices for most battery and power plane impedances. Minimizing input trace inductance optimizes performance. Applications that operate with low VIN-VOUT differential voltages and that have large, fast load transients may require much higher input capacitor requirements to prevent the input supply from drooping and allowing the regulator to enter dropout. See the Applications Information section for more information on input capacitor requirements. OUT (Pins 15, 16, 17, 18): Output. These pins supply power to the load. Tie all OUT pins together for proper performance. A minimum output capacitance of 15µF is required for stability. LTC recommends low ESR, X5R or X7R dielectric ceramic capacitors for best performance. A parallel ceramic capacitor combination of 10µF + 4.7µF + 2.2µF or 15 1µF ceramic capacitors in parallel provide excellent stability and load transient response. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitor requirements. 3071f  LT3071 pin Functions SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is the inverting input to the error amplifier. Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of the regulator. In critical applications, the resistance (RP) of PCB traces between the regulator and the load cause small voltage drops, creating a load regulation error at the point of load. Connecting the SENSE pin at the load instead of directly to OUT eliminates this voltage error. Figure 1 illustrates this Kelvin-Sense connection method. Note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50µA typically at VOUT = 0.8V to 300µA typically at VOUT = 1.8V. IMON (Pin 21): Output Current Monitor. The IMON pin sources a current typically equal to IOUT/2500 or 400µA per amp of output current. Terminating this pin with a resistor to GND produces a voltage proportional to IOUT . For example, at IOUT = 5A, IMON typically sources 2mA. With a 1k resistor to GND, this produces 2V. If IMON is unused, tie this pin to VBIAS. MARGA (Pin 22): Analog Margining: This pin margins the output voltage over a continuous analog range of ±10%. Tying this pin to GND adjusts output voltage by –10%. Driving this pin to 1.2V adjusts output voltage by +10%. A voltage source or a voltage output DAC is ideal for driving this pin. If the MARGA function is not used, either float this pin or terminate with a 1nF capacitor to GND. VO0, VO1 and VO2 (Pins 23, 24, 25): Output Voltage Select. These three-state pins combine to select a nominal output voltage from 0.8V to 1.8V in increments of 50mV. Output voltage is limited to 1.8V maximum by an internal override of VO1 when VO2 = high. The input logic low threshold is less than 250mV referenced to GND and the logic high threshold is greater than VBIAS – 250mV. The range between these two thresholds as set by a window comparator defines the logic Hi-Z state. See Table 1 in the Applications Information section that defines the VO2, VO1 and VO0 settings versus VOUT . BIAS (Pin 27): Bias Supply. This pin supplies current to the internal control circuitry and the output stage driving the pass transistor. The LT3071 requires a minimum 2.2µF bypass capacitor for stability and proper operation. To ensure proper operation, the BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS voltage is limited to 2.2V. EN (Pin 28): Enable. This pin enables/disables the output device only. The internal reference and all support functions are active if VBIAS is above its UVLO threshold. Pulling EN low keeps the reference circuit active, but disables the output pass transistor and puts the LT3071 into a low power nap mode. Drive the EN pin with either a digital logic port or an open-collector NPN or an open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 35k to meet the VIH condition of the EN pin. If unused, connect EN to BIAS. + VBIAS EN IN VO0 VO1 VIN VO2 MARGA VIOC BIAS PWRGD SENSE OUT RP LOAD LT3071 + IMON REF/BYP GND RP 3071 F01 Figure 1. Kelvin Sense Connection 3071f  LT3071 block DiAgrAm 27 BIAS IN 5-8 UVLO AND THERMAL SHUTDOWN + ISENSE REF/BYP + – IMON 21 + EAMP – BUF LDO CORE DETECT – OUT 15-18 SENSE PWRGD 19 2 1 VIOC GND 4,9-14,20,26,29 PROGRAM CONTROL EN 28 VO2 25 VO1 24 VO0 23 MARGA 22 VBIAS – 0.25V VBIAS VO2, VO1, VO0 MARGSEL OR MARGTOL 100k 100k VBIAS – 0.9V 0.75V LOGIC Hi-Z STATE + – + – LOGIC LOW STATE 0.25V + + – – + – VOUT(NOM) + 300mV VREF REF/BYP 600mV 3 3070 BD LOGIC HIGH STATE HIGH IF IN > VBIAS – 0.25V HIGH IF IN < VBIAS – 0.9V AND IN > 0.75V HIGH IF IN < 0.25V TO LOGIC 3071f  LT3071 ApplicAtions inFormAtion Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement. Some ASIC processors require only a single output voltage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power supply voltages for the processor core, the I/O, and the transceivers. Often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. These requirements mandate the need for very accurate, low noise, high current, very high speed regulator circuits that operate at low input and output voltages. The LT3071 is a low voltage, UltraFast transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µVRMS (BW = 10Hz to 100kHz). The LT3071’s high bandwidth provides UltraFast transient response using low ESR ceramic output capacitors (15µF minimum), saving bulk capacitance, PCB area and cost. The LT3071’s features permit state-of-the-art linear regulator performance. The LT3071 is ideal for high performance FPGAs, microprocessors, sensitive communication supplies, and high current logic applications that also operate over low input and output voltages. Output voltage for the LT3071 is digitally selectable in 50mV increments over a 0.8V to 1.8V range. An analog margining function allows the user to adjust system output voltage over a continuous ±10% range. The LT3071 provides an output current monitor that typically sources a current of IOUT/2500 or 400µA per amp of IOUT at its IMON pin. Terminating the IMON pin to GND with a resistor produces a voltage proportional to output current. This permits a user to measure system performance such as output power or if output current exceeds or falls below some threshold. The IC incorporates a unique tracking function, which if enabled by the user, controls an upsteam regulator powering the LT3071’s input (see Figure 8). This tracking function drives the buck regulator to maintain the LT3071’s input voltage to VOUT + 300mV. This input-to-output voltage control allows the user to change the regulator output voltage, and have the switching regulator powering the LT3071’s input to track to the optimum input voltage with no component changes. This combines the efficiency of a switching regulator with superior linear regulator response. It also permits thermal management of the system even with a maximum 5A output load. LT3071 internal protection includes input undervoltage lockout (UVLO), reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3071 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. The LT3071’s architecture drives an internal N-channel power MOSFET as a source follower. This configuration permits a user to obtain an extremely low dropout, UltraFast transient response regulator with excellent high frequency PSRR performance. The LT3071 achieves superior regulator bandwidth and transient load performance by eliminating expensive bulk tantalum or electrolytic capacitors in the most modern and demanding microprocessor applications. Users realize significant cost savings as all additional bulk capacitance is removed. The additional savings of insertion cost, purchasing/inventory cost and board space are readily apparent. Precision incremental output voltage control accommodates legacy and future microprocessor power supply voltages. Output capacitor networks simplify to direct parallel combinations of ceramic capacitors. Often, the high frequency ceramic decoupling capacitors required by these various 3071f  LT3071 ApplicAtions inFormAtion FPGA and ASIC processors are sufficient to stabilize the system (see Stability and Output Capacitance section). This regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. The LT3071 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection. The LT3071’s unique design combines the benefits of low dropout voltage, high functional integration, precision performance and UltraFast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the LT3071 offers superior regulation and an appreciable component cost savings. The LT3071 steps to the next level of performance for the latest generation FPGAs, DSPs and microprocessors. The simple versatility and benefits derived from these circuits exceed the power supply needs of today’s high performance microprocessors. Programming Output Voltage Three tri-level input pins, VO2, VO1 and VO0, select the value of output voltage. Table 1 illustrates the 3-bit digital word to output voltage resulting from setting these pins high, low or allowing them to float. These pins may be tied high or low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has Hi-Z output capability. This allows output voltage to be dynamically changed if necessary. Output voltage is selectable from a minimum of 0.8V to a maximum of 1.8V in increments of 50mV. The MSB, VO2, sets the pedestal voltage, and the LSB’s, VO1 and VO0 increment VOUT . Output voltage is limited to 1.8V maximum by an internal override of VO1 (default to low) when VO2 = high. Table 1: VO2 to VO0 Settings vs Output Voltage VO2 0 0 0 0 0 0 0 0 0 Z Z VO1 0 0 0 Z Z Z 1 1 1 0 0 VO0 0 Z 1 0 Z 1 0 Z 1 0 Z VOUT(NOM) 0.80V 0.85V 0.90V 0.95V 1.00V 1.05V 1.10V 1.15V 1.20V 1.25V 1.30V VO2 Z Z Z Z Z Z Z 1 1 1 VO1 0 Z Z Z 1 1 1 X X X VO0 1 0 Z 1 0 Z 1 0 Z 1 VOUT(NOM) 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V X = Don’t Care, 0 = Low, Z = Float, 1 = High The input logic low threshold is less than 250mV refer enced to GND and the logic high threshold is greater than VBIAS – 250mV. The range between these two thresholds as set by a window comparator defines the logic Hi-Z state. REF/BYP—Voltage Reference This pin is the buffered output of the internal bandgap reference and has an output impedance of ≅19kΩ. The design includes an internal compensation pole at fC = 4kHz. A 10nF REF/BYP capacitor to GND creates a lowpass pole at fLP = 840Hz. The 10nF capacitor decreases reference voltage noise to about 10µVRMS and soft-starts the reference. The LT3071 only soft-starts the reference voltage during an initial turn-on sequence. If the EN pin is toggled low after initial turn-on, the reference remains powered-up. Therefore, toggling the EN pin from low to high does not soft-start the reference. Only by turning the BIAS supply voltage on and off will the reference be soft-started. Output voltage noise is the RMS sum of the reference voltage noise in addition to the amplifier noise. 3071f  LT3071 ApplicAtions inFormAtion The REF/BYP pin must not be DC loaded by anything except for applications that parallel other LT3071 regulators for higher output currents. Consult the Applications Section on Paralleling for further details. Output Voltage Margining The LT3071’s analog margining pin, MARGA, provides a continuous output voltage adjustment range of ±10%. It margins VOUT by adjusting the internal 600mV reference voltage up and down. The MARGA pin’s typical input impedance is 190kΩ between MARGA and the internal VREF node. Driving MARGA with 600mV to 1.2V provides 0% to 10% of adjustment. Driving MARGA with 600mV to 0V provides 0% to –10% of adjustment. If unused, allow MARGA to float or bypass this pin with a 1nF capacitor to GND. Note that the analog margining function does not adjust the PWRGD threshold. Therefore, negative analog margining may trip the PWRGD comparator and toggle the PWRGD flag. Enable Function—Turning On and Off The EN pin enables/disables the output device only. The LT3071 reference and all support functions remain active if VBIAS is above its UVLO threshold. Pulling the EN pin low puts the LT3071 into nap mode. In nap mode, the reference circuit is active, but the output is disabled and quiescent current decreases. Drive the EN pin with either a digital logic port or an opencollector NPN or an open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 35k to meet the VIH condition of the EN pin. If unused, connect EN to BIAS. Input Undervoltage Lockout on BIAS Pin An internal undervoltage lockout (UVLO) comparator monitors the BIAS supply voltage. If VBIAS drops below the UVLO threshold, all functions shut down, the pass transistor is gated off and output current falls to zero. The typical BIAS pin UVLO threshold is 1.55V on the rising edge of VBIAS. The UVLO circuit incorporates about 150mV of hysteresis on the falling edge of VBIAS. High Efficiency Linear Regulator—Input-to-Output Voltage Control The VIOC (voltage input-to-output control) pin is a function to control a switching regulator and facilitate a design solution that maximizes system efficiency at high load currents and still provides low dropout voltage performance. The VIOC pin is the output of an integrated transconductance amplifier that sources and sinks about 250µA of current. It typically regulates the output of most LTC® switching regulators or LTM® power modules, by sinking current from the ITH compensation node. The VIOC function controls a buck regulator powering the LT3071’s input by maintaining the LT3071’s input voltage to VOUT + 300mV. This 300mV VIN-VOUT differential voltage is chosen to provide fast transient response and good high frequency PSRR while minimizing power dissipation and maximizing efficiency. For example, 1.5V to 1.2V conversion and 1.3V to 1V conversion yield 1.5W maximum power dissipation at 5A full output current. Figure 2 depicts that the switcher’s feedback resistor network sets the maximum switching regulator output voltage if the linear regulator is disabled. However, once the LT3071 is enabled, the VIOC feedback loop decreases the switching regulator output voltage back to VOUT + 300mV. Using the VIOC function creates a feedback loop between the LT3071 and the switching regulator. As such, the feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many LTC switching regulator ITH pins represents a high impedance characteristic which is the optimum circuit node to frequency compensate the feedback loop. Figure 2 illustrates the typical frequency compensation network used at the VIOC node to GND. The VIOC amplifier characteristics are: gm = 3.2mS, IOUT = ±250µA, BW = 10MHz. If the VIOC function is not used, terminate the VIOC pin to GND with a small capacitor (1000pF) to prevent oscillations. 3071f  LT3071 ApplicAtions inFormAtion IN SWITCHING REGULATOR REF LT3071 OUT LOAD + – PWM FB VOUT + VREF 300mV REFERENCE ITH 3071 F02 VIOC Figure 2. VIOC Control Block Diagram PWRGD—Power Good PWRGD pin is an open-drain NMOS digital output that actively pulls low if any one of these fault modes is detected: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . • VOUT drops below 85% of VOUT(NOMINAL) for more than 25µs. • VBIAS is less than its undervoltage lockout threshold. • The OUT-to-IN reverse-current detector activates. • Junction temperature exceeds 145°C typically.* *The junction temperature detector is an early warning indicator that trips approximately 20°C before thermal shutdown engages. Stability and Output Capacitance The LT3071’s feedback loop requires an output capacitor for stability. Choose COUT carefully and mount it in close proximity to the LT3071’s OUT and GND pins. Include wide routing planes for OUT and GND to minimize inductance. If possible, mount the regulator immediately adjacent to the application load to minimize distributed inductance for optimal load transient performance. Point-of-Load applications present the best case layout scenario for extracting full LT3071 performance. Low ESR, X5R or X7R ceramic chip capacitors are the LTC recommended choice for stabilizing the LT3071. Additional bulk capacitors distributed beyond the immediate decoupling capacitors are acceptable as their parasitic ESL and ESR, combined with the distributed PCB inductance isolates them from the primary compensation pole provided by the local surface mount ceramic capacitors. The LT3071 requires a minimum output capacitance of 15µF for stability. LTC strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. Why Do Multiple, Small-Value Output Capacitors Connected in Parallel Work Better? The LT3071’s unity-gain bandwidth with COUT of 15µF is about 1MHz at its full-load current of 5A. Surface mounted MLCC capacitors have a self-resonance frequency of fR = 1/(2π√LC), which must be pushed to a frequency higher than the regulator bandwidth. Standard MLCC capacitors are acceptable. To keep the resonant frequency greater than 1MHz, the product 1/(2π√LC) must be greater than 1MHz. At this bandwidth, PCB vias can add significant inductance, thus the fundamental decoupling capacitors must be mounted on the same plane as the LT3071. 3071f  LT3071 ApplicAtions inFormAtion Typical 0603 or 0805 case-size capacitors have an ESL of ~800pH and PCB mounting can contribute up to ~200pH. Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, fR, will form a tank circuit that can induce ringing of their own accord. Small amounts of ESR (5mΩ to 20mΩ) have some benefit in dampening the resonant loop, but higher ESRs degrade the capacitor response to transient load steps with rise/fall times less than 1µs. The most area efficient parallel capacitor combination is a graduated 4/2/1 scale of fR of the same case size. Under these conditions, the individual ESLs are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. The recommended parallel combination that approximates 15µF is 10µF + 4.7µF + 2.2µF . Capacitors with case sizes larger than 0805 have higher ESL and lower ESR (