LT3462A

LT3462/LT3462A Inverting 1.2MHz/2.7MHz DC/DC Converters with Integrated Schottky in ThinSOT FEATURES s s s s s s s s s s s s s DESCRIPTIO Integrated Schottky Rectifier Fixed Frequency 1.2MHz/2.7MHz Operation Very Low Noise: 1mVP-P Output Ripple Low VCESAT Switch: 270mV at 250mA –5V at 100mA from 5V Input –12V at 30mA from 3.3V Input Low Input Bias Current GND Based FB Input Low Impedance (40Ω) 1.265V Reference Output High Output Voltage: Up to – 38V Wide Input Range: 2.5V to 16V Uses Tiny Surface Mount Components Low Shutdown Current: ISDREF ≥ –80µA 10µA > ISDREF ≥ –80µA SDREF >1.2V FB = –0.05V, Not Switching SDREF = 0V, FB = Open, VIN = 5V q 1.245 1.235 –12 120 1.265 15 1.263 180 2.9 6.5 0.007 1.285 50 1.285 12 3.6 10 1.6 3.5 q q 0.8 2.0 90 77 300 1.2 2.7 420 270 0.01 0.03 800 350 1 4 1100 0.20 3 1 –300 2 –200 Note 3: The LT3462E is guaranteed to meet specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 3462af 2 U mA mV µA µA mV V µA µA W U U WW W LT3462/LT3462A TYPICAL PERFOR A CE CHARACTERISTICS Oscillator Frequency (LT3462) 1.6 1.5 CURRENT LIMIT (mA) 360 LT3462A FREQUENCY (MHz) 1.4 1.3 1.2 1.1 1.0 –40 –20 0 10 480 SDREF MINUS FB (V) 40 20 60 0 TEMPERATURE (°C) Oscillator Frequency (LT3462A) 3.2 3.0 FB BIAS CURRENT (nA) FREQUENCY (MHz) 2.8 2.6 2.4 2.2 2.0 –40 –20 TA = 25°C 0 –5 –15 –20 –25 –30 –35 –40 –45 QUIESCENT CURRENT (µA) 40 20 60 0 TEMPERATURE (°C) PI FU CTIO S SW (Pin 1): Switch Pin. Connect to external inductor L1 and positive terminal of transfer cap. GND (Pin 2): Ground. Tie directly to local ground plane. FB (Pin 3): Feedback Pin. Connect resistive divider tap here. Set R1 according to R1 = R2 • (VOUT/1.265V). In shutdown, a proprietary shutdown bias current cancellation circuit allows the internal 3µA source to pull up the SDREF pin, even with residual negative voltage on VOUT. SDREF (Pin 4): Dual Function Shutdown and 1.265V Reference Output Pin. Pull to GND with external N-FET to turn regulator off. Turn-off pull-down and a 2µA internal source will pull SDREF up to turn-on the regulator. At turnon, a 180µA internal source pulls the pin to the regulation voltage. The SDREF pin can supply up to 80µA at 1.265V to bias the feedback resistor divider. An optional soft-start circuit capacitor connects from this pin to –VOUT. D (Pin 5): Anode Terminal of Integrated Schottky Diode. Connect to negative terminal of transfer cap and external inductor L2. VIN (Pin 6): Input Supply Pin. Must be locally bypassed. 3462af UW 80 100 3462 G01 Current Limit TA = 25°C LT3462 1.29 1.28 1.27 1.26 1.25 1.24 SDREF Minus FB Pin Voltage 240 120 20 30 40 50 60 70 DUTY CYCLE (%) 80 90 1.23 –40 –20 40 20 60 0 TEMPERATURE (°C) 80 100 3462 G02 3462 G03 FB Bias Current 10 Quiescent Current in Shutdown Mode TA = 25°C FB = N/C –10 8 6 4 2 80 100 –50 –40 0 –20 0 20 40 60 TEMPERATURE (°C) 80 100 3462 G05 0 4 8 12 16 3462 G06 SUPPLY VOLTAGE (V) 3462 G04 U U U 3 LT3462/LT3462A BLOCK DIAGRA FB 3 SDREF 4 SHUTDOWN BIAS CURRENT CANCELLATION OFF → 3µA ON → 180µA SHUTDOWN VIN 6 1.265V REFERENCE OPERATIO The LT3462 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. At the start of each oscillator cycle, the SR latch is set, turning on the power switch Q1. A voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator. When this voltage exceeds the voltage at the output of the EAMP, the SR latch is reset, turning off the power switch. The level at the output of the EAMP is simply an amplified version of the difference between the feedback voltage and GND. In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. If the error amplifier’s output increases, more current is taken from the output; if it decreases, less current is taken. One function not shown in Figure 1 is the current limit. The switch current is constantly monitored and not allowed to exceed the nominal value of 400mA. If the switch current reaches 400mA, the SR latch is reset regardless of the 4 W 1 SW 5D – A1 E AMP – RC CC A2 COMP R S Q DRIVER Q1 DO LG + + ∑ + 0.1Ω ISRC RAMP GENERATOR VOUT 1.2MHz* OSCILLATOR *LT3462A IS 2.7MHz R1 (EXTERNAL) FB R2 (EXTERNAL) Q2 SDREF CS1, CS2 OPTIONAL SOFT-START COMPONENTS 3462 F02 – 2 GND VOUT CS1 (EXTERNAL) SDREF CS2 (EXTERNAL) – + Figure 1. Block Diagram U output state of the PWM comparator. This current limit cell protects the power switch as well as various external components connected to the LT3462. SDREF is a dual function input pin. When driven low it shuts the part down, reducing quiescent supply current to less than 10µA. When not driven low, the SDREF pin has an internal pull-up current that turns the regulator on. Once the part is enabled, the SDREF pin sources up to 180µA nominally at a fixed voltage of 1.265V through external resistor R2 to FB. If there is no fault condition present, FB will regulate to 0V, and VOUT will regulate to 1.265V • (–R1/R2). An optional soft-start circuit uses the fixed SDREF pull-up current and a capacitor from SDREF to VOUT to set the dV/dt on VOUT. In shutdown, an FB bias current cancellation circuit supplies up to 150µA biasing current to external resistor R1 while VOUT is lower than FB. This function eliminates R2 loading of SDREF during shutdown. As a result, supply current in shutdown may exceed 10µA by the amount of current flowing in R1. 3462af LT3462/LT3462A APPLICATIO S I FOR ATIO Inrush Current The LT3462 has a built-in Schottky diode. When supply voltage is applied to the VIN pin, the voltage difference between VIN and VD generates inrush current flowing from input through the inductor and the Schottky diode to charge the flying capacitor to VIN. The maximum nonrepetitive surge current the Schottky diode in the LT3462 can sustain is 1.5A. The selection of inductor and capacitor value should ensure the peak of the inrush current to be below 1.5A. The peak inrush current can be calculated as follows:    π VIN – O.6  – exp IP =  L L –1 – 1 2  C C where L is the inductance between supply and SW, and C is the capacitance between SW and D. Table 3 gives inrush peak currents for some component selections. Table 3. Inrush Peak Current VIN (V) 5 5 12 L (µH) 22 33 47 C (µF) 1 1 1 IP (A) 0.70 0.60 1.40 Inductor Selection Each of the two inductors used with LT3462 should have a saturation current rating (where inductance is approximately 70% of zero current inductance ) of approximately 0.25A or greater. If the device is used in the charge pump mode, where there is only one inductor, then its rating should be 0.35A or greater. DCR of the inductors should be less than 1Ω. For LT3462, a value of 22µH is suitable if using a coupled inductor such as Sumida CLS62-220. If using two separate inductors, increasing the value to 47µH will result in the same ripple current. For LT3462A, a value of 10µH for the coupled inductor and 22µH for two inductors will be acceptable for most applications. C3 R1 U Capacitor Selection Ceramic capacitors are recommended. An X7R or X5R dielectric should be used to avoid capacitance decreasing severely with applied voltage and at temperature limits. The “flying” capacitor between the SW and D pins should be a ceramic type of value 1µF or more. When used in the dual inductor or coupled inductor topologies the flying capacitor should have a voltage rating that is more than the difference between the input and output voltages. For the charge pump inverter topology, the voltage rating should be more than the output voltage. The output capacitor should be a ceramic type. Acceptable output capacitance varies from 1µF for high VOUT (–36V), to 10µF for low VOUT (–5V). The input capacitor should be a 1µF ceramic type and be placed as close as possible to the LT3462/LT3462A. Layout Hints The high speed operation of the LT3462 demands careful attention to board layout. You will not get advertised performance with careless layout. Figure 2 shows the recommended component placement. A ceramic capacitor of 1µF or more must be placed close to the IC for input supply bypassing. C1 W UU + GND L1 VIN 1 2 3 R2 6 5 4 L2 C2 C4 VOUT 3462 F03 Figure 2. Suggested Layout 3462af 5 LT3462/LT3462A TYPICAL APPLICATIO S 3.3V to –12V with Soft-Start Circuit L1 47µH C2 1µF L2 47µH 80 75 TA = 25°C VIN 3.3V C1 4.7µF SW VIN D FB R1 267k R2 27.4k C4 15pF CS1 100nF EFFICIENCY (%) LT3462 SDREF GND OFF C1: TAIYO YUDEN X5R JMK212BJ475MG C2: TAIYO YUDEN X5R EMK212BJ105MG C3: TAIYO YUDEN EMK316BJ225 L1, L2: MURATA LQH32CN470 VOUT Reaches –12V in 750µs; Input Current Peaks at 300mA without CS1 OFF OFF VOUT 10V/DIV IIN 100mA/DIV 2ms/DIV 3462 TA02c Li+ to –8V Supply VIN 2.7V TO 4.2V L1A 22µH C2 1µF L1B 22µH 80 75 TA = 25°C C1 4.7µF SW VIN LT3462 D FB R1 267k R2 42.2k C4 15pF C3 4.7µF EFFICIENCY (%) SDREF GND C1: TAIYO YUDEN X5R JMK212BJ475MG C2: TAIYO YUDEN X5R EMK212BJ105MG C3: TAIYO YUDEN LMK316BJ475 L1: SUMIDA CLS62-220 OR 2X MURATA LQH32CN330 6 U –12V Efficiency VOUT –12V 30mA C3 2.2µF VIN = 3.3V 70 65 60 55 M1 22nF 50 3462 TA02a 0 5 10 15 20 25 LOAD CURRENT (mA) 30 35 3462 TA02b VOUT Reaches –12V in 7.5ms; Input Current Peaks at 125mA with CS1 = 100nF VOUT 10V/DIV IIN 50mA/DIV 2ms/DIV 3462 TA02d –8V Efficiency VIN = 3.3V VOUT –8V 70 65 60 55 50 3462 TA03a 0 10 20 30 40 LOAD CURRENT (mA) 50 3462 TA03b 3462af LT3462/LT3462A TYPICAL APPLICATIO S 3.3V to –8V (LT3462A) VIN 2.7V TO 4.2V L1A 10µH C2 1µF L1B 10µH VIN 5V VOUT –8V 35mA C1 1µF SW VIN D FB C1 1µF SW VIN D FB LT3462A SDREF GND C1: TAIYO YUDEN JMK107BJ105MA C2: TAIYO YUDEN EMK212BJ105MA C3: TAIYO YUDEN LMK316BJ475 .. L1: WURTH 50310057-100 PACKAGE DESCRIPTIO 0.62 MAX 0.95 REF 3.85 MAX 2.62 REF RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.20 BSC DATUM ‘A’ 0.30 – 0.50 REF Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U 5V to –5V Supply (LT3462A) L1 22µH C2 1µF L2 22µH R1 267k R2 42.2k C4 22pF R1 267k R2 68.1k C4 22pF VOUT –5V 100mA C3 10µF C3 4.7µF LT3462A SDREF GND 3462 TA04a C1: TAIYO YUDEN JMK107BJ105MA C2: TAIYO YUDEN EMK212BJ105MA C3: MURATA GRM219R60J106KE19B L1, L2: MURATA LQH32CN220 3462 TA05a Switching Waveform INDUCTOR 50mA/DIV VSW 10V/DIV VOUT 1mV/DIV AC COUPLED 200ns/DIV 3462 TA05b S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 2.90 BSC (NOTE 4) 1.22 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID 0.95 BSC 0.80 – 0.90 0.09 – 0.20 (NOTE 3) 1.00 MAX 0.30 – 0.45 6 PLCS (NOTE 3) 0.01 – 0.10 1.90 BSC S6 TSOT-23 0302 3462af 7 LT3462/LT3462A TYPICAL APPLICATIO S 12V to –36V DC/DC Converter L1 47µH C2 0.47µF VIN 12V C1 1µF SW VIN LT3462 D FB R1 432k R2 15k 100nF EFFICIENCY (%) SDREF GND C1: TAIYO YUDEN X5R EMK212BJ105 C2: MURATA GRM42-6X7R474K50 C3: MURATA GRM42-6X7R474K50 ×2 D1: CENTRAL CMSH5-4-LTN L1: MURATA LQH32CN470 RELATED PARTS PART NUMBER LT1617/LT1617-1 LT1931/LT1931A LT1945 LT1946/LT1946A LT3463 DESCRIPTION 350mA/100mA (ISW) High Efficiency Micropower Inverting DC/DC Converter 1A (ISW), 1.2MHz/2.2MHz, High Efficiency Micropower Inverting DC/DC Converter Dual Output, Boost/Inverter, 350mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter 1.5A (ISW), 1.2MHz/2.7MHz, High Efficiency Step-Up DC/DC Converter Dual Output, Boost/Inverter, 250mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter with Integrated Schottky Diodes 85mA (ISW), High Efficiency Step-Up DC/DC Converter with Integrated Schottky and PNP Disconnect COMMENTS VIN: 1.2V to 15V, VOUT(MAX) = –34V, IQ = 20µA, ISD