LT3579EFE-1-PBF

LT3579/LT3579-1 6A Boost/Inverting DC/DC Converter with Fault Protection FEATURES n n n n n n n n n n n n DESCRIPTION The LT®3579 is a PWM DC/DC converter with built-in fault protection features to aid in protecting against output shorts, input/output overvoltage, and overtemperature conditions. The part consists of a 42V master switch, and a 42V slave switch that can be tied together for a total current limit of 6A. The LT3579 is ideal for many local power supply designs. It can be easily configured in Boost, SEPIC, Inverting, or Flyback configurations, and is capable of generating 12V at 1.7A, or –12V at 1.2A from a 5V input. In addition, the LT3579’s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are very efficient and require fewer components than traditional circuits. The LT3579’s switching frequency range can be set between 200kHz and 2.5MHz. The part may be clocked internally at a frequency set by the resistor from the RT pin to ground, or it may be synchronized to an external clock. A buffered version of the clock signal is driven out of the CLKOUT pin, and may be used to synchronize other compatible switching regulator ICs to the LT3579. The LT3579 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT3579 is available in 20-lead TSSOP and 20-pin 4mm × 5mm QFN packages. 6A, 42V Combined Power Switch Output Short Circuit Protection Wide Input Range: 2.5V to 16V Operating, 40V Maximum Transient LT3579-1: Dual-Phase Capable Master/Slave (3.4A/2.6A) Switch Design User Configurable Undervoltage Lockout Easily Configurable as a Boost, SEPIC, Inverting, or Flyback Converter Low VCESAT Switch: 250mV at 5.5A (Typical) Can be Synchronized to External Clock Can Synchronize other Switching Regulators High Gain SHDN Pin Accepts Slowly Varying Input Signals 20-Lead TSSOP and 20-Pin 4mm × 5mm QFN Packages APPLICATIONS n n n n Local Power Supply Vacuum Flourescent Display (VFD) Bias Supplies TFT-LCD Bias Supplies Automotive Engine Control Unit (ECU) Power L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7579816. TYPICAL APPLICATION 1MHz, 5V to 12V Boost Converter with Output Short Circuit Protection VIN 5V 2.2μH 10μF 130k FB GATE LT3579 SHDN RT SYNC GND 86.6k CLKOUT VC SS 0.1μF 47pF TEMPERATURE MONITOR 8k 2.2nF 3579 TA01 Efficiency and Power Loss 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0 0.25 0.5 0.75 1 1.25 1.5 1.75 LOAD CURRENT (A) 2 35791f 35791 TA02 3.2 2.8 2.4 POWER LOSS (W) 2.0 1.6 1.2 0.8 0.4 0 VOUT 12V 1.7A 6.3k 10μF SW1 SW2 22μF VIN 100k 200k FAULT VIN 1 LT3579/LT3579-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltage ................................................. –0.3V to 40V SW1/SW2 Voltage ..................................... –0.4V to 42V RT Voltage .................................................... –0.3V to 5V SS, FB Voltage ......................................... –0.3V to 2.5V VC Voltage ................................................... –0.3V to 2V SHDN Voltage ............................................ –0.3V to 40V SYNC Voltage ............................................ –0.3V to 5.5V GATE Voltage ............................................. –0.3V to 80V FAULT ......................................................... –0.3V to 40V FAULT Current .....................................................±0.5mA CLKOUT ....................................................... –0.3V to 3V CLKOUT Current ....................................................±1mA Operating Junction Temperature Range LT3579E (Notes 2, 4) .........................–40°C to 125°C LT3579I (Notes 2, 4) ..........................–40°C to 125°C Storage Temperature Range...................–65°C to 150°C PIN CONFIGURATION TOP VIEW FB VC GATE FAULT VIN SW1 SW1 SW1 SW1 1 2 3 4 5 6 7 8 9 21 GND 20 SYNC 19 SS 18 RT 17 SHDN 16 CLKOUT 15 SW2 14 SW2 13 SW2 12 SW2 11 SW2 GATE 1 FAULT 2 VIN 3 SW1 4 SW1 5 SW1 6 7 SW1 8 GND 9 10 GND SW2 21 GND TOP VIEW SYNC 16 RT 15 SHDN 14 CLKOUT 13 SW2 12 SW2 11 SW2 SS VC FB 20 19 18 17 SW1 10 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB UFD PACKAGE 20-LEAD (4mm 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W, θJC = 2.7°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LT3579EFE#PBF LT3579IFE#PBF LT3579EUFD#PBF LT3579IUFD#PBF LT3579EFE-1#PBF LT3579IFE-1#PBF LT3579EUFD-1#PBF LT3579IUFD-1#PBF TAPE AND REEL LT3579EFE#TRPBF LT3579IFE#TRPBF LT3579EUFD#TRPBF LT3579IUFD#TRPBF LT3579EFE-1#TRPBF LT3579IFE-1#TRPBF LT3579EUFD-1#TRPBF LT3579IUFD-1#TRPBF PART MARKING* LT3579FE LT3579FE 3579 3579 LT3579FE-1 LT3579FE-1 35791 35791 PACKAGE DESCRIPTION 20-Lead Plastic TSSOP 20-Lead Plastic TSSOP 20-Lead (4mm × 5mm) Plastic QFN 20-Lead (4mm × 5mm) Plastic QFN 20-Lead Plastic TSSOP 20-Lead Plastic TSSOP 20-Lead (4mm × 5mm) Plastic QFN 20-Lead (4mm × 5mm) Plastic QFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 35791f 2 LT3579/LT3579-1 ELECTRICAL CHARACTERISTICS PARAMETER Minimum Input Voltage VIN Overvoltage Lockout Positive Feedback Voltage Negative Feedback Voltage Positive FB Pin Bias Current Negative FB Pin Bias Current Error Amp Transconductance Error Amp Voltage Gain Quiescent Current Quiescent Current in Shutdown Reference Line Regulation Switching Frequency, fOSC Switching Frequency in Foldback Switching Frequency Range SYNC High Level for Sync SYNC Low Level for Sync SYNC Clock Pulse Duty Cycle Recommended Minimum SYNC Ratio fSYNC/fOSC Minimum Off-Time Minimum On-Time SW1 Current Limit SW Current Sharing, ISW2/ISW1 SW1 + SW2 Current Limit Switch VCESAT SW1 Leakage Current SW2 Leakage Current At All Duty Cycles (Note 3) SW1 and SW2 Tied Together ISW2/ISW1 = 0.78, At All Duty Cycles (Note 3) SW1 and SW2 Tied Together, ISW1 + ISW2 = 5.5A VSW1 = 5V VSW2 = 5V l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN unless otherwise noted. (Note 2). CONDITIONS l MIN 16.2 1.195 3 80.5 81 TYP 2.3 18.7 1.215 9 83.3 83.3 250 70 1.9 0 0.01 MAX 2.5 21.2 1.230 16 85 85.5 UNITS V V V mV μA μA μmhos V/V VFB=Positive Feedback Voltage, Current into Pin VFB=Negative Feedback Voltage, Current out of Pin ΔI=10μA Not Switching VSHDN = 0V 2.5V ≤ VIN ≤ 15V RT = 34kΩ RT = 432kΩ Compared to Normal fOSC Free-Running or Synchronizing 2.4 1 0.05 2.8 225 2500 0.4 mA μA %/V MHz kHz ratio kHz V V % l l l l l 2.2 175 200 1.3 20 2.5 200 1/6 VSYNC = 0V to 2V 80 3/4 45 55 nS nS 5.1 9.4 350 1 1 A A/A A mV μA μA 3.4 6 4.2 0.78 7.5 250 0.01 0.01 35791f 3 LT3579/LT3579-1 ELECTRICAL CHARACTERISTICS PARAMETER Soft-Start Charge Current Soft-Start Discharge Current CONDITIONS VSS = 30mV, Current Flows Out of SS pin Part in FAULT VSS = 2.1V, Current Flows into SS Pin Part in FAULT Part Exiting FAULT Active Mode, SHDN Rising Active Mode, SHDN Falling Shutdown Mode VSHDN = 3V VSHDN = 1.3V VSHDN = 0V CCLKOUT = 50pF CCLKOUT = 50pF LT3579, TJ = 25°C LT3579-1, All TJ CLKOUT Rise Time CLKOUT Fall Time GATE Pull Down Current GATE Leakage Current FAULT Output Voltage Low FAULT Leakage Current FAULT Input Voltage Low Threshold FAULT Input Voltage High Threshold Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3579E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3579I is guaranteed over the full –40°C to 125°C operating junction temperature range. CCLKOUT = 50pF CCLKOUT = 50pF VGATE = 3V VGATE = 80V VGATE = 50V, GATE Off 100μA into FAULT Pin VFAULT = 40V, FAULT Off l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN unless otherwise noted. (Note 2). MIN 5.7 5.7 1.65 30 1.27 1.24 TYP 8.7 8.7 1.8 50 1.33 1.3 40 11.4 0 2.1 100 42 50 12 8 800 800 933 933 0.01 150 0.01 700 950 750 1000 1100 1100 1 300 1 800 1050 MAX 11.3 11.3 1.95 85 1.41 1.38 .3 9.5 1.9 60 13.4 0.1 2.3 200 UNITS μA μA V mV V V V μA μA μA V mV % % ns ns μA μA μA mV μA mV mV Soft-Start High Detection Voltage Soft-Start Low Detection Voltage SHDN Minimum Input Voltage High SHDN Input Voltage Low SHDN Pin Bias Current CLKOUT Output Voltage High CLKOUT Output Voltage Low CLKOUT Duty Cycle Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. 35791f 4 LT3579/LT3579-1 TYPICAL PERFORMANCE CHARACTERISTICS Switch Current Limit 10 9 SATURATION VOLTAGE (mV) SW1 + SW2 CURRENT (A) 8 7 6 5 4 3 2 1 0 20 30 50 40 60 DUTY CYCLE (%) 70 80 35791 G01 TA = 25°C, unless otherwise noted. Switch Saturation Voltage 350 300 VSW1 = VSW2 250 ISW2/ISW1 (A/A) 200 150 100 50 0 0 1 3 2 4 5 6 SW1 + SW2 CURRENT (A) 7 8 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.0 0.9 Switch Current Sharing 0 0.5 1 1.5 2 2.5 3 SW1 CURRENT (A) 3.5 4 35791 G02 35791 G03 Switch Current Limit vs Temperature 10 9 SW1 + SW2 CURRENT (A) SW1 + SW2 CURRENT (A) 8 7 6 5 4 3 2 1 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G04 Commanded Switch Current vs SS 10 9 8 FB VOLTAGE (V) 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 SS VOLTAGE (V) 1 1.2 35791 G05 Positive Feedback Voltage 1.23 1.225 1.22 1.215 1.21 1.205 1.2 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G06 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –50 –25 NORMALIZED OSCILLATOR FREQUENCY (FSW/FNOM) Oscillator Frequency Oscillator Frequency During Soft-Start 1 80 70 CLKOUT DUTY CYCLE (%) 60 50 40 30 20 CLKOUT Duty Cycle RT = 34k FREQUENCY (MHz) 1/2 1/3 1/4 1/5 1/6 0 0 RT = 432k 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G07 INVERTING CONFIGURATIONS 0.2 BOOSTING CONFIGURATIONS 1 1.2 35791 G08 0.4 0.6 0.8 FB VOLTAGE (V) 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G09 35791f 5 LT3579/LT3579-1 TYPICAL PERFORMANCE CHARACTERISTICS CLKOUT Rise Time at 1MHz 50 45 CLKOUT RISE OR FALL TIME (ns) 40 GATE PIN CURRENT (μA) 35 30 25 20 15 10 5 0 0 50 100 150 200 CLKOUT CAPACITIVE LOAD (pF) 250 35791 G10 35791 G11 35791 G12 TA = 25°C, unless otherwise noted. Gate Pin Current (VSS = 2.1V) 1000 900 GATE PIN CURRENT (μA) 1000 900 TA = –40°C TA = 25°C TA = 125°C 800 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 GATE PIN VOLTAGE (V) 70 80 Gate Pin Current (VGATE = 5V) CLKOUT RISE TIME 800 700 600 550 400 300 200 100 0 CLKOUT FALL TIME 0 0.25 0.5 0.75 1 SS VOLTAGE (V) 1.25 1.5 Active/Lockout Threshold 1.4 1.38 SHDN PIN CURRENT (μA) 30 25 20 15 10 5 SHDN Pin Current 250 SHDN Pin Current TA = – 40°C SHDN PIN CURRENT (μA) 1.36 SHDN VOLTAGE (V) 1.34 1.32 1.3 1.28 1.26 1.24 1.22 1.2 –50 –25 SHDN RISING 200 TA = 25°C 150 TA = 125°C SHDN FALLING 100 TA = 25°C TA = 125°C 50 TA = – 40°C 2 0 0 5 10 15 20 25 30 SHDN VOLTAGE (V) 35 40 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G13 0 0.25 0.5 0.75 1 1.25 1.5 1.75 SHDN VOLTAGE (V) 35791 G14 35791 G15 Internal UVLO 2.5 2.45 2.4 VIN VOLTAGE (V) 2.35 2.3 2.25 2.2 2.15 2.1 –50 –25 VIN VOLTAGE (V) 22 21 20 VIN OVLO 1.25 Fault Input Threshold FAULT RISING 1 FAULT VOLTAGE (V) 19 18 17 16 15 14 13 0.75 FAULT FALLING 0.5 0.25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G16 12 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G17 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35791 G18 35791f 6 LT3579/LT3579-1 PIN FUNCTIONS (QFN/TSSOP) GATE (Pin 1/Pin 3): PMOS Gate Drive Pin. The GATE pin is a pull-down current source, and can be used to drive the gate of an external PMOS transistor for output short circuit protection or output disconnect. The GATE pin current increases linearly with the SS pin’s voltage, with a maximum pull-down current of 933μA at SS voltages exceeding 500mV. Note that if the SS voltage is greater than 500mV, and the GATE pin voltage is less than 2V, the GATE pin looks like a 2kΩ impedance to ground. See the Appendix for more information. FAULT (Pin 2/Pin 4): Fault Indication Pin. This active low, bidirectional pin can either be pulled low (below 750mV) by an external source, or internally by the chip to indicate a fault. When pulled low, this pin causes the power switches to turn off, the GATE pin to become high impedance, the CLKOUT pin to become disabled, and the SS pin to go through a charge/discharge sequence. The end/absence of a fault is indicated when the voltage on this pin exceeds 1V. A pull-up resistor or some other form of pull-up network needs to exist on this pin to pull it above 1V in the absence of a fault. VIN (Pin 3/Pin 5): Input Supply Pin. Must be locally bypassed. SW1 (Pins 4 - 7/Pins 6 - 10): Master Switch Pin. This is the collector of the internal master NPN power switch. SW1 is designed to handle a peak collector current of 3.4A (minimum). Minimize the metal trace area connected to this pin to minimize EMI. GND (Pins 8, 9, Exposed Pad Pin 21/Exposed Pad Pin 21): Ground. Must be soldered directly to local ground plane. SW2 (Pins 10-13/Pins 11-15): Slave Switch Pin. This is the collector of the internal slave NPN power switch. SW2 is designed to handle a peak collector current of 2.6A (minimum). Minimize the metal trace area connected to this pin to minimize EMI. CLKOUT (Pin 14/Pin 16): Clock Output Pin. Use this pin to synchronize one or more other ICs to the LT3579. This pin oscillates at the same frequency as the internal oscillator of the part or as the SYNC pin. CLKOUT may also be used as a temperature monitor since the CLKOUT pin’s duty cycle varies linearly with the part’s junction temperature. The CLKOUT pin signal of the LT3579-1 is 180° out of phase with the internal oscillator or SYNC pin, and the duty cycle is fixed at ~50%. The LT3579-1 is useful for multiphase switching regulators. SHDN (Pin 15/Pin 17): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 0.3V to disable the chip with very low quiescent current. Drive above 1.33V (typical) to activate the chip and restart the soft-start sequence. Do not float this pin. RT (Pin 16/Pin 18): Timing Resistor Pin. Adjusts the LT3579’s switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. SYNC (Pin 17/Pin 20): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must exceed 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. SS (Pin 18/Pin 19): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 250kΩ resistor to ~2.1V. During a fault, the SS pin will be slowly charged up and discharged as part of a timeout sequence. VC (Pin 19/Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. FB (Pin 20/Pin 1): Positive and Negative Feedback Pin. For a Boost or Inverting Converter, tie a resistor from the FB pin to VOUT according to the following equations: ⎛V – 1.215V ⎞ RFB = ⎜ OUT ⎟ ; Boost or SEPIC Converter 83.3µA ⎝ ⎠ ⎛ | V | +9mV ⎞ RFB = ⎜ OUT ⎟ ; Inverting Converter ⎝ 83.3µA ⎠ 35791f 7 LT3579/LT3579-1 BLOCK DIAGRAM OPTIONAL L1 VIN CIN COUT1 RFAULT RGATE D1 M1 VOUT COUT GATE 933μA VC 2.1V FAULT SOFTSTART DIE TEMP 16.2V VIN 165°C 750mV 42V (MIN) SW2 42V (MIN) ISW1 3.4A (MIN) TD ~ 30ns 50mV 1.8V 250k SS CSS SHDN 1.33V + – + – + – UVLO COMPARATOR SR1 – A3 R S Q VIN 1.215V REFERENCE + + + A1 14.6k FB ∑ RAMP GENERATOR FREQUENCY FOLDBACK ÷N ADJUSTABLE OSCILLATOR SS SYNC BLOCK VC RC CC RT SYNC RT CLKOUT – + 14.6k A2 – ** SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3579/LT3579-1 DURING SW OVERVOLTAGE EVENTS. Figure 1. Block Diagram 8 + – DRIVER DISABLE VBE • 0.9 Q2 SW1 15.4m Q1 DRIVER A4 – GND – + + – STARTUP & FAULT LOGIC ** + – – + ** + – SW1 1.17V + – – + + – FB 45mV SW2 RS 12m RFB 3579 BD 35791f LT3579/LT3579-1 STATE DIAGRAM SHDN < 1.33V OR VIN < 2.3V CHIP OFF • ALL SWITCHES DISABLED • IGATE OFF • FAULTS CLEARED SHDN > 1.33V AND VIN > 2.3V INITIALIZE • SS PULLED LOW FAULT1 FAULT2 SS < 50mV SOFT START • IGATE ENABLED • SS CHARGES UP • SWITCHER ENABLED FAULT1 FAULT DETECTED • SS CHARGES UP • IGATE OFF • FAULT PULLED LOW INTERNALLY BY LT3579 • SWITCHER DISABLED • CLKOUT DISABLED SS > 1.8V AND NO FAULT1 CONDITIONS STILL DETECTED POST FAULT DELAY SAMPLE MODE • Q1 & Q2 SWITCHES FORCED ON EVERY CYCLE FOR AT LEAST MINIMUM ON-TIME • IGATE FULLY ACTIVATED WHEN SS > 500mV • SS SLOWLY DISCHARGES FAULT1 FAULT1 SS < 50mV LOCAL FAULT OVER • INTERNAL FAULT PULLDOWN RELEASED BY LT3579 • SS CONTINUES DISCHARGING TO GND NORMAL MODE • NORMAL OPERATION • CLKOUT ENABLED WHEN SS > 1.8V FAULT1 FAULT > 1.0V FAULT1 IF |VOUT| DROPS CAUSING: FB < 1.17V (BOOST) OR FB > 45mV (INVERTING) FAULT1 = OVER VOLTAGE PROTECTION ON VIN (VIN > 16.2V (MIN)) OVER TEMPERATURE (TJUNCTION > 165°C (TYP)) OVER CURRENT ON SW1 (ISW1 > 3.4A (MIN)) OVER VOLTAGE PROTECTION ON SW1 (VSW1 > 42V (MIN)) OVER VOLTAGE PROTECTION ON SW1 (VSW2 > 42V (MIN)) FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V) 3759 SD Figure 2. State Diagram 35791f 9 LT3579/LT3579-1 OPERATION OPERATION – OVERVIEW The LT3579 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function, together with soft-start and frequency foldback, offers a controlled means of starting up. Fault features are incorporated in the LT3579 to aid in the detection of output shorts, overvoltage, and overtemperature conditions. Refer to the Block Diagram (Figure 1) and the State Diagram (Figure 2) for the following description of the part’s operation. OPERATION – START-UP Several functions are provided to enable a very clean start-up for the LT3579. Precise Turn-On Voltage The SHDN pin compares to an internal voltage reference to give a precise turn on voltage level. Taking the SHDN pin above 1.33V (typical) enables the part. Taking the SHDN pin below 0.3V shuts down the chip, resulting in extremely low quiescent current. The SHDN pin has 30mV of hysteresis to protect against glitches and slow ramping. Undervoltage-Lockout (UVLO) The SHDN pin can also be used to create a configurable UVLO. The UVLO function sets the turn on/off of the LT3579 at a desired input voltage (VINUVLO). Figure 3 shows how a resistor divider (or single resistor) from VIN to the SHDN pin can be used to set VINUVLO. RUVLO2 is optional. It may be left out, in which case set it to infinite in the equation below. For increased accuracy, set RUVLO2 ≤ 10kΩ. Pick RUVLO1 as follows: RUVLO1 = VINUVLO – 1.33V ⎛ 1.33V ⎜ ⎜R ⎝ UVLO2 ⎞ ⎟ + 11.6µA ⎟ ⎠ VIN RUVLO1 SHDN RUVLO2 (OPTIONAL) VIN 1.33V – + ACTIVE/ LOCKOUT 11.6μA AT 1.33V GND 3579 F03 Figure 3. Configurable UVLO The LT3579 also has internal UVLO circuitry that disables the chip when VIN < 2.3V (typical). Soft-Start of Switch Current The soft-start circuitry provides for a gradual ramp-up of the switch current (refer to Commanded Switch Current vs. SS in Typical Performance Characteristics). When the part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic circuits in the chip. Then an integrated 250k resistor pulls the SS pin to ~1.8V at a ramp rate set by the external capacitor connected to the pin. Once SS gets to 1.8V, the CLKOUT pin is enabled, and an internal regulator pulls the pin up quickly to ~2.1V. Typical values for the external soft-start capacitor range from 100nF to 1μF. Soft-Start of External PMOS (if used) The soft-start circuitry also gradually ramps up the GATE pin pull-down current which allows an external PMOS to slowly turn on (M1 in Block Diagram). The GATE pin current increases linearly with SS voltage, with a maximum current of 933μA when the SS voltage gets above 500mV. Note that if the GATE pin voltage is less than 2V for SS voltages exceeding 500mV, then the GATE pin impedance to ground is 2kΩ. The soft turn on of the external PMOS helps limit inrush current at start-up, making hot plugs of the LT3579 feasible and safe. 35791f 10 LT3579/LT3579-1 OPERATION Sample Mode Sample Mode is the mechanism used by the LT3579 to aid in the detection of output shorts. It refers to a state of the LT3579 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch current limit of 3.4A (minimum), the LT3579 triggers an overcurrent fault internally (see Operation-Fault section for details). Sample Mode exists when FB is out of regulation by more than 3.7% or 45mV < FB < 1.17V (typical). The LT3579’s power switches are designed to handle a total peak current of 6A (minimum). Frequency Foldback The frequency foldback circuit reduces the switching frequency when 350mV < FB < 900mV (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current during start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal. Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target VOUT, VIN, switching frequency, etc. Test the application’s performance at start-up to ensure that the peak inductor current does not exceed the minimum current limit. OPERATION – REGULATION The following description of the LT3579’s operation assumes the FB voltage is close enough to its regulation target so that the part is not in Sample Mode. Use the Block Diagram as a reference when stepping through the following description of the LT3579 operating in regulation. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switches Q1 and Q2. The collector current through the master switch, Q1, is ~1.3 times the collector current through the slave switch, Q2, when the collectors of the two switches are tied together. Q1’s emitter current flows through a current sense resistor (RS) generating a voltage proportional to the total switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When the voltage on the positive input of A3 exceeds the voltage on the negative input, the SR latch is reset, turning off the master and slave power switches. The voltage on the negative input of A3 (VC pin) is set by A1 (or A2), which is simply an amplified difference between the FB pin voltage and the reference voltage (1.215V if the LT3579 is configured as a boost converter, or 9mV if configured as an inverting converter). In this manner, the error amplifer sets the correct peak current level to maintain output regulation. As long as the part is not in fault (see Operation – FAULT section) and the SS pin exceeds 1.8V, the LT3579 drives its CLKOUT pin at the frequency set by the RT pin or the SYNC pin. The CLKOUT pin can synchronize other compatible switching regulator ICs (including additional LT3579s) with the LT3579. Additionally, the duty cycle of CLKOUT varies linearly with the part’s junction temperature and may be used as a temperature monitor. The CLKOUT signal on the LT3579-1 is ~180° out of phase with the internal oscillator and has a fixed duty cycle of ~50%. OPERATION – FAULT The LT3579’s FAULT pin is an active low, bidirectional pin (refer to Block Diagram) that pulls low to indicate a fault. Each of the following events can trigger a fault in the LT3579: A. FAULT1 Events: 1. SW Overcurrent a. ISW1 > 3.4A (minimum) b. (ISW1 + ISW2) > 6A (minimum) 2. VIN Voltage > 16.2V (minimum) 3. SW1 Voltage and/or SW2 Voltage > 42V (minimum) 4. Die Temperature > 165°C B. FAULT2 Events: 1. Pulling the FAULT pin low externally 35791f 11 LT3579/LT3579-1 OPERATION When a fault is detected, in addition to the FAULT pin being pulled low internally, the LT3579 also disables its CLKOUT pin, turns off its power switches, and the GATE pin becomes high impedance (refer to the State Diagram). The external PMOS, M1, turns off when the gate of M1 is pulled up to its source by the external RGATE resistor (see Block Diagram) With the external PMOS turned off, the power path from VIN to VOUT is cut off, protecting power components downstream. At the same time, a timeout sequence commences where the SS pin is charged up to 1.8V (the SS pin will continue charging up to ~2.1V and be held there in the case of a FAULT1 event still existing), and then discharged to 50mV. This timeout period relieves the part, the PMOS, and other downstream power components from electrical and thermal stress for a minimum amount of time as set by the voltage ramp rate on the SS pin. In the absence of faults, the FAULT pin is pulled high by the external RFAULT resistor (typically 100k). Figures 4 and 5 show the events that accompany the detection of an output short on the LT3579. VOUT 10V/DIV CLKOUT 2V/DIV IL 5A/DIV FAULT 5V/DIV 10μs/DIV 35791 F04 Figure 4. Output Short Circuit Protection of the LT3579 SS 2V/DIV GATE 5V/DIV IL 5A/DIV FAULT 5V/DIV 50ms/DIV 35791 F05 Figure 5. Continuous Output Short Showing FAULT Timeout Cycle 35791f 12 LT3579/LT3579-1 APPLICATIONS INFORMATION BOOST CONVERTER COMPONENT SELECTION VIN 5V L1 2.2μH D1 30V, 4A COUT1 10μF RFB 130k FB GATE LT3579 200k CIN 22μF SHDN RT SYNC GND RT 86.6k CLKOUT VC SS CSS 0.1μF CF 47pF RC 8k CC 2.2nF 37591 F06 Table 1. Boost Design Equations PARAMETERS/EQUATIONS VOUT 12V 1.7A OPTIONAL M1 Step 1: Inputs Step 2: DC Pick VIN, VOUT, and fOSC to calculate equations below. SW1 SW2 100k VIN FAULT RGATE 6.3k VIN DC ≅ COUT 10μF VOUT – VIN + 0.5V VOUT + 0.5V – 0.27 V (1) L TYP = LMIN = Step 3: L1 ( VIN – 0.27V ) • DC fOSC • 1.8 A LMAX ( VIN – 0.27V ) • (2 • DC – 1) 4A • fOSC • (1 – DC) ( V – 0.27V ) • DC = IN fOSC • 0.5A (2) (3) Figure 6. Boost Converter – The Component Values Given Are Typical Values for a 1MHz, 5V to 12V Boost • Solve equations 1, 2, and 3. • Choose the higher value between LTYP and LMIN for L1. L1 should never exceed LMAX. Step 4: IRIPPLE Step 5: IOUT Step 6: D1 Step 7: COUT, COUT1 The LT3579 can be configured as a Boost converter as in Figure 6. This topology allows for positive output voltages that are higher than the input voltage. An external PMOS (optional) driven by the GATE pin of the LT3579 can achieve input or output disconnect during a FAULT event. A single feedback resistor sets the output voltage. For output voltages higher than 40V, see the Charge Pump topology in the Charge Pump Aided Regulators section. Table 1 is a step-by-step set of equations to calculate component values for the LT3579 when operating as a Boost converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 1. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Output Current IRIPPLE = Inductor Ripple Current RDSON_PMOS = RDSON of External PMOS (set to 0 if not using PMOS) IRIPPLE = ( VIN – 0.27V ) • DC fOSC • L1 ⎞ ⎛ I IOUT = ⎜6 A – RIPPLE ⎟ • (1 – DC) 2⎠ ⎝ VR > VOUT ; IAVG > IOUT COUT =COUT1 = IOUT • DC fOSC • 0.01• VOUT – 0.5•IOUT • RDSON_PMOS ( ) Step 8: CIN CIN = CPWR + C VIN CIN = IRIPPLE 6 A • DC + 8 • fOSC • 0.005 • VIN 40 • fOSC • 0.005 • VIN RFB = RT = VOUT – 1.215V 83.3μA Step 9: RFB Step 10: RT 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Only needed for input or output disconnect. See PMOS Step 11: Selection in the Appendix for information on sizing the PMOS PMOS and the biasing resistor, RGATE. Note: The maximum design target for peak switch current is 6A and is used in this table. The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. 35791f 13 LT3579/LT3579-1 APPLICATIONS INFORMATION SEPIC CONVERTER COMPONENT SELECTION – COUPLED OR UN-COUPLED INDUCTORS VPWR 9V TO 16V L1 6.8μH CPWR 4.7μF SW1 SW2 VIN SHDN 100k CVIN 4.7μF FAULT RT RT 86.6k SYNC GND LT3579 CLKOUT VC SS CSS 0.22μF CF 47pF RC 9.53k CC 2.2nF 3759 F07 Table 2. SEPIC Design Equations PARAMETERS/EQUATIONS Step 1: Inputs Step 2: DC Pick VIN, VOUT, and fOSC to calculate equations below. C1 4.7μF D1 60V, 3A L2 6.8μH RFB 130k VOUT 12V 1.6A (VPWR >9V) 1.9A (VPWR >12V) COUT 10μF 3 DC ≅ VOUT + 0.5V VIN + VOUT + 0.5V – 0.27 V (1) VIN 3.3V TO 5V FB GATE L TYP = LMIN = Step 3: L ( VIN – 0.27V ) • DC fOSC • 1.8 A LMAX ( VIN – 0.27V ) • (2 • DC – 1) 4A • fOSC • (1 – DC) ( V – 0.27V ) • DC = IN fOSC • 0.5A (2) (3) • Solve equations 1, 2, and 3. • Choose the higher value between LTYP and LMIN for L. L should never exceed LMAX. • L = L1 = L2 for coupled inductors. • L = L1⏐⏐L2 for un-coupled inductors. Step 4: IRIPPLE Step 5: IOUT Step 6: D1 Step 7: C1 Figure 7. SEPIC Converter – The Component Values Given Are Typical Values for a 1MHz, 9V–16V to 12V SEPIC Topology Using Coupled Inductors The LT3579 can also be configured as a SEPIC as in Figure 7. This topology allows for positive output voltages that are lower, equal, or higher than the input voltage. Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output due to capacitor C1. This implies that a PMOS controlled by the GATE pin is not required in the power path. Table 2 is a step-by-step set of equations to calculate component values for the LT3579 when operating as a SEPIC converter using coupled inductors. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 2. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Output Current IRIPPLE = Inductor Ripple Current IRIPPLE = ( VIN – 0.27V ) • DC fOSC • L ⎞ ⎛ I IOUT = ⎜6 A – RIPPLE ⎟ • (1 – DC) 2⎠ ⎝ VR > VIN + VOUT ; IAVG > IOUT 4.7μF ( typical) ; VRATING > VIN COUT = IOUT • DC fOSC • 0.005 • VOUT IRIPPLE 8 • fOSC • 0.005 • VIN Step 8: COUT Step 9: CPWR CPWR = Step 10: CVIN C VIN = 6 A • DC 40 • fOSC • 0.005 • VIN VOUT – 1.215V 83.3μA Step 11: RFB RFB = RT = Step 12: RT 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Note: The maximum design target for peak switch current is 6A and is used in this table. The final values for COUT, CPWR, and CVIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. 35791f 14 LT3579/LT3579-1 APPLICATIONS INFORMATION DUAL INDUCTOR INVERTING CONVERTER COMPONENT SELECTION – COUPLED OR UN-COUPLED INDUCTORS VIN 5V L1 3.3μH C1 4.7μF L2 3.3μH D1 30V, 2A SW1 SW2 VIN CIN 22μF SHDN 100k FAULT RT SYNC RT 72k LT3579 CLKOUT VC GND SS CSS 0.22μF CF 27pF FB GATE COUT 10μF 2 RFB 144k VOUT –12V 1.2A Table 3. Dual Inductor Inverting Design Equations PARAMETERS/EQUATIONS Step 1: Inputs Step 2: DC Pick VIN, VOUT, and fOSC to calculate equations below. DC ≅ | VOUT | + 0.5V VIN + | VOUT | +0.5V – 0.27 V (1) L TYP = LMIN = ( VIN – 0.27V ) • DC fOSC • 1.8 A RC 20k CC 1nF 3759 F08 Step 3: L LMAX ( VIN – 0.27V ) • (2 • DC – 1) 4A • fOSC • (1 – DC) ( V – 0.27V ) • DC = IN fOSC • 0.5A (2) (3) • Solve equations 1, 2, and 3. • Choose the higher value between LTYP and LMIN for L. L should never exceed LMAX. • L = L1 = L2 for coupled inductors. • L = L1⏐⏐L2 for un-coupled inductors. Step 4: IRIPPLE Figure 8. Dual Inductor Inverting Converter – The Component Values Given Are Typical Values for a 1.2MHz, 5V to –12V Inverting Topology Using Coupled Inductors Due to its unique FB pin, the LT3579 can work in a Dual Inductor Inverting configuration as in Figure 8. Changing the connections of L2 and the Schottky diode in the SEPIC topology, results in generating negative output voltages. This solution results in very low output voltage ripple due to inductor L2 in series with the output. Output disconnect is inherently built into this topology due to the capacitor C1. Table 3 is a step-by-step set of equations to calculate component values for the LT3579 when operating as a Dual Inductor Inverting converter using coupled inductors. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 3. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Output Current IRIPPLE = Inductor Ripple Current IRIPPLE = ( VIN – 0.27V ) • DC fOSC • L Step 5: IOUT Step 6: D1 Step 7: C1 Step 8: COUT ⎞ ⎛ I IOUT = ⎜6 A – RIPPLE ⎟ • (1 – DC) 2⎠ ⎝ VR > VIN +| VOUT | ; IAVG > IOUT 4.7μF ( typical) ; VRATING > VIN + | VOUT | COUT = IRIPPLE 8 • fOSC • 0.005 • | VOUT | CIN = CPWR + C VIN Step 9: CIN CIN = IRIPPLE 6 A • DC + 8 • fOSC • 0.005 • VIN 40 • fOSC • 0.005 • VIN RFB = | VOUT | + 9mV 83.3μA Step 10: RFB Step 11: RT RT = 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Note: The maximum design target for peak switch current is 6A and is used in this table. The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. 35791f 15 LT3579/LT3579-1 APPLICATIONS INFORMATION LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL INDUCTOR INVERTING TOPOLOGIES General Layout Guidelines • To optimize thermal performance, solder the exposed ground pad of the LT3579 to the ground plane with multiple vias around the pad connecting to additional ground planes. • A ground plane should be used under the switcher circuitry to prevent interplane coupling and overall noise. • High speed switching path (see specific topology below for more information) must be kept as short as possible. • The VC , FB, and RT components should be placed as close to the LT3579 as possible, while being as far away as practically possible from the switch node. The ground for these components should be separated from the switch current path. • Place the bypass capacitor for the VIN pin (CVIN) as close as possible to the LT3579. • Place the bypass capacitor for the inductor (CPWR) as close as possible to the inductor. • Bypass capacitors, CPWR and CVIN, may be combined into a single bypass capacitor, CIN, if the input side of the inductor can be close to the VIN pin of the LT3579. • The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. Boost Topology Specific Layout Guidelines • Keep length of loop (high speed switching path) governing switch, diode D1, output capacitor COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. SEPIC Topology Specific Layout Guidelines • Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, output capacitor COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE GND 1 2 3 4 CIN 5 6 7 – 21 20 19 18 17 16 15 14 13 12 11 D1 M1 B SYNC SHDN CLKOUT A 8 9 10 – VIN + COUT1 COUT VOUT + L1 D2 RGATE 3579 F08 A– RETURN CIN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B– RETURN COUT AND COUT1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT AND COUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. Figure 9. Suggested Component Placement for Boost Topology in FE20 Package 35791f 16 LT3579/LT3579-1 APPLICATIONS INFORMATION Inverting Topology Specific Layout Guidelines • Keep ground return path from the cathode of D1 (to chip) separated from output capacitor COUT’s ground return path (to chip) in order to minimize switching noise coupling into the output. Notice the separate ground return for D1’s cathode in Figure 11. • Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. THERMAL CONSIDERATIONS For the LT3579 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. Power & Thermal Calculations Power dissipation in the LT3579 chip comes from four primary sources: switch I2R loss, NPN base drive loss (AC), NPN base drive loss (DC), and additional VIN pin current. These formulas assume continuous mode operation, so they should not be used for calculating thermal losses or efficiency in discontinuous mode or at light load currents. VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE GND 1 2 3 4 CIN 5 6 7 – 21 20 19 18 17 16 15 14 13 12 11 B SYNC SHDN CLKOUT A 8 9 VIN + 10 – COUT C1 D1 L1 L2 3579 F10 VOUT + A– RETURN CIN AND L2 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2 –MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE. Figure 10. Suggested Component Placement for SEPIC Topology in FE20 Package 35791f 17 LT3579/LT3579-1 APPLICATIONS INFORMATION VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE GND 1 2 3 4 CIN 5 6 7 – 21 20 19 18 17 16 15 14 13 12 11 B SYNC SHDN CLKOUT A 8 9 VIN + 10 C C1 D1 L1 GND COUT –VOUT L2 3579 F11 A– RETURN CIN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD. C– RETURN D1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2 – MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE. Figure 11. Suggested Component Placement for Inverting Topology in FE20 Package. Note Separate Ground Path for D1’s Cathode 35791f 18 LT3579/LT3579-1 APPLICATIONS INFORMATION The following example calculates the power dissipation in the LT3579 for a particular boost application: (VIN = 5V, VOUT = 12V, IOUT = 1.5A, fOSC = 1MHz, VD = 0.5V, VCESAT = 0.185V). To calculate die junction temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: TJ = TA + θJA • PTOTAL Table 4. Boost Power Calculations Example with VIN = 5V, VOUT = 12V, IOUT = 1.5A, fOSC = 1MHz, VD = 0.5V, VCESAT = 0.185V DEFINITION OF VARIABLES DC = Switch Duty Cycle DC = EQUATIONS VOUT – VIN + VD VOUT + VD – VCESAT VOUT • IOUT VIN • η DESIGN EXAMPLE DC = 12V – 5V + 0.5V 12V + 0.5V – .185V 12V • 1.5A 5V • 0.9 VALUE DC = 60.9% where T J =Die Junction Temperature, TA =Ambient Temperature, PTOTAL is the final result from the calculations shown in Table 4, and θJA is the thermal resistance from the silicon junction to the ambient air. IIN = Average Input Current η = Power Conversion Efficiency (typically 90% at high currents) PSW = Switch I2R Loss RSW = Switch Resistance (typically 45mΩ combined SW1 and SW2) PBAC = Base Drive Loss (AC) PBDC = Base Drive Loss (DC) PBDC = PINP = Input Power Loss IIN = IIN = IIN = 4A PSW = DC • IIN2 • RSW PSW = 0.609 • (4A)2 • 45mΩ PSW = 438mW PBAC = 13ns • IIN • VOUT • fOSC VIN • IIN • DC 40 PBAC = 13ns • 4A • 12V • 1MHz PBDC = 5V • 4A • 0.609 40 PBAC = 624mW PBDC = 305mW PINP = 14mA • VIN PINP = 14mA • 5V PINP = 70mW PTOTAL = 1.437W 35791f 19 LT3579/LT3579-1 APPLICATIONS INFORMATION The published (http://www.linear.com/designtools/ packaging/Linear_Technology_Thermal_Resistance_ Table.pdf) θJA value is 38°C/W for the TSSOP Exposed Pad package and 34°C/W for the 4mm × 5mm QFN package. In practice, lower θJA values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the Layout Guidelines section. For instance, a θJA value of ~22°C/W was consistently achieved for both TSSOP and QFN packages of the LT3579 (at VIN = 5V, VOUT = 12V, IOUT = 1.7A, fOSC = 1MHz) when board layout was optimized as per the suggestions in the Layout Guidelines section. Junction Temperature Measurement The duty cycle of the CLKOUT signal on the LT3579 is linearly proportional to die junction temperature, TJ (the CLKOUT duty cycle on the LT3579-1 is fixed at ~50%). To get an accurate reading, measure the duty cycle of the CLKOUT signal and use the following equation to approximate the junction temperature: TJ = DCCLKOUT – 35% 0.3% SWITCHING FREQUENCY There are several considerations in selecting the operating frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 600kHz is desired. Some communications have sensitivity to 1.1MHz and in that case a 1.5MHz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The tradeoff is efficiency, since the switching losses due to NPN base charge (see Thermal Considerations), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency. Oscillator Timing Resistor (RT) The operating frequency of the LT3579 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: fOSC = 87.6 RT + 1 where DCCLKOUT is the CLKOUT duty cycle in % and TJ is the die junction temperature in °C. Although the absolute die temperature can deviate from the above equation by ±15°C, the relationship between change in CLKOUT duty cycle and change in die temperature is well defined. A 3% increase in CLKOUT duty cycle corresponds to ~10°C increase in die temperature: Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF. Thermal Lockout A fault condition occurs when the die temperature exceeds ~165°C (see Operation – FAULT Section), and the part goes into thermal lockout. The fault condition ceases when the die temperature drops by ~5°C (nominal). where fOSC is in MHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in MHz) using: RT = 87.6 –1 fOSC 35791f 20 LT3579/LT3579-1 APPLICATIONS INFORMATION Clock Synchronization An external source can set the operating frequency of the LT3579 by providing a digital clock signal into the SYNC pin (RT resistor still required). The LT3579 will operate at the SYNC clock frequency. The LT3579 will revert to its internal free-running oscillator clock when the SYNC pin is driven below 0.4V for a few free-running clock periods. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT3579 will stop and the CLKOUT pin will be held at ground. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 200kHz-2.5MHz unless it is stopped below 0.4V to enable the free-running oscillator. The SYNC frequency can always be higher than the free-running oscillator frequency (as set by the RT resistor), fOSC , but should not be less than 25% below fOSC. 4.7μF 10μF GATE VIN 4.7μF 3.3μH VOUT 18V 1A SW1 SW2 CLKOUT LT3579 SLAVE FB VC SS GND 0.1μF 68pF 8k 3.3nF 200k 10μF 2 FAULT SHDN RT SYNC 86.6k VIN 5V 10k 2.2μH 10μF SW1 SW2 CLKOUT LT3579 VIN FB MASTER VC FAULT SS SHDN RT SYNC GND 0.1μF 86.6k 3579 F12 VOUT 12V 1.7A 130k 10μF 3 GATE 100k 110k 47pF 8k 2.2nF 2. Figure 12. Synchronize Multiple LT3579s. The External PMOS Disconnects the Input from Both Power Paths During FAULT Events CLOCK SYNCHRONIZATION OF ADDITIONAL REGULATORS The CLKOUT pin of the LT3579 can synchronize additional switching regulators and/or additional LT3579s as shown in Figure 12. The frequency of the master LT3579 is set by the external RT resistor. The SYNC pin of the slave LT3579 is driven by the CLKOUT pin of the master LT3579. Note that the RT pin of the slave LT3579 must have a resistor tied to ground. It takes a few clock cycles for the CLKOUT signal to begin oscillating, and it’s preferable for all LT3579s to have the same internal free-running frequency. Therefore, in general, use the same value RT resistor for all of the synchronized LT3579s. Also, the FAULT pins can be tied together so that a fault condition from one LT3579 causes all of the LT3579s to enter fault, until the fault condition disappears. 2-Phase Converters using LT3579-1 The CLKOUT pin on the LT3579-1 is ~180° out of phase with the internal oscillator, which allows two LT3579-1s to operate in parallel for a high current, high power output. The advantage of multiphase converters is that the ripple current flowing into the output node is divided by the number of phases or ICs used to generate the output voltage. The VIN, SHDN, FAULT, FB, and VC pins of all the LT3579-1s should be connected together. Figure 13 shows a typical application of a 2-phase 12V to 24V boost with output disconnect. 35791f 21 LT3579/LT3579-1 APPLICATIONS INFORMATION Use the following equations to calculate the FB resistor for 2-phase converters: ⎛V – 1.215V ⎞ RFB = ⎜ OUT ⎟ ; Boost or SEPIC ⎝ 2 • 83.3μA ⎠ Multiphase Converter ⎛ | V | + 9mV ⎞ RFB = ⎜ OUT ⎟ ; Inverting Multiphase ⎝ 2 • 83.3μA ⎠ Converter Note that the CLKOUT pin on the LT3579-1 runs at a fixed duty cycle of ~50%. If monitoring the die temperature is desired, the slave IC can be a LT3579. It is possible to use the LT3579-1 in a multiphase converter of more than 2 phases. Consult the LTC Applications Engineering Department for more information. CHARGE PUMP AIDED REGULATORS Designing charge pumps with the LT3579 can offer efficient solutions with fewer components than traditional circuits because of the master/slave switch configuration on the IC. The current in the master switch (SW1) is sensed by the current comparator (A4 in Block Diagram), but the current in the slave switch (SW2) is not. Note that the slave switch, SW2, operates in phase with SW1. This method of operation by the master/slave switches can offer the following benefits to charge pump designs: • The slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes when the flying capacitors charge up. Since this current spike flows through SW2, it does not affect the operation of the current comparator (A4 in Block Diagram). • The master switch, immune from the capacitor current spike, can sense the inductor current more accurately. • Since the slave switch can sustain large current spikes, the diodes that feed current into the flying capacitors do not need current limiting resistors, leading to efficiency and thermal improvements. 4.7μF 5k 4.7μH 10μF SW1 SW2 VIN CLKOUT FB FAULT LT3579-1 SLAVE GATE SHDN VC RT SYNC GND 86.6k SS 0.22μF VOUT1 4.7μH 10μF 4.7μF 2 VIN SW1 SW2 CLKOUT 137k VOUT 24V 3.7A, 89W 4.7μF 2 4.7μF 2 4.7μF VPWR 12V 6.4k VIN 5V VOUT1 500k 100k 21.5k FB FAULT LT3579-1 MASTER GATE SHDN VC RT SYNC GND 86.6k SS 0.22μF VPWR 47pF 7k 2.2nF 3579 F13 Figure 13. 2-Phase Converters Using LT3579-1 High VOUT Charge Pump Topology The LT3579 can be used in a charge-pump topology (refer to Figure 16), multiplying the output of an inductive boost converter. The master switch (SW1) can be used to drive the inductive boost converter, while the slave switch (SW2) can be used to drive one or more charge pump stages. This topology is useful for high voltage applications including VFD Bias Supplies. Single Inductor Inverting Topology If there is a need to use just 1 inductor to generate a negative output voltage whose magnitude is greater than VIN , the Single Inductor Inverting topology (shown in Figure 15) can be used. Since the master and slave switches are isolated by an external Schottky diode, the current spike through C1 will flow through the slave switch, thereby preventing the current comparator (A4 in Block Diagram) from falsely tripping. Output disconnect is inherently built into the single inductor topology. 35791f 22 LT3579/LT3579-1 APPLICATIONS INFORMATION HOT PLUG The high inrush current associated with hot-plugging VIN can be largely rejected with the use of an external PMOS. A simple hot-plug controller can be designed by connecting an external PMOS in series with VIN, with the gate of the PMOS being driven by the GATE pin of the LT3579. Since the GATE pin pull-down current is linearly proportional to the SS voltage, and the SS charge up time is relatively slow, the GATE pin pull-down current will increase gradually, thereby turning on the external PMOS slowly. Controlled in this manner, the PMOS acts as an input current limiter when VIN hot-plugs or ramps up sharply. Likewise, when the PMOS is connected in series with the output, inrush currents into the output capacitor can be limited during a hot-plug event. To illustrate this, the circuit in Figure 6 was re-configured by adding a large 1500μF capacitor to the output. An 18Ω resistive load was used and a 2.2μF capacitor was placed on SS. Figure 14 shows the result of hot-plugging this re-configured circuit. The inductor current is well behaved and VOUT comes up once VIN settles out. VIN 5V/DIV 100k VOUT 10V/DIV IL 5A/DIV SS 1V/DIV 3579 F14 L1 VIN D1 C1 D2 D3 –VOUT RFB SW1 VIN SHDN 100k FAULT CIN RT SW2 FB GATE COUT LT3579 CLKOUT VC SS CSS CF RC CC 3579 F15 SYNC GND RT Figure 15. Single Inductor Inverting Topology VOUT2 100V 200mA VOUT1 67V 100mA 4.7μF 4.7μF 4.7μF 4.7μF VIN 12V 10μH 6.8μF SW1 SW2 VIN FAULT LT3579 536k 10μF SHDN RT SYNC 86.6k CLKOUT VC GND SS 2.2μF 27pF 34k 470pF 3579 F16 383k FB GATE 6.5k 6.8μF VIN 1s/DIV Figure 14. VIN Hot-Plug Control. Inrush Current is Well Controlled Figure 16. High VOUT Charge Pump Topology 35791f 23 LT3579/LT3579-1 APPENDIX SETTING THE OUTPUT VOLTAGE The output voltage is set by connecting a resistor (RFB) from VOUT to the FB pin. RFB is determined from the following equation: |V – VFB | RFB = OUT 83.3μA where VFB is 1.215V (typical) for non-inverting topologies (i.e. boost and SEPIC regulators) and 9mV (typical) for inverting topologies (see Electrical Characteristics). POWER SWITCH DUTY CYCLE In order to maintain loop stability and deliver adequate current to the load, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “on” for 100% of each clock cycle. The maximum allowable duty cycle is given by: DCMAX = For the boost topology (see Figure 6): DCBOOST ≅ VOUT – VIN + VD VOUT + VD – VCESAT For the SEPIC or Dual Inductor Inverting topology (see Figures 7 and 8): DCSEPIC _&_ INVERT ≅ VD + | VOUT | VIN + | VD | + VOUT − VCESAT For the Single Inductor Inverting topology (see Figure 14): DCSI _ INVERT ≅ | VOUT | −VIN + VCESAT + 3 • VD | VOUT | + 3 • VD The LT3579 can be used in configurations where the duty cycle is higher than DCMAX , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. INDUCTOR SELECTION The high frequency operation of the LT3579 allows for the use of small surface mount inductors. For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper-wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor only carries one half of the total switch current. Multilayer chokes or chip inductors usually do not have enough core volume to support peak inductor currents in the 4A to 7A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 5 for a list of inductor manufacturers. (TP – MinOffTime) • 100% TP where TP is the clock period and MinOffTime (found in the Electrical Characteristics) is typically 45nS. Conversely, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “off” for 100% of each clock cycle, and will turn on for a minimum time (MinOnTime) when in regulation. This MinOnTime governs the minimum allowable duty cycle given by: DCMIN = (MinOnTime) • 100% TP where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is typically 55nS. The application should be designed such that the operating duty cycle is between DCMIN and DCMAX. Duty cycle equations for several common topologies are given below where VD is the diode forward voltage drop and VCESAT is typically 250mV at 5.5A for a combined SW1 and SW2 current. 35791f 24 LT3579/LT3579-1 APPENDIX Table 5. Inductor Manufacturers Vishay Coilcraft IHLP-2020BZ-01 and IHLP-2525CZ-01 Series XLP MLC and MSS Series , www.vishay.com www.coilcraft.com www.cooperbussmann. com www.sumida.com www.tdk.com www.we-online.com where: LBOOST = L1 for Boost Topologies (see Figure 6) LDUAL = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 7 and 8) LDUAL = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 7 and 8) DC = Switch Duty Cycle (see Power Switch Duty Cycle section in Appendix) = Maximum Peak Switch Current; Should IPK Not Exceed 6A for a Combined SW1 + SW2 Current or 3.4A of SW1 Current (see Electrical Characteristics section.) η = Power Conversion Efficiency (typically 90% for Boost and 85% for Dual Inductor Topologies at high currents) fOSC = Switching Frequency IOUT = Maximum Output Current Negative values of LBOOST or LDUAL indicate that the output load current, IOUT, exceeds the switch current limit capability of the LT3579. Avoiding Sub-Harmonic Oscillations The LT3579’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LMIN = where: LMIN LMIN LMIN = L1 for Boost Topologies (see Figure 6) = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 7 and 8) = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 7 and 8) Cooper Bussmann DRQ125 and DRQ127 Series Sumida TDK Würth CDRH series RLF and SLF series WE-PD, WE-PDF WE-HC , and WE-DD Series Minimum Inductance Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are three conditions that limit the minimum inductance; (1) providing adequate load current, (2) avoidance of subharmonic oscillation, and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. Adequate Load Current Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least: LBOOST > DC • VIN − VCESAT ⎛ 2 • fOSC • ⎜ IPK ⎝ or LDUAL > DC • VIN − VCESAT ( Boost VOUT • IOUT ⎞ Topology − ⎟ VIN • η ⎠ ) ( ) ⎛ |V | •I 2 • fOSC • ⎜ IPK − OUT OUT VIN • η ⎝ SEPIC or ⎞ Inverting − IOUT ⎟ Topologies ⎠ ( VIN − VCESAT ) • (2 • DC − 1) 4A • fOSC • (1− DC) 35791f 25 LT3579/LT3579-1 APPENDIX Maximum Inductance Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A4 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX = where: LMAX LMAX LMAX = L1 for Boost Topologies (see Figure 6) = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 7 and 8) = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 7 and 8) DIODE SELECTION Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT3579. Choose a Schottky with low parasitic capacitance to reduce reverse current spikes through the power switch of the LT3579. The Diodes Inc. MBRM360 is a very good choice with a 60V reverse voltage rating and an average forward current of 3A. OUTPUT CAPACITOR SELECTION Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small packages. X5R or X7R type are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. A 22μF to 47μF output capacitor is sufficient for most applications, but systems with low output currents may need only 4.7μF to 22μF. Always use a capacitor with a sufficient voltage rating. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. Tantalum polymer or OS-CON capacitors can be used, but it is likely that these capacitors will occupy more board area than a ceramic, and will have higher ESR with greater output ripple. INPUT CAPACITOR SELECTION Ceramic capacitors make a good choice for the input decoupling capacitor, CVIN, which should be placed as close as possible to the VIN pin of the LT3579. This ensures that the voltage seen at the VIN pin of the LT3579 remains a nearly flat DC voltage. A 1μF to 4.7μF input capacitor is sufficient for most applications. A ceramic bypass capacitor, CPWR, should also be placed as close as possible to the input of the inductor. This ensures that the inductor ripple current is supplied from the bypass capacitor and provides a nearly flat DC voltage to the input of the voltage converter. A 4.7μF to 10μF input power capacitor is sufficient for most applications. ( VIN − VCESAT ) • DC fOSC • 0.5A Inductor Current Rating The inductor(s) must have a rating greater than its (their) peak operating current to prevent inductor saturation, which would result in catastrophic failure and efficiency losses. The maximum inductor current (considering start-up and steady-state conditions) is given by: V •T IL _ PEAK = ILIM + IN MIN _ PROP L where: = Peak Inductor Current in L1 for a Boost Topology, or the sum of the Peak Inductor Currents in L1 and L2 for Dual Inductor Topologies. = For Hard-Saturation Inductors, 9.4A with ILIM SW1 and SW2 Tied Together, or 5.1A with just SW1 used. For Soft-Saturation Inductors, 6A with SW1 and SW2 Tied Together, or 3.4A with just SW1 used. TMIN_PROP = 100ns (Propagation Delay through the Current Feedback Loop). IL_PEAK Note that these equations offer conservative results for the required inductor current ratings. The current ratings could be lower for applications with light loads, provided the SS capacitor is sized appropriately to limit inductor currents at start-up. 35791f 26 LT3579/LT3579-1 APPENDIX Table 6 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts. Table 6. Ceramic Capacitor Manufacturers TDK Murata Taiyo Yuden www.tdk.com www.murata.com www.t-yuden.com the relationship between RGATE (see Block Diagram) and the desired VSG that the PMOS is biased with: ⎧ RGATE < 2V if V ⎪ VS VSG = ⎨ RGATE + 2kΩ GATE ⎪ ⎩ 933μA • RGATE if VGATE > 2V When using a PMOS, it is advisable to configure the specific application for undervoltage lockout (see the Operations section). The goal is to have VIN get to a certain minimum voltage where the PMOS has sufficient headroom to attain a high enough VSG, which prevents it from entering the saturation mode of operation during start-up. Figure 6 shows the PMOS connected in series with the output to act as an output disconnect during a fault condition. The Schottky diode from the VIN pin to the GATE pin is optional and helps turn off the PMOS quicker in the event of hard shorts. The resistor from VIN to the SHDN pin sets a UVLO of 4V for this application. Connecting the PMOS in series with the output offers certain advantages over connecting it in series with the input: • Since the load current is always less than the input current for a boost converter, the current rating of the PMOS goes down when connected in series with the output as opposed to the input. • A PMOS in series with the output can be biased with a higher overdrive voltage than a PMOS used in series with the input, since VOUT > VIN. This higher overdrive results in a lower RDSON for the PMOS, thereby improving the efficiency of the regulator. In contrast, an input connected PMOS works as a simple hot-plug controller (covered in more detail in the Hot-Plug section). The input connected PMOS also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the LT3579 with other compatible ICs (see Figure 12). PMOS SELECTION An external PMOS, controlled by the LT3579’s GATE pin, can be used to facilitate input or output disconnect. The GATE pin turns on the PMOS gradually during start-up (see Soft-Start of External PMOS in the Operation section), and turns the PMOS off when the LT3579 is in shutdown or in fault. The use of the external PMOS, controlled by the GATE pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. In a conventional boost regulator, the inductor, Schottky diode, and power switches are susceptible to damage in the event of an output short to ground. Using an external PMOS in the boost regulator’s power path (path from VIN to VOUT) controlled by the GATE pin, will serve to disconnect the input from the output when the output has a short to ground, thereby helping save the IC, and the other components in the power path from damage. The PMOS chosen must be capable of handling the maximum input or output current depending on whether the PMOS is used at the input (see Figure 12) or the output (see Figure 13). Ensure that the PMOS is biased with enough source to gate voltage (VSG) to enhance the device into the triode mode of operation. The higher the VSG voltage that biases the PMOS, the lower the RDSON of the PMOS, thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application in which the PMOS is used. The following equations show 35791f 27 LT3579/LT3579-1 APPENDIX Table 7 shows a list of several discrete PMOS manufacturers. Consult the manufacturers for detailed information on their entire selection of PMOS devices. Table 7. Discrete PMOS Manufacturers Vishay Fairchild Semiconductor Central Semiconductor www.vishay.com www.fairchildsemi.com www.centralsemi.com ILOAD 1A/DIV RC = 1k 100μs/DIV 3579 F17a VOUT 500mV/DIV AC COUPLED IL 2A/DIV COMPENSATION – ADJUSTMENT To compensate the feedback loop of the LT3579, a series resistor-capacitor network in parallel with an optional single capacitor must be connected from the VC pin to GND. For most applications, choose a series capacitor in the range of 1nF to 10nF with 2.2nF being a good starting value. The optional parallel capacitor should range in value from 22pF to 180pF with 47pF being a good starting value. The compensation resistor, RC , is usually in the range of 5k to 50k. A good technique to compensate a new application is to use a 100kΩ potentiometer in place of the series resistor RC. With the series and parallel capacitors at 2.2nF and 47pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC can be found. Figures 17a to 17c illustrate this process for the circuit of Figure 20 with a load current stepped between 0.7A and 1.5A. Figure 17a shows the transient response with RC equal to 1k. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 17b, the value of RC is increased to 3.5k, which results in a more damped response. Figure 17c shows the results when RC is increased further to 8k. The transient response is nicely damped and the compensation procedure is complete. COMPENSATION – THEORY Like all other current mode switching regulators, the LT3579 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT3579: a fast current loop which does not require compensation, and a slower voltage loop which does. Standard Bode plot analysis can be used to understand and adjust the voltage Figure 17a. Transient Response Shows Excessive Ringing VOUT 500mV/DIV AC COUPLED IL 2A/DIV ILOAD 1A/DIV RC = 3.5k 100μs/DIV 3579 F17b Figure 17b. Transient Response Is Better VOUT 500mV/DIV AC COUPLED IL 2A/DIV ILOAD 1A/DIV RC = 8k 100μs/DIV 3579 F17c Figure 17c. Transient Response Is Well Damped 35791f 28 LT3579/LT3579-1 APPENDIX feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 18 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier gmp and the current controlled current source (which converts IVIN to ηVIN I ). Gmp acts as a current VOUT VIN are finite. The output of the gmp stage is limited by the minimum switch current limit (see Electrical Specifications) and gma is nominally limited to about ±12μA. From Figure 18, the DC gain, poles and zeros can be calculated as follows: DC Gain: V R 0.5R2 ADC = gma •RO • gmp • η• IN • L • VOUT 2 R1 + 0.5R2 Output Pole : P1 = 2 2• π •RL •COUT 1 2• π • (RO + RC ) •CC 1 2• π •RC •CC 1 2• π •RESR •COUT VIN2 •RL 2• π • VOUT2 •L fS 3 CF RC CC RO Figure 18. Boost Converter Equivalent Model source where the peak input current, IVIN, is proportional to the VC voltage. Note that the maximum output currents of gmp and gma + + gma – gmp IVIN VOUT • VIN Error Amp Pole : P2 = RL VOUT • IVIN RESR COUT Error Amp Zero : Z1 = ESR Zero : Z2 = 1.215V REFERENCE R2 CPL R1 – R2 FB RHP Zero : Z3 = 3579 F18 CC: COMPENSATION CAPACITOR COUT: OUTPUT CAPACITOR CPL: PHASE LEAD CAPACITOR CF: HIGH FREQUENCY FILTER CAPACITOR gma: TRANSCONDUCTOR AMPLIFIER INSIDE IC gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER RC: COMPENSATION RESISTOR RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOADMAX RO: OUTPUT RESISTANCE OF gma R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK RESR: OUTPUT CAPACITOR ESR : CONVERTER EFFICIENCY (~90% AT HIGHER CURRENTS) High Frequency Pole : P3 > Phase Lead Zero : Z 4 = Phase Lead Pole : P4 = 1 2• π •R1•CPL 1 R • 0.5R2 2• π • 1 •C R1 + 0.5R2 PL CC 10 Error Amp Filter Pole : P5 = 2• π • 1 RC •RO C RC + RO F , CF < 35791f 29 LT3579/LT3579-1 APPENDIX 140 120 PHASE 100 0 –45 –90 –135 –180 GAIN 46° AT 8kHz –225 –270 –315 10 100 1k 10k 100k FREQUENCY (Hz) –360 1M 3060 TA02 The current mode zero (Z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. Using the circuit in Figure 20 as an example, Table 8 shows the parameters used to generate the Bode plot shown in Figure 19. Table 8. Bode Plot Parameters PARAMETER RL COUT RESR R0 CC CF CPL RC R1 R2 VOUT VIN gma gmp L fOSC VALUE 7 30 2 305 2200 47 0 8 130 14.6 12 5 250 28 2.2 1.0 UNITS Ω μF mΩ kΩ pF pF pF kΩ kΩ kΩ V V μmho mho μH MHz COMMENT Application Specific Application Specific Application Specific Not Adjustable Adjustable Optional/Adjustable Optional/Adjustable Adjustable Adjustable Not Adjustable Application Specific Application Specific Not Adjustable Not Adjustable Application Specific Adjustable VIN 5V PHASE (DEG) GAIN (dB) 80 60 40 20 0 –20 Figure 19. Bode Plot for Example Boost Converter L1 2.2μH D1 VOUT 12V 1.7A 130k SW1 SW2 VIN 100k CIN 22μF FAULT SHDN RT SYNC GND 86.6k LT3579 GATE CLKOUT VC SS 0.1μF FB COUT 10μF 3 47pF 8k 2.2nF 3579 F20 Figure 20. 5V to 12V Boost Converter From Figure 19, the phase is –134° when the gain reaches 0dB giving a phase margin of 46°. The crossover frequency 35791f 30 LT3579/LT3579-1 TYPICAL APPLICATION 1MHz, 5V to 12V Boost Converter can Survive Output Shorts L1 2.2μH D1 COUT1 10μF SW1 SW2 100k 200k CIN 22μF 86.6k VIN FAULT LT3579 SHDN RT SYNC CLKOUT VC GND SS 0.1μF 47pF 8k 2.2nF 3579 TA03a VIN 5V M1 VOUT 12V 1.7A COUT 10μF D2 VIN 130k FB GATE 6.3k , CIN: 22μF 16V, X7R, 1210 COUT1, COUT: 10μF, 25V, X7R, 1210 D1: VISHAY SSB43L D2: CENTRAL SEMI CMDSH-3TR L1: WÜRTH WE-PD 744771002 M1: SILICONIX SI7123DN Efficiency and Power Loss 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0 0.25 0.5 0.75 1 1.25 1.5 1.75 LOAD CURRENT (A) 2 3.2 2.8 2.4 POWER LOSS (W) 2 1.6 1.2 0.8 0.4 0 3579 TA03 Output Short VOUT 10V/DIV CLKOUT 2V/DIV Transient Response with 0.7A to 1.5A to 0.7A Output Load Step VOUT 500mV/DIV AC COUPLED IL 2A/DIV IL 2A/DIV FAULT 5V/DIV 10μs/DIV 3579 TA05 ILOAD 1A/DIV 100μs/DIV 3579 TA06 35791f 31 LT3579/LT3579-1 TYPICAL APPLICATION 500kHz SEPIC Converter Generates 3.3V from a 3V to 33V Input D3 L1 3.3μH CPWR 4.7μF 2 200k M1 C1 10nF D1 15V 100k CVIN 10μF 174k Q1 0.22μF C1: 10nF 16V, X7R, 0603 , CVIN: 10μF 16V, X7R, 1206 , CPWR, C2: 4.7μF 50V, X7R, 1210 , COUT: 47μF 6.3V, X7R, 1210 , D1: CENTRAL SEMI CMHZ5245B-LTZ D2: VISHAY SS5P6 D3: CENTRAL SEMI CMMSH2-40 D4: CENTRAL SEMI CMMSH2-40 L1, L2: WÜRTH WE-DD 744870003 M1: 2N7002 Q1: MMBT3904 4.7nF 3579 TA07a VBAT 3V TO 33V (OPERATING) 6V TO 16V (START-UP) • C2 4.7μF D4 D2 L2 3.3μH 10k 4.7nF SW1 SW2 VOUT 3.3V 1.8A (VBAT = 3V) 3.1A (VBAT = 9V) 3.4A (VBAT ≥ 12V) • 24.9k COUT 47μF 6 VIN SHDN LT3579 FAULT FB GATE VC 10k RT CLKOUT SYNC GND SS 100pF 8.25k Efficiency and Power Loss 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.5 1 1.5 2 2.5 3 LOAD CURRENT (A) 3.5 4 VBAT = 3V VBAT = 12V 2 1.5 1 0.5 0 4 3.5 3 POWER LOSS (W) 2.5 Transient Response with 9V to 33V to 9V VBAT Glitch (RLOAD = 1.5Ω) VOUT 2V/DIV VBAT 10V/DIV IL1 + IL2 1A/DIV 50ms/DIV 3579 TA08b 3579 TA08a 35791f 32 LT3579/LT3579-1 TYPICAL APPLICATION 1.2MHz, 5V to -12V Inverting Converter L1 3.3μH C1 4.7μF L2 3.3μH D1 SW1 SW2 VIN SHDN 100k CIN 22μF FAULT RT SYNC GND 71.5k LT3579 CLKOUT VC SS 0.22μF FB GATE COUT 10μF 2 143k VIN 5V VOUT –12V 1.2A 27pF 20k 1nF 3579 TA14 CIN: 22μF 16V, X7R, 1210 , C1: 4.7μF 25V, X7R, 1206 , , COUT: 10μF 25V, X7R, 1210 D1: DIODES INC B230A L1, L2: COOPER BUSSMANN DRQ125-3R3-R Efficiency and Power Loss 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0 0.25 0.5 0.75 LOAD CURRENT (A) 1 3.2 2.8 2.4 POWER LOSS (W) 2 1.6 1.2 0.8 0.4 0 1.25 3579 TA15 Transient Response with 0.5A to 1A to 0.5A Output Load Step VOUT 500mV/DIV AC COUPLED IL1 + IL2 1A/DIV ILOAD 1A/DIV 3579 TA16 100μs/DIV 35791f 33 LT3579/LT3579-1 TYPICAL APPLICATION VFD (Vacuum Flourescent Display) Power Supply Switches at 1MHz Danger High Voltage! Operation by High Voltage Trained Personnel Only D6 D5 C4 2.2μF 2 D4 C5 2.2μF 2 C6 2.2μF 2 VOUT2 100V 330mA* VOUT1 67V 500mA* D3 C3 2.2μF 2 D2 VIN 9V TO 16V L1 10μH D1 D9** C1 2.2μF 3 383k FB GATE LT3579 536k CIN 10μF 86.6k SHDN RT SYNC CLKOUT VC GND SS 2.2μF 27pF 34k 470pF 3579 TA17 M1** D8** 8.2V 6.5k** D7** VIN SW1 SW2 100k VIN FAULT C2 2.2μF 3 CIN: 10μF 25V, X7R, 1210 , C1-C6: 2.2μF 50V, X7R, 1210 , D1-D6: DIODES INC SBR2A40P1 D7: CENTRAL SEMI CMDSH-3TR D8: CENTRAL SEMI CMDZ5237B-LTZ D9: DIODES INC MBRM360 L1: WÜRTH WE-PD 7447710 M1: SILICONIX SI7461DP *MAX TOTAL OUTPUT POWER 22W (VIN = 9V) 27W (VIN = 12V) 33W (VIN = 16V) **OPTIONAL FOR OUTPUT SHORT CIRCUIT PROTECTION Efficiency and Power Loss (VIN = 12V) 90 5 VOUT1 2V/DIV AC COUPLED VOUT2 2V/DIV AC COUPLED IL 1A/DIV SW1 20V/DIV Cycle-to-Cycle 85 EFFICIENCY (%) 4 POWER LOSS (W) 80 3 75 2 70 1 1μs/DIV 3579 TA19 65 0 5 15 10 20 25 TOTAL OUTPUT POWER (W) 0 30 3579 TA18 35791f 34 LT3579/LT3579-1 TYPICAL APPLICATION 1MHz, 5V to ±12V Converter C2 4.7μF D4 L1 4.7μH D1 C1 4.7μF D3 D2 SW1 VIN SHDN LT3579 100k FAULT CIN 10μF RT SYNC 86.6k CLKOUT VC GND SS 0.1μF 27pF 34k 1nF 3579 TA20 D5 R1** 1.2k VIN 5V VOUT 2 –12V COUT 2 0.8A* 10μF 2 VOUT1 12V 0.8A* COUT1 10μF 2 SW2 FB GATE 130k , CIN: 10μF 16V, X7R, 1206 C1, C2: 4.7μF 25V, X7R, 1206 , , COUT1, COUT2: 10μF 25V, X7R, 1210 D1-D5: DIODES INC SBR2A40P1 L1: VISHAY IHLP-2525CZ-01-4R7 R1: 1.2k, 2W *MAX TOTAL OUTPUT POWER = 9.6W **IF DRIVING ASYMMETRICAL LOADS, PLACE A 1.2k, 2W RESISTOR FROM THE +12V OUTPUT TO THE –12V OUTPUT FOR IMPROVED LOAD REGULATION OF THE –12V OUTPUT. Efficiency and Power Loss 90 85 80 EFFICIENCY (%) 75 70 65 60 55 50 45 40 0 100 300 200 400 LOAD CURRENT (mA) 3 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 500 3579 TA21 Transient Response with 0.15A to 0.35A to 0.15A Symmetrical Output Load Step VOUT1 500mV/DIV AC COUPLED POWER LOSS (W) VOUT2 500mV/DIV AC COUPLED IL 1A/DIV 100μs/DIV 3579 TA22 35791f 35 LT3579/LT3579-1 TYPICAL APPLICATION 1MHz, 2-Phase Converter Generates a 24V Output from a 8V to 16V Input and Uses Small Components L2 4.7μH CPWR2 10μF SW1 SW2 VIN CLKOUT FB FAULT LT3579-1 SLAVE GATE SHDN VC RT SYNC GND 86.6k SS 0.22μF VOUT1 L1 4.7μH CPWR1 10μF VIN 3.3V TO VPWR VIN SW1 SW2 CLKOUT D1 6.4k** COUT1M 4.7μF 2 137k D3** VPWR COUT 4.7μF 2 M1** VOUT 24V 5.1A* D2 COUT1S 4.7μF 2 CVIN2 4.7μF VPWR 8V TO 16V VOUT1 500k 21.5k 100k FB FAULT LT3579-1 MASTER GATE SHDN VC RT SYNC GND SS 0.22μF CVIN1 4.7μF 5k 47pF 7k 2.2nF 3579 F23 86.6k , CPWR1, CPWR2: 10μF 25V, X7R, 1210 CVIN1, CVIN2: 4.7μF 25V, X7R, 1206 , COUT1M, COUT1S, COUT: 4.7μF 50V, X5R, 1210 , D1, D2: CENTRAL SEMI CTLSH5-40M833 D3: CENTRAL SEMI CTLSH1-40M563 L1, L2: VISHAY IHLP-2525CZ-01-4R7 M1: SILICONIX SI7461DP *MAX OUTPUT CURRENT VPWR = 8V VIN = 3.3V TO 5V VIN = VPWR 2.4A 2.2A VPWR = 12V 3.7A 3.1A VPWR = 16V 5.1A 3.9A **OPTIONAL FOR OUTPUT SHORT CIRCUIT PROTECTION Efficiency and Power Loss (VPWR = 12V) 100 90 80 EFFICIENCY (%) 70 60 VIN = 3.3V 50 40 30 20 0 0.5 1 1.5 2 2.5 3 3.5 LOAD CURRENT (A) 4 3 2 1 VIN = 12V 8 7 6 POWER LOSS (W) 5 4 Transient Response with 1.5A to 3.25A to 1.5A Output Load Step (VPWR = 12V and VIN = 3.3V) VOUT 1V/DIV AC COUPLED IL1 + IL2 5A/DIV ILOAD 1A/DIV 3579 TA25 100μs/DIV 0 4.5 3579 TA24 35791f 36 LT3579/LT3579-1 TYPICAL APPLICATION 2MHz, Boost Converter with Output Disconnect Generates a 5V Output from 2.8V to 4.2V Input VIN 2.8V TO 4.2V L1 0.47μH D1 COUT1 22μF SW1 SW2 VIN SHDN 100k CIN 10μF 43.2k LT3579 CLKOUT FAULT VC RT SYNC GND SS 22nF FB GATE COUT 22μF 47pF 6.34k 2.2nF 3579 TA26 M1 VOUT 5V 2A 43.5k 10k , CIN: 10μF 16V, X7R, 1206 COUT1, COUT: 22μF 16V, X7R, 1210 , D1: CENTRAL SEMI CTLSH3-30M833 L1: VISHAY IHLP-2020BZ-01-R47 M1: SILICONIX SI7123DN Efficiency and Power Loss 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0 0.5 1 1.5 LOAD CURRENT (A) 2 VIN = 3.3V 2.4 2.1 1.8 POWER LOSS (W) 1.5 1.2 0.9 0.6 0.3 0 2.5 3579 TA27 Transient Response with 0.8A to 1.8A to 0.8A Output Load Step (VIN = 3.3V) VOUT 200mV/DIV AC COUPLED IL 1A/DIV ILOAD 1A/DIV 100μs/DIV 3579 TA28 35791f 37 LT3579/LT3579-1 PACKAGE DESCRIPTION FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CB 3.86 (.152) 6.40 – 6.60* (.252 – .260) 3.86 (.152) 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 4.50 ±0.10 SEE NOTE 4 2.74 (.108) 0.45 ±0.05 1.05 ±0.10 0.65 BSC 6.40 2.74 (.252) (.108) BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX 0° – 8° 4.30 – 4.50* (.169 – .177) 0.25 REF 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 35791f 38 LT3579/LT3579-1 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 ±0.05 4.50 ± 0.05 1.50 REF 3.10 ± 0.05 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 ± 0.05 R = 0.05 TYP 1.50 REF 19 20 0.40 ± 0.10 PIN 1 NOTCH R = 0.20 OR C = 0.35 1 2 5.00 ± 0.10 (2 SIDES) 2.50 REF 3.65 ± 0.10 2.65 ± 0.10 (UFD20) QFN 0506 REV B 0.200 REF 0.00 – 0.05 R = 0.115 TYP 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 35791f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 39 LT3579/LT3579-1 TYPICAL APPLICATION 1MHz SEPIC Converter Generates a 12V Output from a 9V to 16V Input 100 L1 6.8μH C1 4.7μF D1 90 VOUT 12V 1.9A* 130k 80 EFFICIENCY (%) 70 60 50 40 30 20 47pF 9.53k 2.2nF 3579 TA29 Efficiency and Power Loss 3.2 2.8 2.4 POWER LOSS (W) 2 VPWR = 12V VIN = 5V 1.6 1.2 0.8 0.4 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 LOAD CURRENT (A) 2 VPWR 9V TO 16V • CPWR 4.7μF L2 6.8μH SW1 VIN SHDN LT3579 CLKOUT FAULT RT VC SYNC GND SS SW2 FB GATE • COUT 10μF 3 VIN 3.3V TO VPWR 100k CVIN 4.7μF 86.6k 0.22μF 3579 TA08 *MAX OUTPUT CURRENT CPWR: 4.7μF 25V, X7R, 1206 , CVIN: 4.7μF 25V, X7R, 1206 , VPWR = 9V VPWR = 12V C1: 4.7μF 25V, X7R, 1206 , , COUT: 10μF 25V, X7R, 1210 1.6A 1.9A VIN = 3.3V TO 5V D1: DIODES INC MBRM360 1.4A 1.4A VIN = VPWR L1, L2: COOPER BUSSMANN DRQ125-6R8-R LINE REGULATION (VIN = 5V, IOUT = 1A) = 0.017%/V LOAD REGULATION (VPWR = 12V, VIN = 5V) = –0.23%/A RELATED PARTS PART NUMBER LT3581 LT3580 LT3479 DESCRIPTION 3.3A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC Converter 2A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC Converter 3A (ISW), 40V, 3.5MHz, High Efficiency Step-Up DC/DC Converter COMMENTS VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = < 1μA, 4mm × 3mm DFN-14, MSOP-16E VIN: 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD = < 1μA, 3mm × 3mm DFN-8, MSOP-8E VIN: 2.5V to 24V, VOUT(MAX) = 40V, IQ = 5mA, ISD = < 1μA, 4mm × 3mm DFN-14, TSSOP-16E 35791f 40 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0410 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010