LT3581IMSE-TRPBF

LT3581 3.3A Boost/Inverting DC/DC Converter with Fault Protection FeaTures n n n n DescripTion The LT®3581 is a PWM DC/DC converter with built-in fault protection features to aid in protecting against output shorts, input/output overvoltages, and overtemperature conditions. The part consists of a 42V master switch, and a 42V slave switch that can be tied together for a total current limit of 3.3A. The LT3581 is ideal for many local power supply designs. It can be easily configured in Boost, SEPIC, Inverting or Flyback configurations, and is capable of generating 12V at 830mA, or –12V at 625mA from a 5V input. In addition, the LT3581’s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are very efficient and require fewer components than traditional circuits. The LT3581’s switching frequency range can be set between 200kHz and 2.5MHz. The part may be clocked internally at a frequency set by the resistor from the RT pin to ground, or it may be synchronized to an external clock. A buffered version of the clock signal is driven out of the CLKOUT pin, and may be used to synchronize other compatible switching regulator ICs to the LT3581. The LT3581 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT3581 is available in 14-Pin 4mm × 3mm DFN and 16-Lead MSE packages. Efficiency and Power Loss vs Load Current 100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 3581 TA01 n n n n n n n n 3.3A, 42V Combined Power Switch Master/Slave (1.9A/1.4A) Switch Design Output Short Circuit Protection Wide Input Range: 2.5V to 22V Operating, 40V Maximum Transient Switching Frequency Up to 2.5MHz Easily Configurable as a Boost, SEPIC, Inverting or Flyback Converter User Configurable Undervoltage Lockout Low VCESAT Switch: 250mV at 2.75A (Typical) Can be Synchronized to External Clock Can Be Synchronized to other Switching Regulators High Gain SHDN Pin Accepts Slowly Varying Input Signals 14-Pin 4mm × 3mm DFN and 16-Lead MSE Packages applicaTions n n n n Local Power Supply Vacuum Fluorescent Display (VFD) Bias Supplies TFT-LCD Bias Supplies Automotive Engine Control Unit (ECU) Power L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7579816. Typical applicaTion Output Short Protected, 5V to 12V Boost Converter Operating at 2MHz VIN 5V 18.7k 1.5µH 4.7µF SW1 SW2 100k VIN FAULT SHDN 10k 43.2k RT SYNC GND LT3581 FB GATE CLKOUT VC SS 56pF 0.1µF 4.7µF 10.5k 1nF 130k VOUT 12V 830mA 6.04k VIN 2000 1800 1600 1400 1200 1000 800 600 400 200 0 200 600 800 400 LOAD CURRENT (mA) 0 1000 3581 TA01b POWER LOSS (mW) 4.7µF 3581f  LT3581 absoluTe MaxiMuM raTings (Note 1) VIN Voltage ................................................. –0.3V to 40V SW1/SW2 Voltage ..................................... –0.4V to 42V RT Voltage ................................................... –0.3V to 5V SS, FB Voltage .......................................... –0.3V to 2.5V VC Voltage .................................................... –0.3V to 2V SHDN Voltage ............................................ –0.3V to 40V SYNC Voltage............................................ –0.3V to 5.5V GATE Voltage ............................................. –0.3V to 80V FAULT Voltage ............................................ –0.3V to 40V FAULT Current .....................................................±500µA CLKOUT Voltage .......................................... –0.3V to 3V CLKOUT Current ......................................................1mA Operating Junction Temperature Range LT3581E (Notes 2, 4) ......................... –40°C to 125°C LT3581I (Notes 2, 4) .......................... –40°C to 125°C Storage Temperature Range .................. –65°C to 150°C pin conFiguraTion TOP VIEW FB VC GATE FAULT VIN SW1 SW1 1 2 3 4 5 6 7 15 GND 14 SYNC 13 SS 12 RT 11 SHDN 10 CLKOUT 9 SW2 8 SW2 TOP VIEW FB VC GATE FAULT VIN SW1 SW1 SW1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SYNC SS RT SHDN CLKOUT SW2 SW2 SW2 17 GND DE14 PACKAGE 14-PIN (4mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB MSE PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH LT3581EDE#PBF LT3581IDE#PBF LT3581EMSE#PBF LT3581IMSE#PBF TAPE AND REEL LT3581EDE#TRPBF LT3581IDE#TRPBF LT3581EMSE#TRPBF LT3581IMSE#TRPBF PART MARKING* 3581 3581 3581 3581 PACKAGE DESCRIPTION 14-Lead (4mm × 3mm) Plastic DFN 14-Lead (4mm × 3mm) Plastic DFN 16-Lead Plastic MSOP 16-Lead Plastic MSOP TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3581f  LT3581 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2). PARAMETER Minimum Input Voltage VIN Overvoltage Lockout Positive Feedback Voltage Negative Feedback Voltage Positive FB Pin Bias Current Negative FB Pin Bias Current Error Amp Transconductance Error Amp Voltage Gain Quiescent Current Quiescent Current in Shutdown Reference Line Regulation Switching Frequency, fOSC Switching Frequency in Foldback Switching Frequency Range SYNC High Level for Synchronization SYNC Low Level for Synchronization SYNC Clock Pulse Duty Cycle Recommended Minimum SYNC Ratio fSYNC/fOSC Minimum Off-Time Minimum On-Time SW1 Current Limit Current Sharing (SW2/SW1) SW1 + SW2 Current Limit Switch VCESAT SW1 Leakage Current SW2 Leakage Current At All Duty Cycles, SW2/SW1 = 78% (Note 3) SW1 & SW2 Tied Together, ISW1 + ISW2 = 2.75A VSW1 = 5V VSW2 = 5V l l l elecTrical characTerisTics CONDITIONS MIN l TYP 2.3 23.5 1.215 9 83.3 83.3 270 70 1.9 0 0.01 MAX 2.5 25 1.230 16 85 85.5 UNITS V V V mV µA µA µmhos V/V 22.1 1.195 3 81 81 VFB = Positive Feedback Voltage, Current into Pin VFB = Negative Feedback Voltage, Current out of Pin ΔI = 10μA Not Switching VSHDN = 0V 2.5V ≤ VIN ≤ 20V RT = 34k RT = 432k Compared to Normal fOSC Free-Running or Synchronizing l l 2.3 1 0.05 2.75 220 2500 0.4 mA µA %/V MHz kHz ratio kHz V V % l l 2.25 180 200 1.3 20 2.5 200 1/6 l l l VSYNC = 0V to 2V 80 3/4 45 55 ns ns 3 5.4 1 1 A % A mV µA µA At All Duty Cycles l 1.9 3.3 2.4 78 4.3 250 0.01 0.01 3581f  LT3581 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2). PARAMETER Soft-Start Charge Current Soft-Start Discharge Current Soft-Start High Detection Voltage Soft-Start Low Detection Voltage SHDN Minimum Input Voltage High SHDN Input Voltage Low SHDN Pin Bias Current CONDITIONS VSS = 30mV, Current Flows Out of SS pin Part in FAULT, VSS = 2.1V, Current Flows into SS Pin Part in FAULT Part Exiting FAULT Active Mode, SHDN Rising Active Mode, SHDN Falling Shutdown Mode VSHDN = 3V VSHDN = 1.3V VSHDN = 0V CCLKOUT = 50pF CCLKOUT = 50pF TJ = 25°C CCLKOUT = 50pF CCLKOUT = 50pF VGATE = 3V VGATE = 80V VGATE = 50V, GATE Off 100μA into FAULT Pin VFAULT = 40V, FAULT Off l l l l l l l l l l l l elecTrical characTerisTics MIN 5.7 5.7 1.65 30 1.27 1.24 TYP 8.7 8.7 1.8 50 1.33 1.3 40 11.4 0 2.1 5 42 12 8 MAX 11.3 11.3 1.95 85 1.41 1.38 0.3 60 13.4 0.1 2.3 200 UNITS µA µA V mV V V V µA µA µA V mV % ns ns 9.7 1.9 CLKOUT Output Voltage High CLKOUT Output Voltage Low CLKOUT Duty Cycle CLKOUT Rise Time CLKOUT Fall Time GATE Pull Down Current GATE Leakage Current FAULT Output Voltage Low FAULT Leakage Current FAULT Input Voltage Low FAULT Input Voltage High 800 800 933 933 0.01 150 0.01 1100 1100 1 300 1 800 1050 µA µA µA mV µA mV mV 700 950 750 1000 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3581E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40°C to 125°C junction temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. 3581f  LT3581 Typical perForMance characTerisTics Switch Fault Current Limit vs Duty Cycle 6 SW1 + SW2 FAULT CURRENT LIMIT (A) 5 4 3 2 1 0 20 450 CURRENT SHARING = SW2/SW1 (%) 0 1 2 3 400 SATURATION VOLTAGE (mV) 350 300 250 200 150 100 50 30 60 50 40 DUTY CYCLE (%) 70 80 3581 G01 TA = 25°C, unless otherwise noted. Current Sharing Between SW1 and SW2 When Tied Together 100 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 3581 G03 Switch Saturation Voltage with SW1 and SW2 Tied Together 0 4 5 3581 G02 SW1 + SW2 CURRENT (A) SW1 + SW2 CURRENT (A) Switch Fault Current Limit vs Temperature 6 SW1 + SW2 FAULT CURRENT LIMIT (A) 5 POSITIVE FB VOLTAGE (V) 1.2175 1.2200 Positive Feedback Voltage vs Temperature 80 70 60 CLKOUT DC (%) 50 40 30 20 CLKOUT Duty Cycle vs Temperature 4 3 2 1 0 –50 –25 1.2150 1.2125 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G04 1.2100 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G05 10 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G06 Oscillator Frequency 3200 SWITCHING FREQUENCY RATIO (fSW/fOSC) 2800 2400 FREQUENCY (kHz) 2000 1600 1200 800 400 0 –50 –25 0 RT = 432k 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G07 Frequency Foldback 1 1000 900 800 GATE CURRENT (µA) 700 600 500 400 300 200 INVERTING CONFIGURATIONS 0 0.2 BOOSTING CONFIGURATIONS 1.0 1.2 3581 G08 Gate Current vs Gate Voltage –40°C 25°C 125°C RT = 34k 1/2 1/3 1/4 1/5 1/6 0 100 0 0 20 40 60 GATE VOLTAGE (V) 80 3581 G09 0.4 0.6 0.8 FB VOLTAGE (V) 3581f  LT3581 Typical perForMance characTerisTics Gate Current vs SS Voltage 1000 900 SW1 + SW2 CURRENT (A) 800 GATE CURRENT (µA) 700 600 500 400 300 200 100 0 0 0.25 0.50 0.75 1.00 SS VOLTAGE (V) 1.25 1.50 0 0 0.2 0.4 0.6 0.8 SS VOLTAGE (V) 1.0 1.2 3580 G11 TA = 25°C, unless otherwise noted. SHDN Voltage Threshold with Hysteresis 1.40 1.38 Commanded Current Limit vs SS Voltage 5 4 SHDN VOLTAGE (V) 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 –50 –25 SHDN RISING 3 2 SHDN FALLING 1 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G12 3581 G10 SHDN Pin Current 32 28 SHDN PIN CURRENT (µA) 24 20 16 12 8 4 0 125°C –40°C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SHDN VOLTAGE (V) 3581 G13 SHDN Pin Current 250 25°C SHDN PIN CURRENT (µA) –40°C 2.40 2.38 2.36 VIN VOLTAGE (V) 25°C 150 125°C 100 2.34 2.32 2.30 2.28 2.26 2.24 2.22 0 0 5 10 15 20 25 30 SHDN VOLTAGE (V) 35 40 Internal UVLO 200 50 2.20 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G15 3581 G14 CLKOUT Rise Time at 1MHz 50 45 CLKOUT RISE OR FALL TIME (ns) 40 35 30 25 20 15 10 5 0 0 50 100 150 200 CLKOUT CAPACITIVE LOAD (pF) 250 3581 G16 30 28 VIN OVLO FAULT Input Voltage Threshold with Hysteresis 1.25 FAULT RISING FAULT VOLTAGE (V) CLKOUT RISE TIME VIN VOLTAGE (V) 1.00 26 24 22 20 18 16 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G17 0.75 FAULT FALLING 0.50 CLKOUT FALL TIME 0.25 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G18 3581f  LT3581 pin FuncTions (DFN/MSOP) FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For a Boost or Inverting Converter, tie a resistor from the FB pin to VOUT according to the following equations: – 1.215V  V RFB =  OUT ; Boost or SEPIC Converter  83.3 • 10 –6    | V | + 9mV  RFB =  OUT ; Inverting Converter  83.3 • 10 –6   VC (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. GATE (Pin 3/Pin 3): PMOS Gate Drive Pin. The GATE pin is a pull-down current source, used to drive the gate of an external PMOS for output short circuit protection or output disconnect. The GATE pin current increases linearly with the SS pin’s voltage, with a maximum pull-down current of 933µA at SS voltages exceeding 500mV. Note that if the SS voltage is greater than 500mV and the GATE pin voltage is less than 2V, then the GATE pin looks like a 2kΩ impedance to ground. See the Appendix for more information. FAULT (Pin 4/Pin 4): Fault Indication Pin. This active low, bidirectional pin can either be pulled low (below 750mV) by an external source, or internally by the chip to indicate a fault. When pulled low, this pin causes the power switches to turn off, the GATE pin to become high impedance, the CLKOUT pin to become disabled, and the SS pin to go through a charge/discharge sequence. The end/absence of a fault is indicated when the voltage on this pin exceeds 1V. A pull-up resistor or current source is needed on this pin to pull it above 1V in the absence of a fault. VIN (Pin 5/Pin 5): Input Supply Pin. Must be locally bypassed. SW1 (Pins 6, 7/Pins 6,7, 8): Master Switch Pin. This is the collector of the internal master NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. SW2 (Pins 8, 9/Pins 9, 10, 11): Slave Switch Pin. This is the collector of the internal slave NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. CLKOUT (Pin 10/Pin 12): Clock Output Pin. Use this pin to synchronize one or more other compatible switching regulator ICs to the LT3581. The clock that this pin outputs runs at the same frequency as the internal oscillator of the part or as the SYNC pin. CLKOUT may also be used as a temperature monitor since the CLKOUT pin’s duty cycle varies linearly with the part’s junction temperature. Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF . SHDN (Pin 11/Pin 13): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 300mV to disable the chip. Drive above 1.33V (typical) to activate the chip and restart the soft-start sequence. Do not float this pin. RT (Pin 12/Pin 14): Timing Resistor Pin. Adjusts the LT3581’s switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. SS (Pin 13/Pin 15): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 250k resistor to about 2.1V. During a fault, the SS pin will be slowly charged up and eventually discharged as part of a timeout sequence (see the State Diagram for more information on the SS pin’s role during a fault event). SYNC (Pin 14/Pin 16): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must exceed 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Ground. Exposed pad must be soldered directly to local ground plane. 3581f  LT3581 block DiagraM VIN CIN RFAULT L1 D1 COUT1 OPTIONAL M1 RGATE COUT2 VOUT GATE SOFTSTART 2.1V 933µA VC FAULT DIE TEMP 165°C 22V MIN VIN 750mV ** + – + – + – SW1 42V MIN SW2 42V MIN ISW1 1.9A MIN TD ~ 30ns SAMPLE SAMPLE MODE BLOCK + – – + + – 50mV + – 1.8V 250k SS CSS SHDN 1.33V LDO – + STARTUP AND FAULT LOGIC ** + – + – 1.17V FB 45mV SW2 DRIVER DISABLE + – UVLO + – SR1 VBE • 0.9 Q2 SW1 RFB COMPARATOR – A3 A3 DRIVER Q 27m Q1 VIN 1.215V REFERENCE R + + A1 S + ∑ RAMP GENERATOR FREQUENCY FOLDBACK ÷N ADJUSTABLE OSCILLATOR SS SYNC BLOCK VC RC CC RT SYNC RT CLKOUT A4 14.6k FB RS 20m – + 14.6k A2 – GND – 3581 BD **SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3581 DURING SW OVERVOLTAGE EVENTS Figure 1. Block Diagram 3581f  LT3581 sTaTe DiagraM SHDN < 1.33V (TYPICAL) or VIN < 2.3V (TYPICAL) CHIP OFF • ALL SWITCHES DISABLED • IGATE OFF • FAULTS CLEARED SHDN > 1.33V (TYPICAL) AND VIN > 2.3V (TYPICAL) INITIALIZE • SS PULLED LOW FAULT1 FAULT2 SS < 50mV FAULT DETECTED • SS CHARGES UP • IGATE OFF • FAULT PIN PULLED LOW INTERNALLY BY LT3581 • SWITCHER DISABLED • CLKOUT DISABLED SS > 1.8V AND NO FAULT1 CONDITIONS STILL DETECTED POST FAULT DELAY SOFT START • IGATE ENABLED • SS CHARGES UP • SWITCHER ENABLED FAULT1 SAMPLE MODE • Q1 & Q2 SWITCHES FORCED ON EVERY CYCLE FOR AT LEAST MINIMUM ON TIME • IGATE FULLY ACTIVATED WHEN SS > 500mV • SS SLOWLY DISCHARGES FAULT1 FAULT1 SS < 50mV LOCAL FAULT OVER • INTERNAL FAULT PIN PULLDOWN RELEASED BY LT3581 • SS CONTINUES DISCHARGING TO GND NORMAL MODE • NORMAL OPERATION • CLKOUT ENABLED WHEN SS > 1.8V FAULT1 FAULT PIN > 1.0V FAULT1 IF |VOUT| DROPS CAUSING: FB < 1.17V (BOOST) OR FB > 45mV (INVERTING) FAULT1 = OVER VOLTAGE PROTECTION ON VIN (VIN > 22V MIN) OVER TEMPERATURE (TJUNCTION > 165°C) OVER CURRENT ON SW1 (ISW1 > 1.9A MIN) OVER VOLTAGE PROTECTION ON SW1 (VSW1 > 42V MIN) OVER VOLTAGE PROTECTION ON SW2 (VSW2 > 42V MIN) FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V) 3581 SD Figure 2. State Diagram 3581f  LT3581 operaTion OPERATION – OVERVIEW The LT3581 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function, together with soft-start and frequency foldback, offers a controlled means of starting up. Fault features are incorporated in the LT3581 to aid in the detection of output shorts, over-voltage, and overtemperature conditions. Refer to the Block Diagram (Figure 1) and the State Diagram (Figure 2) for the following description of the part’s operation. OPERATION – START-UP Several functions are provided to enable a very clean start-up for the LT3581: Precise Turn-On Voltage The SHDN pin is compared to an internal voltage reference to give a precise turn on voltage level. Taking the SHDN pin above 1.33V (typical) enables the part. Taking the SHDN pin below 300mV shuts down the chip, resulting in extremely low quiescent current. The SHDN pin has 30mV of hysteresis to protect against glitches and slow ramping. Undervoltage Lockout (UVLO) The SHDN pin can also be used to create a configurable UVLO. The UVLO function sets the turn on/off of the LT3581 at a desired input voltage (VINUVLO). Figure 3 shows how a resistor divider (or single resistor) from VIN to the SHDN pin can be used to set VINUVLO. RUVLO2 is optional. It may be left out, in which case set it to infinite in the equation below. For increased accuracy, set RUVLO2 ≤ 10k. Pick RUVLO1 as follows: RUVLO1 = VINUVLO – 1.33V  1.33V  R  + 11.6µA   UVLO2 VIN RUVLO1 SHDN RUVLO2 (OPTIONAL) VIN 1.33V – + ACTIVE/ LOCKOUT 11.6µA AT 1.33V GND 3581 F03 Figure 3. Configurable UVLO The LT3581 also has internal UVLO circuitry that disables the chip when VIN < 2.3V (typical). Soft-Start of Switch Current The soft-start circuitry provides for a gradual ramp-up of the switch current (refer to Commanded Current Limit vs SS Voltage in Typical Performance Characteristics). When the part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic circuits in the chip. Then an integrated 250k resistor pulls the SS pin to ~1.8V. The ramp rate of the SS pin voltage is set by this 250k resistor and the external capacitor connected to this pin. Once SS gets to 1.8V, the CLKOUT pin is enabled, and an internal regulator pulls the pin up quickly to ~2.1V. Typical values for the external soft-start capacitor range from 100nF to 1μF . Soft-Start of External PMOS (if used) The soft-start circuitry also gradually ramps up the GATE pin pull-down current which allows an external PMOS to slowly turn on (M1 in Block Diagram). The GATE pin current increases linearly with the SS voltage, with a maximum current of 933µA when the SS voltage gets above 500mV. Note that if the GATE pin voltage is less than 2V for SS voltages exceeding 500mV, then the GATE pin impedance to ground is 2kΩ. The soft turn on of the external PMOS helps limit inrush current at start-up, making hot-plugs of LT3581s feasible and safe. 3581f 0 LT3581 operaTion Sample Mode Sample Mode is the mechanism used by the LT3581 to aid in the detection of output shorts. It refers to a state of the LT3581 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch current limit of 1.9A (min), the LT3581 triggers an overcurrent fault internally (see Operation-Fault section for details). Sample Mode is active when FB is out of regulation by more than approximately 3.7% (45mV < FB < 1.17V). Frequency Foldback The frequency foldback circuit reduces the switching frequency when 350mV < FB < 900mV (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current during start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal. Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target VOUT, VIN, switching frequency, etc. Test each and every application’s performance at start-up to ensure that the peak inductor current does not exceed the minimum fault current limit. OPERATION – REGULATION The following description of the LT3581’s operation assumes that the FB voltage is close enough to its regulation target so that the part is not in sample mode. Use the Block Diagram as a reference when stepping through the following description of the LT3581 operating in regulation. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switches Q1 and Q2. The collector current through the master switch, Q1, is ~1.3 times the collector current through the slave switch, Q2, when the collectors of the two switches are tied together. Q1’s emitter current flows through a current sense resistor (RS) generating a voltage proportional to the total switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When the voltage on the positive input of A3 exceeds the voltage on the negative input, the SR latch is reset, turning off the master and slave power switches. The voltage on the negative input of A3 (VC pin) is set by A1 (or A2), which is simply an amplified difference between the FB pin voltage and the reference voltage (1.215V if the LT3581 is configured as a boost converter, or 9mV if configured as an inverting converter). In this manner, the error amplifier sets the correct peak current level to maintain output regulation. As long as the part is not in fault (see Operation – Fault section) and the SS pin exceeds 1.8V, the LT3581 drives its CLKOUT pin at the frequency set by the RT pin or the SYNC pin. The CLKOUT pin can be used to synchronize other compatible switching regulator ICs (including additional LT3581s) with the LT3581. Additionally, CLKOUT’s duty cycle varies linearly with the part’s junction temperature, and may be used as a temperature monitor. OPERATION – FAULT The LT3581’s FAULT pin is an active low, bidirectional pin that is pulled low to indicate a fault. Each of the following events can trigger a fault in the LT3581: A. FAULT1 events: 1. SW Overcurrent: a. ISW1 > 1.9A (minimum) b. (ISW1 + ISW2) > 3.3A (minimum) 2. VIN Voltage > 22V (minimum) 3. SW1 Voltage and/or SW2 Voltage > 42V (minimum) 4. Die Temperature > 165°C B. FAULT2 events: 1. Pulling the FAULT pin low externally 3581f  LT3581 operaTion Refer to the State Diagram (Figure 2) for the following description of the LT3581’s operation during a fault event. When a fault is detected, in addition to the FAULT pin being pulled low internally, the LT3581 also disables its CLKOUT pin, turns off its power switches, and the GATE pin becomes high impedance. The external PMOS, M1, turns off when the gate of M1 is pulled up to its source by the external RGATE resistor (see Block Diagram). With the external PMOS turned off, the power path from VIN to VOUT is cut off, protecting power components downstream. At the same time, a timeout sequence commences where the SS pin is charged up to 1.8V (the SS pin will continue charging up to 2.1V and be held there in the case of a FAULT1 event that has still not ended), and then discharged to 50mV. This timeout period relieves the part, the PMOS, and other downstream power components from electrical and thermal stress for a minimum amount of time as set by the voltage ramp rate on the SS pin. In the absence of faults, the FAULT pin is pulled high by the external RFAULT resistor (typically 100k). Figure 4 shows the events that accompany the detection of an output short on the LT3581. VOUT 10V/DIV VFAULT 5V/DIV VCLKOUT 2V/DIV IL 2A/DIV 5µs/DIV 3581 F04 Figure 4. Output Short Circuit Protection of the LT3581 3581f  LT3581 applicaTions inForMaTion BOOST CONVERTER COMPONENT SELECTION VIN 5V L1 1.5µH D1 20V, 2A COUT1 4.7µF FB LT3581 GATE CLKOUT VC SS GND CF 56pF CSS 0.1µF RC 10.5k CC 1nF 3581 F05 Table 1. Boost Design Equations PARAMETERS/EQUATIONS VOUT 12V IOUT < 0.83A OPTIONAL PMOS RGATE 6.04k Step 1: Pick VIN, VOUT, and fOSC to calculate equations below. Inputs Step 2: DC SW1 SW2 CIN 4.7µF RFAULT 100k VIN DC ≅ FAULT SHDN RT RFB 130k COUT2 4.7µF VOUT – VIN + 0.5V VOUT + 0.5V – 0.3V (1) (2) (3) L TYP = LMIN = Step 3: L1 ( VIN – 0.3V ) • DC fOSC • 1A RT 43.2k SYNC Figure 5. Boost Converter – The Component Values and Voltages Given Are Typical Values for a 2MHz, 5V to 12V Boost LMAX ( VIN – 0.3V ) • (2 • DC – 1) 2.2A • fOSC • (1 – DC) ( V – 0.3V ) • DC = IN fOSC • 0.35A The LT3581 can be configured as a Boost converter as in Figure 5. This topology allows for positive output voltages that are higher than the input voltage. An external PMOS (optional) driven by the GATE pin of the LT3581 can achieve input or output disconnect during a fault event. A single feedback resistor sets the output voltage. For output voltages higher than 40V, see the Charge Pump Aided Regulators section. Table 1 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a boost converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 1. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current RDSON_PMOS = RDSON of External PMOS (set to 0 if not using PMOS) • Pick L1 out of a range of inductor values where the minimum value of the range is set by LTYP or LMIN, whichever is higher. The maximum value of the range is set by LMAX. See appendix on how to choose current rating for inductor value chosen. Step 4: IRIPPLE Step 5: IOUT Step 6: D1 IRIPPLE = ( VIN – 0.3V ) • DC fOSC • L1 I   IOUT =  3.3A – RIPPLE  • (1 – DC)  2 VR > VOUT ; IAVG > IOUT COUT1 = COUT2 ≥ IOUT • DC Step 7: COUT1, COUT2 fOSC 0.01 • VOUT – 0.50 • IOUT • RDSON _ PMOS    • If PMOS is not used, then use just one capacitor where COUT = COUT1 + COUT2. Step 8: CIN CIN ≥ C VIN + CPWR ≥ 3.3A • DC IRIPPLE + 45 • fOSC • 0.005 • VIN 8 • fOSC • 0.005 • VIN • Refer to Input Capacitor Selection in Appendix for definition of CVIN and CPWR. Step 9: RFB Step 10: RT RFB = RT = VOUT – 1.215V 83.3µA 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Only needed for input or output disconnect. See PMOS Selection Step 11: in the Appendix for information on sizing the PMOS, RGATE and PMOS picking appropriae UVLO components. Note 1: The maximum design target for peak switch current is 3.3A and is used in this table. Note 2: The final values for COUT1, COUT2 and CIN may deviate from the above equations in order to obtain desired load transient performance. 3581f  LT3581 applicaTions inForMaTion SEPIC CONVERTER COMPONENT SELECTION (COUPLED OR UN-COUPLED INDUCTORS) VIN 3V TO 16V L1 3.3µH C1 1µF D1 30V, 2A COUT 22µF 2 RFB 45.3k VOUT 5V IOUT < 0.9A (VIN = 3V) IOUT < 1.5A (VIN = 12V) Table 2. SEPIC Design Equations PARAMETERS/EQUATIONS Step 1: Inputs Step 2: DC Pick VIN, VOUT, and fOSC to calculate equations below. • CIN 22µF SW1 SW2 L2 3.3µH FB DC ≅ VOUT + 0.5V VIN + VOUT + 0.5V – 0.3V fOSC • 1A (1) (2) (3) RFAULT 100k ENABLE RT 124k VIN FAULT SHDN RT SYNC LT3581 GATE CLKOUT VC SS GND CSS 1µF RC 7.87k CC 2.2nF CF 100pF 3581 F06 Figure 6. SEPIC Converter – The Component Values and Voltages Given Are Typical Values for a 700kHz, Wide Input Range (3V to 16V) SEPIC Converter with 5V Out The LT3581 can also be configured as a SEPIC as shown in Figure 6. This topology allows for positive output voltages that are lower, equal, or higher than the input voltage. Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output due to capacitor C1. This implies that a PMOS controlled by the GATE pin is not required in the power path. Table 2 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a SEPIC converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 2. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current  • L TYP = LMIN = Step 3: L ( VIN – 0.3V ) • DC LMAX ( VIN – 0.3V ) • (2 • DC – 1) 2.2A • fOSC • (1 – DC) ( V – 0.3V ) • DC = IN fOSC • 0.35A • Pick L out of a range of inductor values where the minimum value of the range is set by LTYP or LMIN, whichever is higher. The maximum value of the range is set by LMAX. See Appendix on how to choose current rating for inductor value chosen. • Pick L1 = L2 = L for coupled inductors. • Pick L1L2 = L for un-coupled inductors. Step 4: IRIPPLE IRIPPLE = ( VIN – 0.3V ) • DC fOSC • L • L = L1 = L2 for coupled inductors. • L = L1L2 for un-coupled inductors. Step 5: IOUT Step 6: D1 Step 7: C1 Step 8: COUT I   IOUT =  3.3A – RIPPLE  • (1 – DC)  2 VR > VIN + VOUT ; IAVG > IOUT C1 ≥ 1µF; VRATING ≥ VIN COUT ≥ IOUT • DC fOSC • 0.005 • VOUT Step 9: CIN CIN ≥ C VIN + CPWR ≥ 3.3A • DC IRIPPLE + 45 • fOSC • 0.005 • VIN 8 • fOSC • 0.005 • VIN • Refer to Input Capacitor Selection in Appendix for definition of CVIN and CPWR. Step 10: RFB Step 11: RT RFB = RT = VOUT – 1.215V 83.3µA 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Note 1: The maximum design target for peak switch current is 3.3A and is used in this table. Note 2: The final values for COUT, CIN and C1 may deviate from the above equations in order to obtain desired load transient performance. 3581f LT3581 applicaTions inForMaTion DUAL INDUCTOR INVERTING CONVERTER COMPONENT SELECTION (COUPLED OR UN-COUPLED INDUCTORS) VIN 5V L1 3.3µH C1 1µF L2 3.3µH VOUT –12V IOUT < 625mA Table 3. Dual Inductor Inverting Design Equations PARAMETERS/EQUATIONS Step 1: Inputs Pick VIN, VOUT, and fOSC to calculate equations below. CIN 3.3µF SW1 SW2 VIN FAULT SHDN RT SYNC GND FB LT3581 GATE CLKOUT VC SS D1 20V 1A COUT 4.7µF RFB 143k Step 2: DC DC ≅ | VOUT | + 0.5V VIN + | VOUT | +0.5V – 0.3V (1) (2) (3) • • RFAULT 100k ENABLE RT 43.2k L TYP = LMIN = ( VIN – 0.3V ) • DC fOSC • 1A CSS 100nF RC 11k CC 1nF CF 47pF 3581 F07 Step 3: L LMAX ( VIN – 0.3V ) • (2 • DC – 1) 2.2A • fOSC • (1 – DC) ( V – 0.3V ) • DC = IN fOSC • 0.35A Figure 7. Dual Inductor Inverting Converter – The Component Values and Voltages Given Are Typical Values for a 2MHz, 5V to –12V Inverting Topology Using Coupled Inductors Due to its unique FB pin, the LT3581 can work in a Dual Inductor Inverting configuration as in Figure 7. Changing the connections of L2 and the Schottky diode in the SEPIC topology results in generating negative output voltages. This solution results in very low output voltage ripple due to inductor L2 being in series with the output. Output disconnect is inherently built into this topology due to the capacitor C1. Table 3 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a dual inductor inverting converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 3. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current • Pick L out of a range of inductor values where the minimum value of the range is set by LTYP or LMIN, whichever is higher. The maximum value of the range is set by LMAX. See Appendix on how to choose current rating for inductor value chosen. • Pick L1 = L2 = L for coupled inductors. • Pick L1L2 = L for un-coupled inductors. Step 4: IRIPPLE IRIPPLE = ( VIN – 0.3V ) • DC fOSC • L • L = L1 = L2 for coupled inductors. • L = L1L2 for un-coupled inductors. Step 5: IOUT Step 6: D1 Step 7: C1 Step 8: COUT I   IOUT =  3.3A – RIPPLE  • (1 – DC)  2 VR > VIN + | VOUT | ; IAVG > IOUT C1 ≥ 1µF; VRATING ≥ VIN + | VOUT | COUT ≥ IRIPPLE 8 • fOSC ( 0.005 • | VOUT |) CIN ≥ C VIN + CPWR ≥ Step 9: CIN 3.3A • DC IRIPPLE + 45 • fOSC • 0.005 • VIN 8 • fOSC • 0.005 • VIN • Refer to Input Capacitor Selection in Appendix for definition of CVIN and CPWR. Step 10: RFB RFB = RT = | VOUT | + 5mV 83.3µA Step 11: RT 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Note 1: The maximum design target for peak switch current is 3.3A and is used in this table. Note 2: The final values for COUT, CIN and C1 may deviate from the above equations in order to obtain desired load transient performance. 3581f  LT3581 applicaTions inForMaTion LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL INDUCTOR INVERTING TOPOLOGIES General Layout Guidelines • To optimize thermal performance, solder the exposed ground pad of the LT3581 to the ground plane, with multiple vias around the pad connecting to additional ground planes. • A ground plane should be used under the switcher circuitry to prevent interplane coupling and overall noise. • High speed switching path (see specific topology for more information) must be kept as short as possible. • The VC , FB, and RT components should be placed as close to the LT3581 as possible, while being as far away as practically possible from the switch node. The ground for these components should be separated from the switch current path. • Place the bypass capacitor for the VIN pin as close as possible to the LT3581. • Place the bypass capacitor for the inductor as close as possible to the inductor. • The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. GND 1 1 2 3 4 5 CIN A – VIN + 6 7 8 L1 17 16 15 14 13 12 11 10 9 D1 D2 RGATE 3581 F08 Boost Topology Specific Layout Guidelines • Keep length of loop (high speed switching path) governing switch, diode D1, output capacitor COUT1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. SEPIC Topology Specific Layout Guidelines • Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, output capacitor COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. Inverting Topology Specific Layout Guidelines • Keep ground return path from the cathode of D1 (to chip) separated from output capacitor COUT’s ground return path (to chip) in order to minimize switching noise coupling into the output. • Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. GND 16 17 15 14 13 12 11 10 9 D1 B SYNC SYNC 2 3 4 SHDN CLKOUT SHDN CLKOUT B – VOUT + M1 CIN 5 6 7 A – VIN + 8 COUT COUT1 – L2 C1 COUT 3581 F09 • VOUT + L1 A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT AND COUT1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT AND COUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. A: RETURN CIN AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE. • Figure 8. Suggested Component Placement for Boost Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance Figure 9. Suggested Component Placement for SEPIC Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance 3581f  LT3581 applicaTions inForMaTion GND 1 2 3 4 5 CIN A – VIN + 6 7 8 C C1 D1 17 16 15 14 13 12 11 10 9 B SYNC SHDN CLKOUT the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. Power and Thermal Calculations Power dissipation in the LT3581 chip comes from four primary sources: switch I2R losses, switch dynamic losses, NPN base drive DC losses, and miscellaneous input current losses. These formulas assume continuous mode operation, so they should not be used for calculating thermal losses or efficiency in discontinuous mode or at light load currents. The following example calculates the power dissipation in the LT3581 for a particular boost application (VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz, VD = 0.45V, VCESAT = 0.21V). To calculate die junction temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: TJ = TA + θJA • PTOTAL GND COUT L1 L2 3581 F10 – VOUT • • A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD. C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE. Figure 10. Suggested Component Placement for Dual Inductor Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance THERMAL CONSIDERATIONS Overview For the LT3581 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate Table 4. Power Calculations Example for Boost Converter with VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz, VD = 0.45V, VCESAT = 0.21V DEFINITION OF VARIABLES DC = SWITCH DUTY CYCLE EQUATIONS DESIGN EXAMPLE VALUE DC = 60.9% DC = VOUT – VIN + VD VOUT + VD – VCESAT VOUT • IOUT VIN • η DC = 12V – 5V + 0.45V 12V + 0.45V – 0.21V 12V • 0.83A 5V • 0.88 IIN = Average Switch Current η = Power Conversion Efficiency (typically 88% at high currents) PSWDC = Switch I2R Loss (DC) RSW = Switch Resistance (typically 90mΩ combined SW1 and SW2) PSWAC = Switch Dynamic Loss (AC) PBDC = Base Drive Loss (DC) PINP = Input Power Loss IIN = IIN = IIN = 2.3A PSWDC = DC • IIN2 • RSW PSWAC = 13ns • IIN • VOUT • fOSC PBDC = VIN • IIN • DC 45 PSWDC = 0.609 • (2.3A)2 • 90mΩ PSWAC = (13ns ) • 2.3A • 12V • ( 2MHz ) PBDC = 5V • 2.3A • 0.609 45 PSWDC = 290mW PSWAC = 718mW PBDC = 156mW PINP = 45mW PTOTAL = 1.209W 3581f PINP = 9mA • VIN PINP = 9mA • 5V  LT3581 applicaTions inForMaTion where TJ = Die Junction Temperature, TA = Ambient Temperature, PTOTAL is the final result from the calculations shown in Table 4, and θJA is the thermal resistance from the silicon junction to the ambient air. The published (http://www.linear.com/designtools/packaging/Linear_Technology_Thermal_Resistance_Table.pdf) θJA value is 43°C/W for the 4mm × 3mm 14-pin DFN package and 45°C/W for the 16-lead MSOP package. In practice, lower θJA values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the Layout Guidelines section. For instance, a θJA value of ~24°C/W was consistently achieved for both MSE and DFN packages of the LT3581 (at VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz) when board layout was optimized as per the suggestions in the Board Layout Guidelines section. Junction Temperature Measurement The duty cycle of the CLKOUT signal is linearly proportional to die junction temperature, TJ. To get a temperature reading, measure the duty cycle of the CLKOUT signal and use the following equation to approximate the junction temperature: TJ = DCCLKOUT – 35% 0.3% Thermal Lockout A fault condition occurs when the die temperature exceeds 165°C (see Operation Section), and the part goes into thermal lockout. The fault condition ceases when the die temperature drops by ~5°C (nominal). SWITCHING FREQUENCY There are several considerations in selecting the operating frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 600kHz is desired. Some communications have sensitivity to 1.1MHz and in that case a 1.5MHz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The tradeoff is efficiency, since the losses due to switching dynamics (see Thermal Considerations), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency. Oscillator Timing Resistor (RT) The operating frequency of the LT3581 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: fOSC = 87.6 RT + 1 where DCCLKOUT is the CLKOUT duty cycle in % and TJ is the die junction temperature in °C. Although the actual die temperature can deviate from the above equation by ±15°C, the relationship between change in CLKOUT duty cycle and change in die temperature is well defined. Basically a 1% change in CLKOUT duty cycle corresponds to a 3.33°C change in die temperature. Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF . where fOSC is in MHz and RT is in k. Conversely, RT (in k) can be calculated from the desired frequency (in MHz) using: RT = 87.6 –1 fOSC 3581f  LT3581 applicaTions inForMaTion Clock Synchronization The operating frequency of the LT3581 can be set by an external source by simply providing a digital clock signal into the SYNC pin (RT resistor still required). The LT3581 will revert to its internal free-running oscillator clock (set by the RT resistor) when the SYNC pin is driven below 0.4V for a few free-running clock periods. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT3581 will stop and the CLKOUT pin will be held at ground. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: (1) SYNC may not toggle outside the frequency range of 200kHz to 2.5MHz unless it is stopped low (below 0.4V) to enable the free-running oscillator. (2) The SYNC frequency can always be higher than the free-running oscillator frequency (as set by the RT resistor), fOSC , but should not be less than 25% below fOSC. CLOCK SYNCHRONIzATION OF ADDITIONAL REGULATORS The CLKOUT pin of the LT3581 can be used to synchronize one or more other compatible switching regulator ICs as shown in Figure 11. The frequency of the master LT3581 is set by the external RT resistor. The SYNC pin of the slave LT3581 is driven by the CLKOUT pin of the master LT3581. Note that the RT pin of the slave LT3581 must have a resistor tied to ground. It takes a few clock cycles for the CLKOUT signal to begin oscillating, and it’s preferable for all LT3581s to have the same internal free-running frequency. Therefore, in general, use the same value RT resistor for all of the synchronized LT3581s. VIN 5V 6.8µF 10k GATE VIN 100k ENABLE 43.2k FAULT SHDN RT SYNC 1.5µH 2.2µF 4.7µF SW1 GATE VIN SW2 FB VOUT –12V 450mA 143k CLKOUT LT3581 VC SHDN SLAVE FAULT RT SYNC SS GND 0.1µF 10k 2.2nF 100pF 43.2k 1.5µH 6.8µF SW1 SW2 CLKOUT LT3581 MASTER FB VC SS GND 0.1µF 4.7µF VOUT 12V 830mA 130k 10.5k 1nF 56pF 3581 F11 Figure 11. A Single Inductor Inverting Topology Is Synchronized with a Boost Regulator to Generate –12V and 12V Outputs. The External PMOS Helps Disconnect the Input from the Power Paths During Fault Events Also, the FAULT pins can be tied together so that a fault condition from one LT3581 causes all of the LT3581s to enter fault, until the fault condition disappears. CHARGE PUMP AIDED REGULATORS Designing charge pumps with the LT3581 can offer efficient solutions with fewer components than traditional circuits because of the master/slave switch configuration on the IC. Although the slave switch, SW2, operates in phase with the master switch, SW1, it is only the current through the master switch (SW1) that is sensed by the current comparator (A4 in Block Diagram) as part of the current feedback loop. This method of operation by the master/slave switches can offer the following benefits to charge pump designs: 3581f  LT3581 applicaTions inForMaTion • The slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes when the flying capacitors charge up. Since this current spike flows through SW2, it does not affect the operation of the current comparator (A4 in Block Diagram). • The master switch, immune from the capacitor current spike (seen only by the slave switch) can sense the inductor current more accurately. • Since the slave switch can sustain large current spikes, the diodes that feed current into the flying capacitors do not need current limiting resistors, leading to efficiency and thermal improvements. High VOUT Charge Pump Topology The LT3581 can be used in a charge-pump topology as shown in Figure 12, multiplying the output of an inductive boost converter. The master switch (SW1) can be used to drive the inductive boost converter (first stage of charge pump), while the slave switch (SW2) can be used to drive one or more other charge pump stages. This topology is useful for high voltage applications including VFD bias supplies. Single Inductor Inverting Topology If there is a need to use just one inductor to generate a negative output voltage whose magnitude is greater than VIN , the single inductor inverting topology (shown in Figure 13) can be used. Since the master and slave switches are isolated by a Schottky diode, the current spike through C1 will flow only through the slave switch, thereby preventing the current comparator, (A4 in the Block Diagram), from falsely tripping. Output disconnect is inherently built into the single inductor topology. 100k ENABLE 2.2µF 2.2µF 2.2µF 2.2µF VOUT2 97V 140mA VOUT1 65V 70mA VIN 12V 2.2µF 10µH SW1 SW2 100k VIN FAULT SHDN RT 43.2k SYNC LT3581 GND 2.2µF 8.06k FB GATE CLKOUT VC SS 0.47µF 100pF 24k 1nF 3581 F12 370k 2.2µF Figure 12. High VOUT Charge Pump Topology Can Be Used to Build VFD Bias Supplies VIN CIN L1 D1 C1 D2 D3 COUT VOUT < 0V AND |VOUT| > |VIN| RFB SW1 GATE VIN FAULT SHDN RT RT SW2 FB CLKOUT LT3581 VC SS SYNC GND CSS RVC CVC1 CVC2 3579 F13 Figure 13. Single Inductor Inverting Topology 3581f 0 LT3581 applicaTions inForMaTion HOT-PLUG The high inrush current associated with hot-plugging VIN can be largely rejected with the use of an external PMOS. A simple hot-plug controller can be designed by connecting an external PMOS in series with VIN, with the gate of the PMOS being driven by the GATE pin of the LT3581. Since the GATE pin pull-down current is linearly proportional to the SS voltage, and the SS charge up time is relatively slow, the GATE pin pull-down current will increase gradually, thereby turning on the external PMOS slowly. Controlled in this manner, the PMOS acts as an input current limiter when VIN hot-plugs or ramps up sharply. Likewise, when the PMOS is connected in series with the output, inrush currents into the output capacitor can be limited during a hot-plug event. To illustrate this, the circuit in Figure 18 was re-configured by adding a large 1500µF capacitor to the output. An 18Ω resistive load was used and a 2.2µF capacitor was placed on SS. Figure 14 shows the results of hot-plugging this re-configured circuit. Notice how the inductor current is well behaved. VIN 5V/DIV VOUT 10V/DIV IL 5A/DIV SS 1V/DIV 1s/DIV 3581 F14 Figure 14. Inrush Current Is Well Controlled in Spite Of HotPlugging the Re-configured Boost Converter in Figure 18 3581f  LT3581 appenDix SETTING THE OUTPUT VOLTAGE The output voltage is set by connecting a resistor (RFB) from VOUT to the FB pin. RFB is determined by using the following equation: RFB = | VOUT – VFB | 83.3µA For the SEPIC or Dual Inductor Inverting topology (see Figures 6 and 7): DCSEPIC _&_ INVERT ≅ VD + | VOUT | VIN + | VOUT | + VD − VCESAT For the Single Inductor Inverting topology (see Figure 13): DCSI _ INVERT = | VOUT | − VIN + VCESAT + 3 • VD | VOUT | + 3 • VD where VFB is 1.215V (typical) for non-inverting topologies (i.e. boost and SEPIC regulators) and 5mV (typical) for inverting topologies. POWER SWITCH DUTY CYCLE In order to maintain loop stability and deliver adequate current to the load, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “on” for 100% of each clock cycle. The maximum allowable duty cycle is given by: DCMAX = The LT3581 can be used in configurations where the duty cycle is higher than DCMAX , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. INDUCTOR SELECTION General Guidelines: The high frequency operation of the LT3581 allows for the use of small surface mount inductors. For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper-wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor only carries one half of the total switch current. Molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2A to 6A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 5 for a list of inductor manufacturers. Table 5. Inductor Manufacturers Sumida Coilcraft Vishay Taiyo Yuden Wurth TDK CDR6D28MN and CDR7D28MN Series MSD7342 Series IHLP-1616BZ-01, IHLP-2020BZ-01 and IHLP-2525CZ-01 Series NR Series WE-PD Series VLF SLF and RLF Series , www.sumida.com www.coilcraft.com www.vishay.com www.t-yuden.com www.we-online.com www.tdk.com ( TP – MinOffTime) • 100% TP where TP is the clock period and MinOffTime (found in the Electrical Characteristics) is typically 60ns. Conversely, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “off” for 100% of each clock cycle, and will turn on for a minimum on time (MinOnTime) when in regulation. This MinOnTime governs the minimum allowable duty cycle given by: DCMIN = (MinOnTime) • 100% TP Where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is typically 100ns. The application should be designed such that the operating duty cycle is between DCMIN and DCMAX. Duty cycle equations for several common topologies are given below where VD is the diode forward voltage drop and VCESAT is the collector to emitter saturation voltage of the switch. VCESAT, with SW1 and SW2 tied together, is typically 250mV when the combined switch current (ISW1 + ISW2) is 2.75A. For the boost topology (see Figure 5): DCBOOST ≅ VOUT – VIN + VD VOUT + VD – VCESAT 3581f  LT3581 appenDix Minimum Inductance Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are three conditions that limit the minimum inductance: (1) providing adequate load current, (2) avoidance of subharmonic oscillations and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. Adequate Load Current Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least: LBOOST >  | V |• I  2 • fOSC •  IPK − OUT OUT  V •η   IN Negative values of LBOOST or LDUAL indicate that the output load current, IOUT, exceeds the switch current limit capability of the LT3581. Avoiding Sub-Harmonic Oscillations The LT3581’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a certain minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LMIN = where: LMIN LMIN LMIN ( VIN − VCESAT ) • (2 • DC − 1) 2.2A • fOSC • (1− DC) = L1 for Boost Topologies (see Figure 5) = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 6 and 7) = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 6 and 7) DC • ( VIN − VCESAT ) Boost Topology LDUAL >   | V |• I 2• fOSC•  IPK − OUT OUT − IOUT  VIN • η   DC • ( VIN − VCESAT ) or SEPIC or Inverting Topologies Maximum Inductance Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A4 in the Block Diagram) to cleanly discriminate, causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX = where: LMAX LMAX LMAX = L1 for Boost Topologies (see Figure 5) = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 6 and 7) = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 6 and 7) VIN − VCESAT DC • 350mA fOSC where: LBOOST = L1 for Boost Topologies (see Figure 5) LDUAL = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 6 and 7) LDUAL = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 6 and 7) DC = Switch Duty Cycle (see Power Switch Duty Cycle section in Appendix) IPK = Maximum Peak Switch Current; should not exceed 3.3A for a combined SW1 + SW2 current, or 1.9A of SW1 current if SW1 is being used by itself. η = Power Conversion Efficiency (typically 88% for Boost and 75% for Dual Inductor Topologies at High Currents) fOSC = Switching Frequency IOUT = Maximum Output Current 3581f  LT3581 appenDix Inductor Current Rating Inductors must have a rating greater than their peak operating current, or else they could saturate and hence contribute to losses in efficiency. The maximum inductor current (considering start-up and steady-state conditions) is given by: IL _ PEAK = ILIM + where: IL_PEAK VIN • TMIN _ PROP L Multilayer ceramic capacitors are an excellent choice, as they have extremely low ESR and are available in very small packages. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. A 10μF to 22μF output capacitor is sufficient for most applications, but systems with very low output currents may need only 2.2μF to 10μF Always . use a capacitor with a sufficient voltage rating. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. Tantalum Polymer or OS-CON capacitors can be used, but it is likely that these capacitors will occupy more board area than a ceramic, and will have higher ESR with greater output ripple. INPUT CAPACITOR SELECTION Ceramic capacitors make a good choice for the input decoupling capacitor, and should be placed such that it is in close proximity to the VIN of the chip as well as to the inductor connected to the input of the power path. If it is not possible to optimally place a single input capacitor, then use two separate capacitors—use one at the VIN of the chip (see equation for CVIN in Tables 1, 2 and 3) and one at the input to the power path (see equation for CPWR in Tables 1, 2 and 3) A 4.7μF to 20μF input capacitor is sufficient for most applications. Table 6 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts. Table 6: Ceramic Capacitor Manufacturers AVX Murata Taiyo Yuden www.avxcorp.com www.murata.com www.t-yuden.com = Peak Inductor Current in L1 for a Boost Topology, or the Peak of the sum of the Inductor Currents in L1 and L2 for Dual Inductor Topologies. = 3.3A with SW1 and SW2 Tied Together, ILIM** or 1.9A with just SW1 (This assumes usage of an inductor whose core material soft-saturates such as powdered iron core). TMIN_PROP = 100ns (Propagation Delay through the Current Feedback Loop). **If using an inductor whose core material saturates hard (e.g., ferrite), then pick ILIM to be 5.4A with SW1 and SW2 tied together, or 3A when just SW1 is used. Note that these equations offer conservative results for the required inductor current ratings. The current ratings could be lower for applications with light loads, if the SS capacitor is sized appropriately to limit inductor currents at start-up. DIODE SELECTION Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT3581. Choose a Schottky diode with low parasitic capacitance to reduce reverse current spikes through the power switch of the LT3581. The Central Semiconductor Corp. CMMSH2-40 diode is a very good choice with a 40V reverse voltage rating and an average forward current of 2A. OUTPUT CAPACITOR SELECTION Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. PMOS SELECTION An external PMOS, controlled by the LT3581’s GATE pin, can be used to facilitate input or output disconnect. The GATE pin turns on the PMOS gradually during start-up (see Soft-Start of External PMOS in the Operation section), and turns the PMOS off when the LT3581 is in shutdown or in fault. 3581f  LT3581 appenDix The use of the external PMOS, controlled by the GATE pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. In a conventional boost regulator, the inductor, Schottky diode, and power switches are susceptible to damage in the event of an output short to ground. Using an external PMOS in the boost regulator’s power path (path from VIN to VOUT) controlled by the GATE pin, will serve to disconnect the input from the output when the output has a short to ground, thereby helping save the IC, and the other components in the power path from damage. Ensure that both, the diode and the inductor can survive low duty cycle current pulses of 3 to 4 times their steady state levels. The PMOS chosen must be capable of handling the maximum input or output current depending on whether the PMOS is used at the input (see Figure 11) or the output (see Figure 18). Ensure that the PMOS is biased with enough source to gate voltage (VSG) to enhance the device into the triode mode of operation. The higher the VSG voltage that biases the PMOS into triode, the lower the RDSON of the PMOS, thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application in which the PMOS is used. The following equations show the relationship between RGATE (see Block Diagram) and the desired VSG that the PMOS is biased with: RGATE  if VGATE < 2V  VIN VSG =  RGATE + 2kΩ  933µA • R GATE if VGATE ≥ 2V  When using a PMOS, it is advisable to configure the specific application for undervoltage lockout (see the Operations section). The goal is to have VIN get to a certain minimum voltage where the PMOS has sufficient headroom to attain a high enough VSG, which prevents it from entering the saturation mode of operation during start-up. Figure 18 shows the PMOS connected in series with the output to act as an output disconnect during a fault condition. The Schottky diode from the VIN pin to the GATE pin is optional and helps turn off the PMOS quicker in the event of hard shorts. The resistor divider from VIN to the SHDN pin sets a UVLO of 4V for this application. Connecting the PMOS in series with the output offers certain advantages over connecting it in series with the input: • Since the load current is always less than the input current for a boost converter, the current rating of the PMOS goes down. • A PMOS in series with the output can be biased with a higher overdrive voltage than a PMOS used in series with the input, since VOUT > VIN. This higher overdrive results in a lower RDSON rating for the PMOS, thereby improving the efficiency of the regulator. In contrast, an input connected PMOS works as a simple hot-plug controller (covered in more detail in the Hot-Plug section). The input connected PMOS also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the LT3581 with other compatible ICs (see Figure 11). Table 7 shows a list of several discrete PMOS manufacturers. Consult the manufacturers for detailed information on their entire selection of PMOS devices. Table 7. Discrete PMOS Manufacturers Vishay Fairchild Semiconductor www.vishay.com www.fairchildsemi.com COMPENSATION – ADJUSTMENT To compensate the feedback loop of the LT3581, a series resistor-capacitor network in parallel with an optional single capacitor should be connected from the VC pin to GND. For most applications, choose a series capacitor in the range of 1nF to 10nF with 2.2nF being a good starting value. The optional parallel capacitor should range in value from 47pF to 160pF with 100pF being a good starting value. The compensation resistor, RC , is usually in the range of 5k to 50k with 10k being a good starting value. A good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor RC. With the series and parallel capacitors at 2.2nF and 100pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC can be 3581f  LT3581 appenDix found. Figures 15a to 15c illustrate this process for the circuit of Figure 18 with a load current stepped between 540mA and 800mA. Figure 15a shows the transient response with RC equal to 1k. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 15b, the value of RC is increased to 3k, which results in a more damped response. Figure 15c shows the results when RC is increased further to 10.5k. The transient response is nicely damped and the compensation procedure is complete. VOUT AC-COUPLED 500mV/DIV COMPENSATION – THEORY Like all other current mode switching regulators, the LT3581 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT3581: a fast current loop which does not require compensation, and a slower voltage loop which does. Standard Bode plot analysis can be used to understand and adjust the voltage feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 16 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier gmp and the current controlled current source (which converts IVIN to ηVIN/VOUT • IVIN). gmp acts as a current source where the peak input current, IVIN, is proportional to the VC voltage. η is the efficiency of the switching regulator and is typically about 80%. Note that the maximum output currents of the gmp and gma stages are finite. The output of the gmp stage is limited by the minimum switch current limit (see Electrical Specifications) and the output of the gma stage is nominally limited to about ±12μA. – gmp VOUT • VIN IL 1A/DIV 50µs/DIV 3581 F15a Figure 15a. Transient Response Shows Excessive Ringing VOUT AC-COUPLED 500mV/DIV IL 1A/DIV IVIN VOUT 1.215V REFERENCE R2 • IVIN 50µs/DIV 3581 F15b Figure 15b. Transient Response is Better VC VOUT AC-COUPLED 500mV/DIV CF RC CC RO IL 1A/DIV 50µs/DIV 3581 F15c Figure 15c. Transient Response is Well Damped Figure 16. Boost Converter Equivalent Model 3581f  + + gma RESR COUT CPL R1 RL – R2 FB 3581 F16 CC: COMPENSATION CAPACITOR COUT: OUTPUT CAPACITOR CPL: PHASE LEAD CAPACITOR CF: HIGH FREQUENCY FILTER CAPACITOR gma: TRANSCONDUCTOR AMPLIFIER INSIDE IC gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER RC: COMPENSATION RESISTOR RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOAD(MAX) RO: OUTPUT RESISTANCE OF gma R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK RESR: OUTPUT CAPACITOR ESR LT3581 appenDix From Figure 16, the DC gain, poles and zeros can be calculated as follows: DC Gain : (Breaking loop at FB pin) ∂V ∂I ∂V ∂V ADC = A OL (0) = C • VIN • OUT • FB = ∂VFB ∂VC ∂IVIN ∂VOUT   2 (gma • RO ) • gmp •  η • VVIN • R2L  • R 0.5R5R   1 + 0. 2 OUT 2 Output Pole : P1 = 2 • π • RL • COUT Error Amp Pole : P2 = 1 2 • π • RO + RC  • CC   Using the circuit in Figure 18 as an example, Table 8 shows the parameters used to generate the Bode plot shown in Figure 17. Table 8. Bode Plot Parameters PARAMETER RL COUT RESR RO CC CF CPL RC R1 R2 VREF VOUT VIN gma gmp L fOSC VALUE 14.5 9.4 1 305 1000 56 0 10.5 130 14.6 1.215 12 5 270 15.1 1.5 2 UNITS Ω µF mΩ kΩ pF pF pF kΩ kΩ kΩ V V V µmho mho µH MHz COMMENT Application Specific Application Specific Application Specific Not Adjustable Adjustable Optional/Adjustable Optional/Adjustable Adjustable Adjustable Not Adjustable Not Adjustable Application Specific Application Specific Not Adjustable Not Adjustable Application Specific Adjustable 1 Error Amp Zero : Z1 = 2 • π • RC • CC ESR Zero : Z2 = RHP Zero : Z3 = 1 2 • π • RESR • COUT VIN2 • RL fS 3 2 • π • VOUT • L 2 High Frequency Pole : P3 > Phase Lead Zero : Z 4 = GAIN (dB) 1 2 • π • R1• CPL 1 Phase Lead Pole : P4 = R2 R1• 2 •C 2• π • R2 PL R1+ 2 Error Amp Filter Pole : P5 = C 1 , CF < C RC • R O 10 2• π • • CF RC + R O From Figure 17, the phase is –130° when the gain reaches 0dB giving a phase margin of 50°. The crossover frequency is 17kHz, which is more than three times lower than the frequency of the RHP zero Z3 to achieve adequate phase margin. 170 150 130 110 90 70 50 30 10 –10 –30 10 100 1k 10k FREQUENCY (Hz) 100k 1M 3851 F17 0 –40 PHASE –80 –120 PHASE (DEG) –160 –180 –200 GAIN –240 –280 –320 –360 The current mode zero (Z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. Figure 17. Bode Plot for Example Boost Converter 3581f  LT3581 Typical applicaTions VIN 5V 18.7k 100k C1 4.7µF 10k 43.2k L1 1.5µH D1 C2 4.7µF FB GATE CLKOUT LT3581 GND VC SS 56pF 0.1µF 10.5k 1nF 3581 F18 M1 6.04k D2 VIN VOUT 12V 830mA SW1 SW2 VIN FAULT SHDN RT SYNC 130k C3 4.7µF C1: 4.7µF 16V, X7R, 1206 , C2, C3: 4.7µF 25V, X7R, 1206 , D1: DIODES INC. PD3S230H-7 D2: VISHAY MSS2P3 L1: SUMIDA CDR6D28MN-IR5 M1: VISHAY SILICONIX SI7123DN Figure 18. 2MHz, 5V to 12V, 830mA Boost Converter with Output Short Circuit Protection Transient Response with 430mA to 830mA to 430mA Load Step VOUT AC-COUPLED 1V/DIV IL 1A/DIV VOUT AC-COUPLED 200mV/DIV IL 1A/DIV VSW 0.5A/DIV VCLKOUT (BW LIMIT) 2V/DIV 50µs/DIV 3581 TA02a Switching Waveforms with 830mA Load LOAD 0.5A/DIV 500ns/DIV 3581 TA02b 2MHz, 5V, 1.1A Boost Converter Operates from an Input Range of 2.8V to 4.2V VIN 2.8V TO 4.2V L1 0.68µH D1 VOUT 5V 1.1A Efficiency and Power Loss at VIN = 3.3V 90 85 2000 1800 1600 1400 1200 1000 800 600 400 200 0 200 600 800 400 LOAD CURRENT (mA) 1000 0 1200 POWER LOSS (mW) SW1 SW2 C1 3.3µF VIN 100k FAULT SHDN RT 43.2k SYNC GND FB LT3581 GATE CLKOUT VC SS 68pF 0.1µF 6.98k 1.5nF 3581 TA03a 45.3k EFFICIENCY (%) C2 22µF 80 75 70 65 60 55 50 C1: 3.3µF 16V, X7R, 1206 , C2: 22µF 16V, X7R, 1210 , D1: DIODES INC. PD3S230H-7 L1: VISHAY IHLP1616 BZ-01-OR68 (ONLY 4.1mm 4.5mm 2mm) 3581 TA03b 3581f  LT3581 Typical applicaTions High Efficiency, VFD (Vacuum Fluorescent Display) Power Supply Switches at 2MHz to Avoid AM Band DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY D6 D5 C5 2.2µF D4 D3 D7 L1 10µH C4 2.2µF D2 D1 C2 2.2µF FB GATE CLKOUT LT3581 GND VC SS 0.47µF 100pF 24k 1nF 3581 TA04a C7 2.2µF VOUT2 97V 90mA (VIN = 9V) 140mA (VIN = 12V) 180mA (VIN = 16V) VOUT1 65V 60mA (VIN = 9V) 70mA (VIN = 12V) 90mA (VIN = 16V) C6 2.2µF VIN 9V TO 16V C1 2.2µF 32.6k M1* SW1 SW2 VIN 100k FAULT SHDN RT SYNC 8.06k D9* 10V D8* VIN 365k 10k 43.2k C3 2.2µF C1: 2.2µF 25V, X7R, 1206 , C2 TO C7: 2.2µF 50V, X7R, 1206 , D1 TO D7: CENTRAL SEMI SOD123F D8: CENTRAL SEMI CMDSH-3TR D9: CENTRAL SEMI CMHZ5240B-LTZ L1: TAIYO YUDEN NR6045T100M M1: VISHAY SILICONIX SI7611DN *OPTIONAL, FOR OUTPUT SHORT-CIRCUIT PROTECTION Transient Response with 60mA to 140mA to 60mA Load Step on VOUT2 (VIN = 12V) VOUT AC-COUPLED 2V/DIV IL 0.5A/DIV VOUT2 50V/DIV VOUT1 50V/DIV IL 0.5A/DIV VSS 1V/DIV 100µs/DIV 3581 TA04b Start-Up Waveforms ILOAD 0.1A/DIV 100ms/DIV 3581 TA04c Efficiency and Power Loss at VIN = 12V 90 3.0 85 EFFICIENCY (%) 2.5 POWER LOSS (mW) 80 2.0 75 1.5 70 0 4 12 16 8 TOTAL OUTPUT POWER (W) 20 3581 TA04d 1.0 3581f  LT3581 Typical applicaTions 2MHz, 12V SEPIC Converter Can Accept Input Voltages from 9V to 16V VIN 9V TO 16V L1 3.3µH C2 2.2µF D1 VOUT 12V 1A (VIN = 9V) 1.1A (VIN = 12V) 1.3A (VIN = 16V) • VIN C1 3.3µF 100k SHDN FAULT RT 43.2k SYNC LT3581 FB GATE CLKOUT VC SS GND 100pF 0.1µF 10k 2.2nF 3581 TA06a C1: 3.3µF 25V, X7R, 1206 , C2: 2.2µF 50V, X7R, 1206 , C3: 10µF 25V, X7R, 1210 , D1: CENTRAL SEMI CTLSH2-40M832 L1, L2: COILCRAFT MSD7342-332MLB Efficiency 100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 300 1200 600 900 LOAD CURRENT (mA) 1500 3581 TA06b VIN = 9V VOUT (V) VIN = 16V VIN = 12V 11.996 Load Regulation at VIN = 12 12.01 LOAD REGULATION ~0.25%/A 12.00 VOUT (V) 11.99 11.98 11.97 11.96 0 200 400 600 800 1000 1200 1400 ILOAD (mA) 3581 TA06d 0 • 130k C3 10µF SW1 SW2 L2 3.3µH Line Regulation with No Load 12.000 LINE REGULATION ~0.0044%/V 11.998 11.994 11.992 11.990 8 9 10 11 12 13 VIN (V) 14 15 16 17 3581 TA06c 3581f LT3581 Typical applicaTions Wide Input Range, 3.3V SEPIC Converter Can Operate from 3V to 36V L1 3.3µH D3 C4 2.2µF VBAT 3V TO 36V (VBAT AT START-UP = 6V TO 16V) D2 200k C1 10µF SW1 M1 VIN 100k C3 4.7µF SHDN FAULT RT SYNC SW2 FB GATE VC SS CLKOUT GND 10k 10k LT3581 24.9k C5 47µF 2 10k 2.2nF D1 18V C2 10nF 47pF 1µF 174k Q1 C1: 10µF 50V, X7R, 1210 , C2: 10nF 25V, X7R, 0603 , C3: 4.7µF 25V, X7R, 1206 , C4: 2.2µF 50V, X7R, 1206 , C5: 47µF 10V, X7R, 1210 , D1: CENTRAL SEMI CMHZ5248B-LTZ D2: CENTRAL SEMI CMMSH2-40 D3: DIODES INC. PD3S230H-7 L1, L2: COILCRAFT MSD7342-332MLB M1: 2N7002 Q1: MMBT3904 Efficiency 80 VBAT = 9V 75 EFFICIENCY (%) 70 65 60 55 50 VBAT = 12V Wide Input Range SEPIC Can Ride Through VBAT Voltages that Are Higher than VIN_OVP VBAT 10V/DIV VOUT 2V/DIV VBAT = 17V VBAT = 31V VOUT = 3.3V VBAT = 3V IL 2A/DIV 3581 TA07c 0 800 1200 400 LOAD CURRENT (mA) 1600 3581 TA07b • 470pF L2 3.3µH VOUT 3.3V 0.9A (3V < VBAT < 9V) 1.5A (VBAT = 9V) • 3581 TA07a 1s/DIV 3581f  LT3581 Typical applicaTions 1MHz, ±12V Charge Pump Topology Uses Only Single Inductor C3 1µF D4 L1 8.2µH D1 C2 1µF D2 SW1 VIN C1 3.3µF 100k SHDN FAULT RT 86.6k SYNC GND SW2 FB GATE CLKOUT VC SS 100pF 0.1µF 16.9k 2.2nF 3581 TA08a D5 C5 10µF VOUT– –12V 0.27A VOUT+ 12V 0.27A EFFICIENCY (%) Efficiency and Power Loss with Symmetric Load 90 85 80 75 70 65 60 55 50 0 50 150 100 200 LOAD CURRENT (mA) 250 1800 1600 1400 POWER LOSS (mW) 1200 1000 800 600 400 200 0 300 VIN 5V D3 R1 *2.4k LT3581 130k C4 10µF 3581 TA08b C1: 3.3µF 25V, X7R, 1206 , C2, C3: 1µF 25V, X7R, 1206 , C4, C5: 10µF 50V, X7R, 1210 , D1 TO D5: DIODES INC. PD3S230H-7 L1: VISHAY IHLP-2525CZ-01-8R2 R1: 2.4k, 2W *IF DRIVING ASYMMMETRICAL LOADS, PLACE A 2.4k, 2W RESISTOR FROM THE 12V OUTPUT TO THE –12V OUTPUT FOR IMPROVED LOAD REGULATION OF THE –12V OUTPUT 700kHz, –5V Inverting Converter Can Accept Input Voltages from 3V to 16V VIN 3V TO 16V L1 3.3µH C2 1µF L2 3.3µH Efficiency VOUT –5V 0.9A (VIN = 3.3V) 1.5A (VIN = 12V) 1.6A (VIN = 16V) EFFICIENCY (%) 90 85 80 75 70 65 60 55 50 0 300 600 900 1200 LOAD CURRENT (mA) 1500 1800 VIN = 16V VIN = 3.3V VIN = 12V • • D1 SW1 VIN SW2 FB GATE CLKOUT VC SS GND 56pF 0.1µF 6.19k 2.2nF 3581 TA09a LT3581 C1 22µF 100k SHDN FAULT RT 60.4k C3 22µF 124k SYNC C1: 22µF 25V, X7R, 1210 , C2: 1µF 50V, X7R, 1206 , C3: 22µF 16V, X7R, 1210 , D1: VISHAY SSB44 L1, L2: COILCRAFT MSD7342-332MLB 3581 TA09b 3581f  LT3581 Typical applicaTions 700kHz, 5V SEPIC Can Accept Input Voltages from 3V to 16V VIN 3V TO 16V L1 3.3µH C2 1µF D1 VOUT 5V 0.9A (VIN = 3V) 1.5A (12V ≤ VIN ≤ 16V) Efficiency 90 85 80 EFFICIENCY (%) 75 70 65 60 55 50 0 400 800 1200 LOAD CURRENT (mA) 1600 3581 TA10b • VIN C1 22µF 100k SHDN FAULT RT 124k SYNC LT3581 FB GATE CLKOUT VC SS GND 100pF 1µF 7.87k 2.2nF 3581 TA10a C1: 22µF 25V, X7R, 1210 , C2: 1µF 50V, X7R, 1206 , C3: 22µF 16V, X7R, 1210 , D1: DIODES INC. B230LA L1, L2: COILCRAFT MSD7342-332MLB • 45.3k C3 22µF 2 SW1 SW2 L2 3.3µH VIN = 3.3V VIN = 12V VIN = 16V 3581f  LT3581 package DescripTion MSE Package 16-Lead Plastic MSOP Exposed Die Pad , (Reference LTC DWG # 05-08-1667 Rev A) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 (.112 0.102 .004) 0.889 (.035 0.127 .005) 2.845 (.112 1 0.102 .004) 8 0.35 REF 5.23 (.206) MIN 1.651 (.065 0.102 3.20 – 3.45 .004) (.126 – .136) 0.305 0.038 (.0120 .0015) TYP 0.50 (.0197) BSC 16 4.039 0.102 (.159 .004) (NOTE 3) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE 0.280 0.076 (.011 .003) REF 1.651 (.065 0.102 .004) 0.12 REF RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 0 – 6 TYP 16151413121110 9 0.254 (.010) GAUGE PLANE 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.53 0.152 (.021 .006) DETAIL “A” 0.18 (.007) 1.10 (.043) MAX 12345678 0.86 (.034) REF SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MSE16) 0608 REV A 3581f  LT3581 package DescripTion (Reference LTC DWG # 05-08-1708 Rev B) 4.00 0.10 (2 SIDES) 0.70 0.05 3.60 0.05 2.20 0.05 1.70 3.30 0.05 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.00 – 0.05 PIN 1 TOP MARK (SEE NOTE 6) 7 0.200 REF 0.75 0.05 3.00 REF BOTTOM VIEW—EXPOSED PAD R = 0.05 TYP 3.00 0.10 (2 SIDES) 8 R = 0.115 TYP 0.40 14 0.10 DE Package 14-Lead Plastic DFN (4mm × 3mm) 3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER 1 0.25 0.05 0.50 BSC (DE14) DFN 0806 REV B NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3581f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LT3581 Typical applicaTion 5V to –12V Inverting Converter Switches at 2MHz VIN 5V L1 3.3µH C2 1µF L2 3.3µH Efficiency and Power Loss VOUT –12V 625mA 90 85 80 EFFICIENCY (%) 2000 1800 1600 1400 1200 1000 800 600 400 200 0 125 375 500 250 LOAD CURRENT (mA) 0 625 3581 TA05b • • D1 SW1 SW2 VIN LT3581 FB GATE CLKOUT VC SS GND 47pF 0.1µF 11k 1nF 3581 TA05a POWER LOSS (mW) C1 3.3µF 100k SHDN FAULT RT 143k C3 4.7µF 75 70 65 60 55 50 43.2k SYNC C1: 3.3µF 16V, X7R, 1206 , C2: 1µF 25V, X7R, 1206 , C3: 4.7µF 25V, X7R, 1206 , D1: DIODES INC. PD3S230H-7 L1, L2: COILCRAFT MSD7342-332MLB relaTeD parTs PART NUMBER LT3580 LT3471 LT3479 LT3477 DESCRIPTION 2A (ISW), 2.5MHz, High Efficiency Step-Up DC/DC Converter Dual Output 1.3A (ISW), 1.2MHz, High Efficiency Step-Up DC/DC Converter 40V, 3A, Full Featured DC/DC Converter with Soft-Start and Inrush Current Protection 40V, 3A, Full Featured DC/DC Converter COMMENTS VIN = 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD < 1µA, 3mm × 3mm DFN-8, MSOP-8E Packages VIN = 2.4V to 16V, VOUT(MAX) = ±40V, IQ = 2.5mA, ISD < 1µA, 3mm × 3mm DFN-10 Package VIN = 2.5V to 24V, VOUT(MAX) = 40V, IQ = Analog/PWM, ISD < 1µA, DFN, TSSOP Packages VIN = 2.5V to 25V, VOUT(MAX) = 40V, IQ = Analog/PWM, ISD < 1µA, QFN, TSSOP-20E Packages VIN = 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1µA, MS8E Package VIN = 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1µA, ThinSOT Package VIN = 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1µA, ThinSOT Package VIN = 3V to 25V, VOUT(MAX) = 34V, IQ = 0.9mA, ISD < 6µA, TSSOP-16E Package LT1946/LT1946A 1.5A (ISW), 1.2MHz/2.7MHz, High Efficiency Step-Up DC/DC Converter LT1935 LT1310 LT3436 2A (ISW), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter 2A (ISW), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter 3A (ISW), 800kHz, 34V Step-Up DC/DC Converter 3581f  Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0310 • PRINTED IN USA www.linear.com  LINEAR TECHNOLOGY CORPORATION 2010