LT3640IFEPBF

Electrical Specifications Subject to Change FEATURES n LT3640 Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer DESCRIPTION The LT®3640 is a dual channel, current mode monolithic buck switching regulator with a power-on reset and a watchdog timer. Both regulators are synchronized to a single oscillator with an adjustable frequency (350kHz to 2.5MHz). At light loads, both regulators operate in low ripple Burst Mode® to maintain high efficiency and low output ripple. The high voltage channel is a nonsynchronous buck with an internal 2.4A top switch that operates from an input of 4V to 36V; a 38V OVLO protects the device to 55V. The low voltage channel operates from an input of 2.5V to 5.5V. Internal synchronous power switches provide high efficiency without the need of external Schottky diode. Both channels have cycle-by-cycle current limit, providing protection against shorted outputs. The power-on reset and watchdog timeout periods are both adjustable using external capacitors. The window mode watchdog timer flags when the μP pulses group too close together or too far apart. The LT3640 is available in a 28-pin 4mm × 5mm QFN package and 28-pin TSSOP package. Both packages have an exposed pad for low thermal resistance. n n n n n n n n n n High Voltage Buck Regulator: 4V to 36V Operating Range 1.3A Output Current OVLO Protects Input to 55V Low Voltage Synchronous Buck Regulator: 2.5V to 5.5V Input Voltage Range 1A Output Current Synchronizable, Adjustable 350kHz to 2.5MHz Switching Frequency Programmable Power-On Reset Timer Programmable Window Mode Watchdog Timer Quiescent Current: 275μA Short-Circuit Robust Programmable Soft-Start Low Shutdown Current: IQ < 1μA Available in Thermally Enhanced 28-Lead (4mm × 5mm) QFN and 28-Lead TSSOP Packages APPLICATIONS n n Industrial Power Supplies Automotive Electronic Control Units L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 2MHz 3.3V/0.8A and 1.8V/0.8A Step Down Regulators 0.22μF VIN 5V TO 34V 10μF EN/UVLO VIN SW SYNC PGOOD WDE VOUT1 100k 100k RST1 RST2 WDO WDI CWDT CPOR 1.5nF LT3640 VIN2 EN2 SW2 100k RT GND SS2 FB2 SS1 1nF 1nF 3640 TA01a HV Channel Efficiency, 2MHz, VOUT1 = 3.3V 90 90 LV Channel Efficiency, 2MHz, VOUT2 = 1.8V VIN2 = 3.3V 3.3μH BST SW1 DA FB1 80.6k VOUT1 3.3V/0.8A 22μF EFFICIENCY (%) 85 VIN = 12V EFFICIENCY (%) 0.2 0.4 0.6 0.8 1.0 VOUT1 CURRENT (A) 85 49.9k 80 80 10μF 1μH VOUT2 1.8V/0.8A 47μF μP 75 75 49.9k 70 0 1.2 3640 TA01b 70 0 0.2 0.4 0.6 VOUT2 CURRENT (A) 0.8 3640 TA01c 1.5nF 32.4k 1 3640p 1 LT3640 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN, EN/UVLO Voltage (Note 7) .................................55V WDE Voltage .............................................................30V BST Above SW, SW1 Voltage ....................... –0.3V to 6V SW1 Above SW Voltage ............................... –0.3V to 6V VIN2, SYNC, EN2, PGOOD, WDI, WDO, RST1, RST2, Voltages ....................... –0.3V to 6V SS1, SS2, FB1, FB2, RT, CWDT, CPOR Voltages………... ........................... –0.3V to 2.5V SW2 Voltage ................................ –0.3V to (VIN2 + 0.3V) DA Current ..................................................................2A Operating Junction Temperature Range (Note 2) LT3640E ................................................. –40°C to 125°C LT3640I .................................................. –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature, FE Only (Soldering, 10 sec) .... 300°C PIN CONFIGURATION TOP VIEW EN/UVLO PGOOD FB2 PGOOD EN/UVLO SYNC SS1 FB1 RT RST2 RST1 1 2 3 4 5 6 7 8 9 29 28 SS2 27 EN2 26 GND 25 SW2 24 VIN2 23 GND 22 VIN 21 BST 20 SW 19 SW1 18 DA 17 NC 16 GND 15 GND SYNC 1 SS1 2 FB1 3 RT 4 RST2 5 RST1 6 WDO 7 CWDT 8 9 10 11 12 13 14 WDE WDI GND GND CPOR NC 29 GND TOP VIEW GND 22 SW2 21 VIN2 20 GND 19 VIN 18 BST 17 SW 16 SW1 15 DA SS2 EN2 FB2 28 27 26 25 24 23 WDO 10 CWDT 11 CPOR 12 WDE 13 WDI 14 FE PACKAGE 28-LEAD PLASTIC TSSOP θJA = 30°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN θJA = 34°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LT3640EFE#PBF LT3640IFE#PBF LT3640EUFD#PBF LT3640IUFD#PBF TAPE AND REEL LT3640EFE#TRPBF LT3640IFE#TRPBF LT3640EUFD#TRPBF LT3640IUFD#TRPBF PART MARKING* LT3640FE LT3640FE 3640 3640 PACKAGE DESCRIPTION 28-Lead Plastic TSSOP 28-Lead Plastic TSSOP 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3640p 2 LT3640 ELECTRICAL CHARACTERISTICS PARAMETER VIN Undervoltage Lockout Threshold VIN Undervoltage Release Threshold VIN Overvoltage Lockout Threshold VIN Overvoltage Release Threshold Quiescent Current from VIN EN/UVLO Threshold Voltage EN/UVLO High Bias Current EN/UVLO Low Bias Current SYNC Input Frequency SYNC Threshold Voltage Switching Frequency FB1 Voltage FB1 Bias Current FB1 Line Regulation SW1 Minimum Off-Time SW1 VCESAT SW1 Leakage Current SW1 Current Limit DA Current limit BST Pin Current Minimum BST-SW Voltage ΔFB1 to Start LV Channel ΔFB1 Hysteresis to Stop LV Channel VIN2 Minimum Operating Voltage VIN2 Maximum Operating Voltage EN2 Threshold Voltage FB2 Voltage FB2 Bias Current FB2 Line Regulation SW2 Minimum Off-Time SW2 PMOS Current Limit SW2 NMOS Current Limit SW2 PMOS RDS(ON) SW2 NMOS RDS(ON) ΔFB2 to Enable PGOOD ΔFB2 Hysteresis to Disable PGOOD PGOOD Voltage FB2 = 0.6V, IPGOOD = 1mA (Note 5) (Note 5) ISW2 = 0.5A (Note 6) ISW2 = 0.5A (Note 6) 20 20 l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted. CONDITIONS l l l l MIN TYP 3.6 3.8 MAX 4 4.2 38 37 1 375 1.3 UNITS V V V V μA μA V μA μA 35 34 36.5 35.5 0.1 275 EN/UVLO = 0.3V Not Switching 1.2 EN/UVLO = Threshold + 60mV EN/UVLO = Threshold – 60mV 0.35 0.4 RT = 32.4k RT = 182k FB1 = 1.265V 5V < VIN < 30V ISW1 = 800mA FB1 = 1V (Note 3) FB1 = 0.1V FB1 = 1V (Note 4) FB1 = 0.1V ISW1 = 800mA 80 30 l l l l l 1.26 2 0.1 2.5 0.8 2 500 1.265 30 0.001 70 400 0.1 1 3.3 1.7 50 2.7 130 90 2.5 5.5 1.5 612 100 1 2.35 550 1.29 100 MHz V MHz kHz V nA %/V ns mV μA A A A A mA V mV mV V V V mV nA %/V ns 1.75 450 1.24 2.2 1.1 2.8 1.8 1.35 0.8 30 2 100 50 2.3 0.3 588 FB2 = 0.6V 2.5V < VIN2 < 5.5V 1.5 0.9 1 600 0 0.01 70 1.9 1.1 275 200 40 40 200 2.2 1.3 A A mΩ mΩ 80 80 320 mV mV mV 3640p 3 LT3640 ELECTRICAL CHARACTERISTICS PARAMETER SS1, SS2 Charge Current SS1 to FB1 Offset Voltage SS2 to FB2 Offset Voltage RST1 Threshold as Percentage of VFB RST2 Threshold as Percentage of VFB Undervoltage to RST Assert Time RST1, RST2, WDO Pull-Up Current RST1, RST2, WDO Output Voltage RST1, RST2 Timeout Period (tRST) Watchdog Start Delay Time (tDLY) Watchdog Upper Boundary (tWDU) Watchdog Lower Boundary (tWDL) WDI Pull-Up Current WDI Voltage Threshold WDI Low Minimum Pulse Width WDI High Minimum Pulse Width WDE Pull-Down Current WDE Threshold Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3640E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3640I is guaranteed and tested over the full –40°C to 125°C operating junction temperature range. WDE = 2V l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted. CONDITIONS SS1 = 0.5V, SS2 = 0.5V SS1 = 0.6V SS2 = 0.3V l l MIN 1.4 TYP 1.9 5 5 MAX 2.5 30 30 94 94 30 250 11 18 35 2.2 1.15 UNITS μA mV mV % % μs μA mV ms ms ms ms μA V ns ns 90 89 5 92 92 20 15 150 9.5 16 32 2 2 0.85 RST1, RST2, WDO = 0V IRST1, IRST2, IWDO = 2mA CPOR = 220pF CWDT = 820pF CWDT = 820pF CWDT = 820pF WDI = 1.2V l l l 8 14 27 1.68 0.55 300 300 1 0.5 0.7 0.9 μA V Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycle. Note 4: The oscillator cycle is extended when DA current exceeds its limit. DA current limit is flat over duty cycle. Note 5: If the SW2 NMOS current exceeds its limit at the start of an oscillator cycle, the PMOS will not be turned on in the cycle. Note 6: The QFN switch RDS(ON) is guaranteed by correlation to wafer level measurement. Note 7: Absolute maximum voltage at VIN and RUN/SS pin is 55V for nonrepetitive one second transients, and 36V for continuous operation. 3640p 4 LT3640 TYPICAL PERFORMANCE CHARACTERISTICS HV Channel Efficiency (2MHz, VOUT1 = 3.3V) 90 90 TA = 25°C, unless otherwise noted. LV Channel Efficiency (2MHz, VOUT2 = 1.2V) HV Channel Efficiency (2MHz, VOUT1 = 5V) VIN = 12V 90 85 EFFICIENCY (%) VIN = 16V 80 VIN = 24V 75 VIN = 12V EFFICIENCY (%) 85 VIN = 16V EFFICIENCY (%) VIN = 24V 80 85 VIN2 = 3.3V 80 VIN2 = 5V 75 75 70 0 0.2 0.4 0.6 0.8 1.0 VOUT1 CURRENT (A) 1.2 3640 G01 70 0 0.2 0.4 0.6 0.8 1.0 VOUT1 CURRENT (A) 1.2 3640 G02 70 0 0.2 0.4 0.6 VOUT2 CURRENT (A) 0.8 1.0 3640 G03 LV Channel Efficiency (2MHz, VOUT2 = 1.8V) 90 VIN QUIESCENT CURRENT (mA) VIN2 = 3.3V 85 EFFICIENCY (%) VIN2 = 5V 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 0.2 0.4 0.6 VOUT2 CURRENT (A) 0.8 1.0 3640 G04 Quiescent Current vs VIN 350 VIN QUIESCENT CURRENT (μA) 20 VIN VOLTAGE (V) 3640 G05 Quiescent Current vs Temperature 300 250 200 150 100 50 0 –50 80 75 70 0 10 30 40 0 50 100 150 3640 G06 TEMPERATURE (°C) FB1 Voltage vs Temperature 1.40 1.35 1.30 FB1 VOLTAGE (V) 1.25 1.20 1.15 1.10 1.05 1.00 –50 0 50 100 150 3640 G07 FB1 Voltage vs SS1 1.4 1.2 0.65 FB1 VOLTAGE (V) FB2 VOLTAGE (V) 0.70 FB2 Voltage vs Temperature REGULATION 1.0 0.8 0.6 0.4 0.60 REGULATION RST1 THRESHOLD 0.55 RST2 THRESHOLD 0.50 0.2 0.0 0 0.5 1.0 SS1 VOLTAGE (V) 3640 G08 1.5 2.0 0.45 –50 0 50 100 150 3640 G09 TEMPERATURE (°C) TEMPERATURE (°C) 3640p 5 LT3640 TYPICAL PERFORMANCE CHARACTERISTICS FB2 Voltage vs SS2 700 SWITCHING FREQUENCY (MHz) 600 FB2 VOLTAGE (mV) 500 400 300 200 100 0 0 200 400 6000 800 1000 3640 G10 TA = 25°C, unless otherwise noted. HV Channel Current Limit vs Duty Cycle 2.5 SW1 PEAK CURRENT LIMIT (A) Switching Frequency vs Temperature 0.52 0.51 2.0 1.5 0.50 1.0 0.49 0.5 0.48 –50 0.0 0 50 100 150 3640 G11 0 20 40 60 80 100 3640 G12 SS2 VOLTAGE (mV) TEMPERATURE (°C) DUTY CYCLE (%) LV Channel Peak Current Limit vs Duty Cycle 2.0 SW2 PEAK CURRENT LIMIT (A) 450 400 LV Channel Switch Voltage Drop vs Current (VIN2 = 3.3V) 0.45 0.40 0.35 VOUT1 CURRENT (A) 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 3640 G14 VOUT1 Minimum Load to Run at Full Frequency (VOUT1 = 3.3V) 1.5 SW2 VOLTAGE DROP (mV) 350 300 250 200 150 100 50 NMOS PMOS 2.5MHz 2MHz 1.0 0.5 0.0 0 20 40 60 80 100 3640 G13 0 DUTY CYCLE (%) SW2 CURRENT (A) 0 5 10 15 20 25 30 3640 G15 VIN VOLTAGE (V) HV Channel Switching Frequency (VOUT1 = 3.3V) 2.5 SWITCHING FREQUENCY (MHz) SWITCHING FREQUENCY (MHz) VIN = 12V 2.5 LV Channel Switching Frequency (VOUT2 = 1.8V) VIN2 = 3.3V 2.0 2.0 1.5 VIN = 16V 1.5 VIN2 = 5V 1.0 1.0 VIN = 24V 0.5 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VOUT1 CURRENT (A) 3640 G16 0 0 0.2 0.4 0.6 0.8 1.0 3640 G17 VOUT2 CURRENT (A) 3640p 6 LT3640 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Full Frequency Waveforms SW1 10V/DIV SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV 200ns/DIV VIN2 = VOUT1 VIN1 = 12V VOUT1 = 3.3V/0.5A VOUT2 = 1.8V/0.5A 3640 G18 PFM Operation Waveforms WATCHDOG UPPER BOUNDARY PERIOD (ms) 180 160 140 120 100 80 60 40 20 0 0 Watchdog Upper Boundary Period vs CWDT IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV 200ns/DIV VIN2 = VOUT1 VIN1 = 12V VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA 3640 G19 1000 2000 3000 4000 5000 3640 G20 CWDT CAPACITANCE (pF) Watchdog Upper Boundary Period vs Temperature WATCHDOG UPPER BOUNDARY PERIOD (ms) 35 RST/ WDO PULL-UP CURRENT (μA) 0 50 100 150 3640 G21 RST/WDO Pull-Up Current 20 30 25 20 15 10 5 0 –50 15 10 5 0 0 1 1.5 0.5 RST/ WDO VOLTAGE (V) 3640 G22 2 TEMPERATURE (°C) 3640p 7 LT3640 PIN FUNCTIONS (FE/QFN) FB2 (Pin 1/Pin 26): The low voltage converter regulates the FB2 pin to 600mV. Connect the feedback resistor divider tap to this pin to set output voltage. PGOOD (Pin 2/Pin 27): Open-drain logic output that starts to sink current when FB2 is in regulation. EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut down the LT3640. The 1.26V threshold can function as an accurate undervoltage lockout, preventing the LT3640 from operating until VIN voltage has reached the programmed level. SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external clock signal synchronizes both converters to the applied frequency. The lowest external clock frequency should be 20% higher than the internal oscillator frequency. SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage externally between 0V and 1.265V, providing soft-start and tracking. Tie this pin 1.5V or higher to use the internal 1.265V reference. A capacitor to ground at this pin sets the ramp time to regulated output voltage for the high voltage converter. Use a resistor divider to track another supply. FB1 (Pin 6/Pin 3): The high voltage converter regulates the FB1 pin to 1.265V. Connect the feedback resistor divider tap to this pin to set output voltage. RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the internal oscillator frequency. RST2 (Pin 8/Pin 5): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor after FB2 goes above 550mV. RST1 (Pin 9/Pin 6): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor after FB1 goes above 1.165V. WDO (Pin 10/Pin 7): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor if WDE is enabled and WDI pin is not driven by an appropriate signal. CWDT (Pin 11/Pin 8): Connect a capacitor to ground at this pin to set watchdog timer. CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this pin to set the power-on reset timer and WDO output timer. WDE (Pin 13/Pin 10): Watchdog Enable Pin. WDI (Pin 14/Pin 11): The WDI pin receives watchdog signals from a microprocessor. GND (Pins 15, 16, 23, 26, Exposed Pad 29/Pins 12, 13, 20, 23, Exposed Pad 29): Ground. These pins must be soldered to PCB ground. NC (Pin 17/Pin 14): Not Connected. DA (Pin 18/Pin 15): The DA pin is used to sense the catch diode current for current limit and protection. Connect this pin to catch diode anode. SW1 (Pin 19/Pin 16): Output of the High Voltage Internal Power Switch. Connect this pin to the inductor and catch diode cathode. SW (Pin 20/Pin 17): The SW pin is used to charge the boost capacitor. Connect this pin to the boost capacitor. BST (Pin 21/Pin 18): The BST pin is used to provide a drive voltage, higher than VIN pin voltage, to the high voltage channel internal power switch. Connect an external boost diode to this pin. VIN (Pin 22/Pin 19): The VIN pin supplies current to the LT3640’s internal circuitry and to the high voltage channel internal power switch. This pin must be locally bypassed. VIN2 (Pin 24/Pin 21): The VIN2 pin supplies current to the internal power MOSFET of the low voltage converter and to the LT3640’s internal circuitry when VIN2 is above 3V. SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage Converter. Connect this pin to an inductor. EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin. Pull this pin below 0.3V to shut down the low voltage converter. Pull this pin above 1.5V to enable the low voltage converter. SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage externally between 0V and 0.6V, providing soft-start and tracking. Tie this pin 0.8V or higher to use the internal 0.6V reference. A capacitor to ground at this pin sets the ramp time to regulated output voltage for the low voltage converter. Use a resistor divider to track another supply. 3640p 8 LT3640 BLOCK DIAGRAM CIN VIN 2μA DBST BST EN/ UVLO 100k 5.5V + A4 – ENABLE – A3 + CBST R S Q DRIVER Q1 SW VREF 1.265V 2μA SS1 A1 + – SW1 L1 D1 COUT1 VOUT1 DA + – + + – –+ A8 gm1 VC1 RAMP GENERATOR OSCILLATOR – A2 + VOUT1 R2 R1 FB1 RT SYNC A5 2μA SS2 + – VIN2 CIN2 + – + 50mV gm2 VC2 + A7 – R S Q LOGIC CIRCUIT SW2 L2 VOUT2 COUT2 VOUT2 R4 R3 FB2 + – –+ A9 VREF 600mV A6 – + PGOOD EN2 2μA CPOR POR TIMER RST1 RST2 WATCHDOG TIMER WDE WDI WDO 2μA CWDT 3640 BD 3640p 9 LT3640 TIMING DIAGRAMS Power-On Reset Timing FB RST tUV tRST Watchdog Timing WDI WDO t < tWDU tWDL < t < tWDU tDLY t < tWDL tRST tWDU tRST 3640 TD OPERATION The LT3640 is a dual channel, constant-frequency, current mode monolithic buck switching regulator with power-on reset and watchdog timer. Both channels are synchronized to a single oscillator with frequency set by RT. Operation can be best understood by referring to the Block Diagram. Buck Regulators The high voltage channel is a nonsynchronous buck regulator that operates from the VIN pin. The start of each oscillator cycle sets an SR latch and turns on the internal NPN power switch. An amplifier and comparator monitor the current flowing between the VIN and SW1 pins, turning the switch off when this current reaches a level determined by the voltage at VC1 node. An error amplifier measures the output voltage through an external resistor divider tied to the FB1 pin and servos the VC1 node. The reference of the error amplifier is determined by the lower of the internal reference and the voltage at the SS1 pin. If the error amplifier’s output increases, more current is delivered to the output; if it decreases, less current is delivered. An active clamp (not shown) on the VC1 node provides peak current limit. A DA pin current comparator extends the oscillator cycle until the catch diode current is below the valley current limit. Both the peak and valley current limits help to control the inductor current in fault conditions such as shorted output with high VIN. Both current limits are reduced when the voltage at the FB1 pin is below 0.2V. This current foldback helps to control the inductor current during start-up and overload. The NPN power switch driver operates from either the VIN pin or the BST pin. An external capacitor and diode are used to generate a voltage between the BST and SW pins. During the power-up of the LT3640, an internal 5mA current source charges the external BST capacitor. The regulator starts switching when the (BST-SW) voltage reaches the 2V threshold. The internal NPN power switch can be fully saturated for efficient operation when the (BST-SW) voltage is between 2.3V and 5.5V. The low voltage channel is a synchronous buck regulator that operates from the VIN2 pin. It starts switching only 3640p 10 LT3640 OPERATION when the VIN2 pin voltage is above 2.3V, the EN2 pin is pulled high and the FB1 pin voltage is above 1.165V. The internal top power MOSFET is turned on each cycle at the beginning of each oscillator cycle, and turned off when the current flowing through the top MOSFET reaches a level determined by the voltage at the VC2 node. An error amplifier measures the output voltage through an external resistor divider tied to the FB2 pin and servos the VC2 node. The reference of the error amplifier is determined by the lower of the internal 600mV reference and the voltage at the SS2 pin. While the top MOSFET is off, the bottom MOSFET is turned on in an oscillator cycle until the inductor current starts to reverse. If the inductor current is higher than the valley current limit at the beginning of an oscillator cycle, the top MOSFET will not turn on in this cycle, limiting inductor current in shorted output fault. An internal regulator provides power to the control circuitry. The regulator draws most power from the VIN2 pin and a small portion of power from the VIN pin when the VIN2 pin voltage is higher than 3V. If the voltage at VIN2 pin is lower than 3V, the regulator draws all power from the VIN pin. The EN/UVLO pin is used to put the LT3640 in shutdown, reducing the input current to less than 1μA. The accurate 1.26V threshold of the EN/UVLO pin provides a programmable VIN undervoltage lockout through an external resistor divider tied to the EN/UVLO pin. A 2μA hysteresis current on the EN/UVLO pin prevents switching noise from shutting down the LT3640. The LT3640 has an overvoltage protection feature which disables switching action in both channels when the VIN pin voltage goes above 36V. When switching is disabled, the LT3640 can sustain VIN voltages up to 55V for one second. Internal 2μA current sources charge the SS1 pin and the SS2 pin up to about 2V. Soft-start or output voltage tracking of the two channels can be independently implemented with capacitors from the SS1 pin and the SS2 pin to ground. Any overvoltage or undervoltage condition on the VIN pin triggers an internal latch that discharges the SS1 pin to below 100mV before it is released. If the EN2 pin goes low, the VIN2 voltage falls below 2.2V or the FB1 pin goes below 1.165V, the SS2 pin will be discharged to below 100mV before it is released. To optimize efficiency, the LT3640 switches to low ripple Burst Mode operation in light load situations. Between switching pulses, control-circuitry current is minimized. A power good comparator with 40mV of hysteresis trips when the low voltage channel is enabled and the FB2 pin is above 550mV. The PGOOD pin is an open-drain output that is pulled low when both the outputs are in regulation. Power-On Reset and Watchdog Timer The LT3640 includes one power-on reset timer for each buck regulator and one common watchdog timer. Poweron reset and watchdog timers are both adjustable using external capacitors. Operation can be best understood by referring to the Timing Diagram. The RST1, RST2 and WDO pins are all open-drain outputs with weak internal pull-ups to about 2V. The RST1 and RST2 pins are pulled low when the LT3640 is enabled and VIN is above 3.6V. Once the FB1 pin rises above 1.165V, the high voltage channel reset timer is started and RST1 is released after the reset timeout period. The low voltage channel reset timer is started once the FB2 pin rises above 550mV, and releases RST2 after the reset timeout period. The watchdog circuit monitors a μP’s activity. As soon as both RST1 and RST2 are released, a delay timer is started. The watchdog timer is started after the delay timer times out. The LT3640 implements windowed watchdog function for higher system reliability. The watchdog timer detects falling edges on the WDI pin. If the falling edges are grouped too close together or too far apart, the WDO pin is pulled down and the reset timer is started. When the reset timer times out, WDO is released and the watchdog timer is again started after the delay period. 3640p 11 LT3640 APPLICATIONS INFORMATION Setting the Output Voltages The internal reference voltage is 1.265V for the high voltage channel, and 600mV for the low voltage channel. The output voltages are set by resistor dividers according to the following formulas: ⎛V ⎞ R2 = R1 • ⎜ OUT1 − 1⎟ ⎝ 1 . 265V ⎠ ⎛V ⎞ R4 = R3 • ⎜ OUT2 − 1⎟ ⎝ 0 . 6V ⎠ Use 1% resistors in the resistor dividers. To avoid noise problems, R1 should be 100k or less, and R3 should be 50k or less. Reference designators refer to the Block Diagram. Switching Frequency The LT3640 uses a constant-frequency PWM architecture that can be programmed to switch from 350kHz to 2.2MHz by using a resistor tied from the RT pin to ground. Table 1 shows the necessary RT value for a desired switching frequency. Table 1. Switching Frequency vs RT Value SWITCHING FREQUENCY (MHz) 0.35 0.5 1 2 2.2 RT (k) 267 182 82.5 32.4 27.4 off for a minimum of ~70ns. The minimum and maximum duty cycles are: DCMIN = fS • tON(MIN) DCMAX = 1 – fS • tOFF(MIN) where fS is the switching frequency, tON(MIN) is the minimum switch on-time, and tOFF(MIN) is the minimum switch off-time. These equations illustrate how duty cycle range increases when switching frequency decreases. The internal oscillator of the LT3640 can be synchronized to an external 350kHz to 2.5MHz positive clock signal on the SYNC pin. The RT value should be chosen such that the internal oscillator’s frequency is 20% lower than the lowest SYNC clock frequency (refer to Table 1). To avoid erratic operation, the LT3640 ignores the SYNC signal until the FB1 pin voltage is above 1.165V. When applying a SYNC signal, the rising edges reset the LT3640’s internal clock and initiate a switch cycle. The amplitude of the SYNC signal must be at least 2V. The SYNC pulse width must be at least 40ns. VIN Voltage Range The LT3640’s minimum operating voltage is 3.6V. A higher minimum operating voltage can be accurately programmed with a resistor divider between the VIN pin and the EN/UVLO pin. The EN/UVLO threshold is 1.26V. When the LT3640 is enabled, a 2μA current flows out of the EN/UVLO pin generating hysteresis to prevent the switching action from falsely disabling the LT3640. Choose the divider resistances for appropriate hysteresis voltage. The high voltage nonsynchronous channel operates from the VIN pin. The minimum VIN voltage to regulate output voltage is: ⎛V +V ⎞ VIN(MIN) = ⎜ OUT1 D ⎟ − VD + VCE ⎝ DCMAX ⎠ Where VD is the forward voltage drop of the catch diode, VCE is the voltage drop of the internal NPN power switch, and DCMAX is the maximum duty cycle (refer to the Switching Frequency section). If VIN is below the calculated minimum voltage, output will lose regulation. 3640p Selection of the operating frequency is mainly a trade-off between efficiency and component size. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. The disadvantage is lower efficiency. The high switching frequency also decreases the duty cycle range. The reason is that the LT3640 switches have finite minimum on- and off-times independent of the switching frequency. The top switch in the high voltage channel can turn on for a minimum of ~60ns and turn off for a minimum of ~70ns. The top switch in the low voltage channel can turn on for a minimum of ~110ns and turn 12 LT3640 APPLICATIONS INFORMATION The maximum VIN should not exceed the absolute maximum rating. For fixed frequency operation, the maximum VIN is: ⎛V +V ⎞ VIN(MAX ) = ⎜ OUT1 D ⎟ − VD + VCE ⎝ DCMIN ⎠ Note that the high voltage buck will still regulate at an input voltage that exceeds VIN(MAX) (up to 36V). However, the switching frequency will be lowered to satisfy the equation (Figure 1). Once the input voltage reaches 36V, an internal overvoltage lockout (OVLO) circuit is triggered to disable switching action (Figure 2). Without switching, the LT3640 can sustain VIN voltage transients up to 55V for one second. VIN2 Voltage Range The low voltage synchronous channel operates from the VIN2 pin. The VIN2 pin can be connected to either an independent voltage supply or the high voltage channel output for a two-stage power regulator. In either configuration, if the high voltage channel is overloaded and pulled out of regulation, the low voltage channel will be disabled. The SS2 pin will be discharged as well. The minimum VIN2 voltage to regulate output voltage is: VIN2(MIN) ≈ VOUT2 DCMAX calculated minimum voltage, the output will fall out of regulation. The maximum VIN2 for fixed frequency operation is: VIN2(MAX ) ≈ VOUT2 DCMIN Where DCMIN is the minimum duty cycle (refer to the Switching Frequency section). For voltage that exceeds VIN2(MAX) (up to 5.5V), the low voltage channel exhibits pulse-skipping behavior, and the output ripple will increase. Inductor Selection Inductor selection involves inductance, saturation current, series resistance (DCR) and magnetic loss. The inductor current ripple determines the inductance. A reasonable current ripple is around 30% of the maximum load current: ΔIL = 0.3 • IOUT(MAX) where IOUT(MAX) is the maximum load current. To guarantee sufficient output current, peak inductor current must be lower than the switch current limit (ILIM). The peak inductor current is: IL(PEAK ) = IOUT(MAX ) + Δ IL 2 Where DCMAX is the maximum duty cycle (refer to the Switching Frequency section). If VIN2 is below the where IL(PEAK) is the peak inductor current. For the high voltage channel, the top switch current limit is at least 2.4A at low duty cycles and decreases linearly to 1.8A at DC = 0.8. Be sure to pick an inductor ripple current that provides sufficient maximum load current IOUT(MAX). Once IL1 2A/DIV SW1 10V/DIV IL1 0.5A/DIV 200ns/DIV VIN = 30V VOUT1 = 3.3V/0.2A RT SET = 2MHz 3640 F01 VIN 20V/DIV 55VPK, 40V, 15V 10μs/DIV 3640 F02 Figure 2. VIN Overvoltage Lockout 3640p Figure 1. Lower Switching Frequency Occurs in High Voltage Channel When Required On-Time Is Below 50ns 13 LT3640 APPLICATIONS INFORMATION the ripple current is determined, the inductance for the high voltage channel is: ⎛ VOUT1 + VD ⎞ ⎜ 1− ⎟ VIN ⎝ ⎠ Δ IL1 • fS Of course, such a simple design guide will not always result in the optimum inductors for the applications. A larger value inductor provides a slightly higher maximum load current and will reduce the output voltage ripple. A larger value inductor also results in higher efficiency in the condition of same DCR and same magnetic loss. However, for a same series of inductors, a larger value inductor has higher DCR. The trade-off between inductance and DCR is not always obvious. Use experiments to find optimum inductors. Low inductance may result in discontinuous mode operation, which is okay, but reduces maximum load current. For details of maximum output current and discontinuous mode operation, see the Linear Technology Application Note 44. For duty cycles greater than 50%, there is a minimum inductance required to avoid subharmonic oscillations. See the Linear Technology Application Note 19. Input Capacitors Bypass the VIN and VIN2 pins of the LT3640 with a ceramic capacitor of X7R or X5R type. Y5V types have poor performance over temperature and applied voltage, and should not be used. Buck converters draw pulse current from the input supply. The input capacitor is required to reduce the resulting voltage ripple: ⎛ ⎞ V IL Δ VIN ≈ VOUT • ⎜ 1 − OUT ⎟ • VIN ⎠ ( VIN • CIN • fS ) ⎝ +ES RCIN • IL where CIN is the input capacitance, ESRCIN is the series resistance (ESR) of the input capacitor, and IL is the inductor current. The input voltage ripple ΔVIN usually should not exceed 100mV. The above equation can be used to estimate the input capacitance for both channels. The input capacitors need to be placed close to the LT3640 (see the PCB Layout section). A second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3640. A ceramic input capacitor combined with trace or cable inductance forms a under damped tank circuit. If the LT3640 circuit is plugged into a live supply, the input voltage can 3640p L1 ≈ ( VOUT1 + VD ) • The largest inductor current ripple occurs at the highest VIN. To guarantee current capacity, use VIN(MAX) in the above formula. For the low voltage channel, the top MOSFET current limit is at least 1.5A at low duty cycle and decreases linearly to 1.2A at DC = 0.8. Pick an inductor ripple current (ΔIL2) following the same principle as the high voltage channel. The inductance for the low voltage channel is: ⎛ VOUT2 ⎞ ⎜ 1− V ⎟ ⎝ IN 2 ⎠ Δ IL2 • fS L2 ≈ ( VOUT2 ) • For robust operation in fault conditions, the inductor saturation current should be higher than the upper limit of the corresponding top switch current limit. For the high voltage channel, the inductor saturation current should be at least 3.5A. For the low voltage channel, the inductor saturation current should be at least 2.5A. To keep the efficiency high, the inductor series resistance (DCR) should be as small as possible (must be < 0.1Ω), and the core material should be intended for the chosen operation frequency. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores; instead use ferrite, molypermalloy or Kool Mμ cores. Table 2 lists several vendors and suitable inductor series. Table 2. Inductor Vendors PART SERIES LQH55D SLF7045 SLF10145 D62CB, D63CB D75C, D75F CR54, CDRH74 CDRH6D38, CR75 VENDOR Murata www.murata.com TDK www.componenttdk.com TOKO www.toko.com Sumida www.sumida.com 14 LT3640 APPLICATIONS INFORMATION ring to twice its nominal value, possibly exceeding the LT3640’s voltage rating. This situation can be easily avoided (see the Linear Technology Application Note 80). Output Capacitors and Output Ripple The output capacitor has two essential functions. In steady state, it determines the output voltage ripple. In transient, it stores energy in order to satisfy transient loads and stabilize the control loop. Ceramic capacitors have low equivalent series resistance (ESR) and provide the best ripple performance. A good starting value is: COUT 100 = VOUT • fS Table 3. Capacitor Vendors PART SERIES Ceramic, Polymer, Tantalum Ceramic, Tantalum Ceramic, Polymer, Tantalum Ceramic Ceramic, Tantalum Ceramic VENDOR Panasonic www.panasonic.com Kemet www.kemet.com Sanyo www.sanyovideo.com Murata www.murata.com AVX www.avxcorp.com Taiyo Yuden www.taiyo-yuden.com Catch Diode where fS is in MHz, and COUT is the recommended output capacitance in μF Use X5R or X7R types. This choice will . provide low output ripple and good transient response. The control loop is usually easier to be stabilized by a bigger value of output capacitor. This equation applies for both channels. In the case where VIN2 is connected to the high voltage channel output, the high voltage channel output capacitor can be combined with the low voltage channel input capacitor. The required VIN2 input capacitor value is usually smaller than the high voltage output capacitor. If the bigger output capacitor can be placed close to the VIN2 pin, an input capacitor is not necessary for the VIN2 pin. When choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions (applied voltage and temperature). A physically larger capacitor or one with a higher voltage rating may be required. High performance tantalum or electrolytic capacitors can be used for the output capacitor. Low ESR is important, so choose one that is intended for use in switching regulators. Table 3 lists several capacitor vendors. The high voltage channel requires an external catch diode to conduct current during switch off-time. Average forward current in normal operation can be calculated from: ID( AVG) = IOUT ( VIN − VOUT ) VIN where IOUT is the output load current. The only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of overloaded output. The diode current will then increase to the typical peak switch current. Peak reverse voltage is equal to the regulator input voltage. Use a diode with a reverse voltage rating greater than the input voltage. Table 4 lists several Schottky diodes and their manufacturers. Table 4. Diode Vendors PART NUMBER On Semiconductor MBRM120E MBRM140 Diodes Inc. B120 B130 B220 B230 DFLS240L International Rectifier 10BQ030 20BQ030 30 30 1 2 420 470 470 20 30 20 30 40 1 1 2 2 2 500 500 500 500 500 20 40 1 1 530 595 VR (V) IAVE (A) VF AT 1A (MV) VF AT 2A (MV) 3640p 15 LT3640 APPLICATIONS INFORMATION BST and SW Pin Considerations The high voltage channel requires an external capacitor between the BST and SW pins and an external boost diode from a voltage source to the BST pin. In most cases, a 0.22μF capacitor will work well. The (BST-SW) voltage cannot exceed 5.5V, and must be more than 2.3V for best efficiency. Connect the boost diode to any voltage between 2.5V and 5.5V. The VIN2 pin is the best choice if the low voltage channel is used. The high voltage channel will not start until the (BST-SW) voltage is 2V or above. When the LT3640 is enabled, an internal ~5mA current source from VIN flows out of the BST pin. The SW pin is disconnected from the SW1 pin, and is pulled down by an internal current source to ground. The external boost capacitor can be charged up regardless of the output. When the (BST-SW) voltage reaches 2V, the SW pin is connected to the SW1 pin, and the high voltage channel starts switching. However, the internal bipolar power switch cannot be fully saturated until the (BST-SW) voltage is further charged to above 2.3V. To start up a traditional nonsynchronous buck regulator with very light load, the input voltage needs to be a couple of volts higher than the minimum running input voltage if the input voltage is ramping up slowly. The LT3640’s unique boost capacitor charging scheme solves this start-up issue. Figure 3 shows that the minimum input voltage to start the high voltage channel nonsynchronous buck regulator of the LT3640 is 5 START 4 VIN VOLTAGE (V) RUN VIN VOLTAGE (V) 4 RUN 3 START very close to the minimum input voltage to regulate the output voltage for most of the load range. Soft-Start The LT3640 has a soft-start pin for each channel. The feedback pin voltage is regulated to the lower of the corresponding SS pin and the internal references, which is 1.265V for the high voltage channel, and 600mV for the low voltage channel. A capacitor from the SS pin to ground is charged by an internal 2μA current source resulting in an output ramping linearly from 0V to the regulated voltage. The duration of the ramp is: t SS1 = C SS1 • t SS2 = C SS2 • 1 . 265V 2 µA 600mV 2 µA where tSS1 is the ramping time for the SS1 pin, tSS2 is the ramping time for the SS2 pin, CSS1 is the capacitance from the SS1 pin to ground, and CSS2 is the capacitance from the SS2 pin to ground. At power-up, a latch is set to discharge the SS1 pin. After the SS1 pin is discharged to below 100mV, the latch is reset. The internal 2μA current source starts to charge the SS1 pin when the (BST-SW) voltage is charge to above 2V. 5 3 2 2 1 1 0 0.001 0.01 0.1 VOUT CURRENT (A) 1 3640 F03a 0 0.001 0.01 0.1 VOUT CURRENT (A) 1 3640 F03b (3a) FS = 2MHz (3b) FS = 500kHz Figure 3. High Voltage Channel Minimum Input Voltage for VOUT1 = 3.3V 3640p 16 LT3640 APPLICATIONS INFORMATION In the event of VIN undervoltage lockout, VIN overvoltage lockout or the EN/UVLO pin being driven below 1.26V, the soft-start latch is set, triggering a start-up sequence. A latch is set to discharge the SS2 pin at power-up. After the FB1 pin reaches 1.165V, the VIN2 voltage is above 2.3V, the EN2 pin is enabled, and the SS2 pin is below 100mV, the latch is reset. The internal 2μA current source starts to charge the SS2 pin. In the event of VFB1 out of regulation, the VIN2 pin falling below 2.2V, or the EN pin going low, the SS2 discharging latch is set, triggering a start-up sequence. The SS pins can also be pulled up by external current sources or resistors for output tracking. The external pullup current should not exceed 100μA for either SS pin. Figure 4 shows the soft-start for a 3.3V and 1.8V application. Shorted-Output Protection If an inductor is chosen that will not saturate excessively, the LT3640 will tolerate a shorted output. For the high voltage channel, the DA current comparator extends the internal oscillator period until the catch diode current is below its limit. Both the top switch and the DA comparator have current foldback to help limit load current when the output is shorted to ground. The DA current limit is 1.35A when the FB1 voltage is above 0.2V, and is 0.8A when the FB1 voltage is below 0.2V. Figure 5 shows the high voltage channel operation under shorted output. Because of the low VIN2 voltage, the low voltage channel does not have current foldback. The low voltage channel does not extend the internal oscillator in shorted output condition allowing the high voltage channel to operate in constant frequency. If the bottom MOSFET current exceeds 1.1A at the start of a clock cycle, the top MOSFET is kept off in this cycle (similar to pulse-skipping operation). The inductor valley current is kept below 1.1A to ensure robustness in shorted output condition (Figure 6). SW1 10V/DIV IL1 0.5A/DIV EN 2V/DIV VOUT1 2V/DIV VOUT2 1V/DIV PGOOD 2V/DIV 500μs/DIV VIN = 12V RT SET = 2MHz 3640 F04 Figure 4. Soft-Start of LT3640 1μs/DIV VIN = 30V VOUT1 = SHORT 3640 F05 Figure 5. The High Voltage Channel Reduces Frequency to Protect Against Shorted Output With 30V Input SW2 2V/DIV IL2 1A/DIV 1μs/DIV VIN2 = 5V VOUT2 = SHORT 3640 F06 Figure 6. The Low Voltage Channel Operates in Pulse-Skipping Mode to Protect Against Shorted Output 3640p 17 LT3640 APPLICATIONS INFORMATION Reverse Protection In battery charging applications or in battery back-up systems, the output will be held high when the input to the LT3640 is absent. If the VIN pin is floated and the LT3640 is enabled, the LT3640’s internal circuitry will pull its quiescent current through the SW1 pin or the SW2 pin. This is fine if the system can tolerate a few mA in this state. If the LT3640 is disabled, the SW1 pin and the SW2 pin current will drop to essentially zero. However, if the VIN pin is grounded while the high voltage channel output is held high, an external diode is required at the VIN pin to prevent current being pulled out of the VIN pin. If the VIN2 pin is grounded while the low voltage channel output is held high, an external diode is required at the VIN2 pin to prevent current being pulled out of the VIN2 pin (Figure 7). 0.1μF SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV 2μs/DIV VIN2 = VOUT1 VIN = 12V VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA 3640 F08a (8a) SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV IN VIN SW BST SW1 DA FB1 OUT1 EN/UVLO LT3640 + – IL2 0.5A/DIV 2μs/DIV VIN2 = VOUT1 VIN = 12V VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA 3640 F08b SW2 IN2 VIN2 FB2 OUT2 (8b) + – SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV 2μs/DIV VIN2 = VOUT1 VIN = 12V VOUT1 = 3.3V/0mA VOUT2 = 1.8V/30mA 3640 F08c GND 3640 F07 Figure 7. Diodes Prevent Shorted Inputs from Discharging a Battery Tied to the Outputs PFM Operation To improve efficiency at light loads, the LT3640 automatically switches to pulse frequency modulation (PFM) operation which minimizes the switching loss and keeps the output voltage ripples small. Because the two channels of the LT3640 may have different loads, the two channels can have different switching frequency (Figure 8). Power-On Reset Timer Each channel of the LT3640 has a power-on comparator. Both comparators are enabled when the LT3640 is powered up and starts monitoring their corresponding feedback voltages. (8c) Figure 8. PFM Operation The threshold of power-on comparator is 1.15V for the high voltage channel, and 550mV for the low voltage channel. Both RST1 and RST2 are open-drain outputs with weak internal pull-ups (100k to ~2V). The DC characteristics of the RST1 and RST2 pull-down strength are shown in the Typical Performance Characteristics section. The weak 3640p 18 LT3640 APPLICATIONS INFORMATION pull-ups eliminate the need for external pull-ups when the rise time of these pins is not critical. The open-drain configuration allows wired-OR connections. The two power-on reset timers share one oscillator. The power-on reset timeout period, t RST (64 cycles on the CPOR pin), which is the same for the two channels, can be programmed by connecting a capacitor, CPOR, between the CPOR pin and ground: ⎛ s⎞ t RST = CPOR • 37 • 10 6 ⎜ ⎟ ⎝ F⎠ For example, using a capacitor value of 8.2nF gives a 303ms reset timeout period. The accuracy of t RST will be limited by the accuracy and temperature coefficient of the capacitor CPOR. Extra parasitic capacitance on the CPOR pin, such as probe capacitance, can affect t RST. Watchdog The WDE pin is the enable pin for the watchdog. As soon as both RST1 and RST2 are released, the watchdog starts a delay period, tDLY, during which the input signal at the WDI pin is ignored for higher reliability. After the delay period, the watchdog starts detecting falling edges on the WDI pin. If the time between any two WDI falling edges is shorter than the watchdog lower boundary, tWDL, or longer than the watchdog upper boundary, tWDU, the WDO pin is pulled down for a period of t RST, which is the same as the power-on reset timeout period. When the WDO pin is released, the watchdog again starts the delay period. The WDO is open-drain output with weak internal pull-up, similar to the RST pins. The delay period corresponding to 33 cycles on CWDT, the watchdog lower boundary (4 cycles on CWDT), and the watchdog upper boundary (64 cycles on CWDT) are all related and set by a capacitor, CWDT, between the CWDT pin and ground: ⎛ 33 ⎞ t DLY = t WDU • ⎜ ⎟ ⎝ 64 ⎠ t t WDL = WDU 16 The accuracy of the watchdog timer will be limited by the accuracy and temperature coefficient of the capacitor CWDT. Extra parasitic capacitance on the CWDT pin, such as probe capacitance, can affect the watchdog timer. CWDT CPOR WD STARTS 64 CYCLES 64 CYCLES FB2 FB1 RST1 RST2 20ms/DIV 3640 F09a (9a) CWDT CPOR WDI WDO 1ms/DIV 3640 F09b (9b) CWDT CPOR WDI WDO 50ms/DIV 3640 F09c (9c) Figure 9. Power-On Reset and Watchdog Timing ⎛ s⎞ t WDU = C WDT • 37 • 10 6 ⎜ ⎟ ⎝ F⎠ 3640p 19 LT3640 APPLICATIONS INFORMATION Figure 9a shows the power-on reset timing. Having FB1 or FB2 high starts the CPOR oscillator. After t RST, the corresponding RST is released. When both RST1 and RST2 are released, the CWDT oscillator starts. Figure 9b shows the watchdog waveform with the WDI period between tWDL and tWDU. The WDI falling edge resets the CWDT oscillator. The CPOR oscillator is disabled and WDO remains high. Figure 9c shows the watchdog waveform with the WDI period longer than tWDU. WDO is asserted for a period of t RST when the watchdog upper boundary, tWDU, expires. PCB Layout For proper operation and minimum EMI, care must be taken during the printed circuit board (PCB) layout. Figure 10 shows the recommended component placement with trace, ground plane and via locations. The input loop of the high voltage channel, which is formed by the VIN and SW1 pins, the external catch diode (D1), the input capacitor (CIN) and the ground, should be as small as possible. These external components should be placed on the same side of the circuit board as the LT3640, and their connections should be made on that layer. Place a local, unbroken ground plane below these components. The BST and SW nodes should be as small as possible. The boost capacitor (CBST) should be as close to the BST and SW pins as possible. The input loop of the low voltage channel is formed by the VIN2 pin, the input capacitor (CIN2) and the ground. Place CIN2 close to the VIN2 and the GND pin to minimize this loop. Place a local, unbroken ground plane below this input loop. Keep the FB1 and FB2 nodes small so that the ground traces will shield them from the switching nodes. The Exposed Pad on the bottom of the package must be soldered to the ground so that the pad acts as a heat sink. To keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3640 to additional ground planes within the circuit board and on the bottom side. COUT2 L2 CIN2 CIN CBST L1 COUT1 3640 F10 Figure 10. Recommended PCB Layout, FE28 Package 3640p 20 LT3640 TYPICAL APPLICATIONS 2MHz 3.3V/1.3A and 1.2V/1A Buck Regulators VIN 5V TO 34V 0.22μF 4.7μF 100k 301k L1 3.3μH VIN SW BST SW1 DA FB1 EN2 LT3640 VIN2 L2 1μH SW2 100k FB2 CPOR 1.5nF 1.5nF 32.4k 1nF 3640 TA02 D2 EN/UVLO D1 80.6k 49.9k VOUT1 3.3V/1.3A 10μF SYN WDE PGOOD RST1 RST2 WDO WDI L1: VISHAY IHLP-2020 L2: VISHAY IHLP-1616 D1: DIODES B240A D2: CENTRAL SEMI CMDSH-4E CWDT RT GND SS2 VIN2 2.5V TO 5.5V 4.7μF VOUT2 1.8V/1A 47μF SS1 1nF 49.9k 2MHz 5V/0.8A and 1.2V/1A Buck Regulators VIN 7V TO 34V 0.22μF 4.7μF 100k 453k L1 4.7μH VIN SW BST SW1 D1 SYN WDE WDI OUT1 100k 100k 100k L1: VISHAY IHLP-2020 L2: VISHAY IHLP-1616 D1: DIODES B240A D2: CENTRAL SEMI CMDSH-4E 100k WDI PGOOD WDO RST1 RST2 CWDT FB2 CPOR 1.5nF 1.5nF 32.4k 1nF 3640 TA03 D2 VOUT1 5V/0.8A 301k 100k 10μF EN/UVLO DA FB1 EN2 LT3640 VIN2 L2 1μH SW2 49.9k 10μF VOUT2 1.2V/1A 47μF RT GND SS2 SS1 1nF 49.9k 2MHz 2.5V/0.8A and 0.6V/1A Buck Regulators 0.22μF VIN 3.6V TO 25V 4.7μF EN/UVLO VIN SW BST SW1 D1 SYN WDE PGOOD RST1 RST2 WDO WDI L1: VISHAY IHLP-2020 L2: VISHAY IHLP-1616 D1: ON SEMI MBRS230 D2: CENTRAL SEMI CMDSH2-3 CWDT CPOR 1.5nF 1.5nF 32.4k 1nF 3640 TA04 D2 L1 3.3μH 100k 100k VOUT1 2.5V/0.8A 22μF DA FB1 EN2 LT3640 VIN2 L2 1μH SW2 FB2 RT GND SS2 SS1 1nF VOUT2 0.6V/1A 100μF 3640p 21 LT3640 PACKAGE DESCRIPTION FE Package 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation EB 4.75 (.187) 9.60 – 9.80* (.378 – .386) 4.75 (.187) 28 2726 25 24 23 22 21 20 19 18 1716 15 6.60 ± 0.10 4.50 ± 0.10 SEE NOTE 4 2.74 (.108) 0.45 ± 0.05 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 6.40 2.74 (.252) (.108) BSC 1.05 ± 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.20 (.047) MAX 0° – 8° 4.30 – 4.50* (.169 – .177) 0.25 REF 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE28 (EB) TSSOP 0204 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3640p 22 LT3640 PACKAGE DESCRIPTION UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ± 0.05 4.50 ± 0.05 3.10 ± 0.05 2.50 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 27 28 0.40 ± 0.10 1 2 5.00 ± 0.10 (2 SIDES) 2.50 REF R = 0.115 TYP PIN 1 TOP MARK (NOTE 6) 3.50 REF 3.65 ± 0.10 2.65 ± 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3640p Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT3640 TYPICAL APPLICATION 2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators 0.1μF VIN 4V TO 34V 4.7μF EN/UVLO VIN SW BST SW1 DA SYN WDE PGOOD RST1 RST2 WDO WDI CWDT CPOR 1.5nF 1.5nF 32.4k 1nF 3640 TA05 4.7μH 80.6k VOUT1 3.3V/0.8A 22μF FB1 EN2 LT3640 VIN2 1μH SW2 16.5k FB2 RT GND SS2 SS1 1nF 49.9k VOUT2 0.8V/1.2A 68μF 49.9k RELATED PARTS PART NUMBER LT1933 LT1936 LT1940 LT1976/LT1967 LT3434/LT3435 LT3437 LT3480 LT3481 LT3493 LT3505 LT3508 LT3680 LT3684 LT3685 LT3693 DESCRIPTION 500mA (IOUT), 500kHz Step-Down Switching Regulator in SOT-23 36V, 1.4A (IOUT), 500kHz, High Efficiency Step-Down DC/DC Converter Dual 25V, 1.4A (IOUT), 1.1MHz, High Efficiency Step-Down DC/DC Converter 60V, 1.2A (IOUT), 200kHz/500kHz, High Efficiency Step-Down DC/DC Converters with Burst Mode Operation 60V, 2.4A (IOUT), 200kHz/500kHz, High Efficiency Step-Down DC/DC Converters with Burst Mode Operation 60V, 400mA (IOUT), Micropower Step-Down DC/DC Converter with Burst Mode Operation 36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency Step-Down DC/DC Converter with Burst Mode Operation 34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency Step-Down DC/DC Converter with Burst Mode Operation 36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC Converter 36V with Transient Protection to 40V, 1.4A (IOUT), 3MHz, High Efficiency Step-Down DC/DC Converter 36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz, High Efficiency Step-Down DC/DC Converter 36V, 3.5A, 2.4MHz, Low Quiescent Current (