LT5568

FEATURES n n n n LTC5588-1 200MHz to 6000MHz Quadrature Modulator with Ultrahigh OIP3 DESCRIPTION The LTC®5588-1 is a direct conversion I/Q modulator designed for high performance wireless applications. It allows direct modulation of an RF signal using differential baseband I and Q signals. It supports LTE, GSM, EDGE, TD-SCDMA, CDMA, CDMA2000, W-CDMA, WiMax and other communication standards. It can also be configured as an image reject upconverting mixer, by applying 90° phase-shifted signals to the I and Q inputs. The I/Q baseband inputs drive double-balanced mixers. An onchip balun converts the differential mixer signals to a 50Ω single-ended RF output. Four balanced I and Q baseband input ports are DC-coupled with a common mode voltage level of 0.5V. The LO path consists of an LO buffer with single-ended or differential inputs and precision quadrature generators to drive the mixers. The supply voltage range is 3.15V to 3.45V. An external voltage can be applied to the LINOPT pin to further improve 3rd-order linearity performance. Accurate temperature dependent calibrations can be performed using the on-chip thermistor. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Contact LTC Marketing for other common mode voltage versions. n n n n n n n Frequency Range: 200MHz to 6000MHz Output IP3: +31dBm Typical at 2140MHz (Uncalibrated) +35dBm Typical (User Optimized) Single Pin Calibration to Optimize OIP3 Low Output Noise Floor at 6MHz Offset: No RF: –160.6dBm/Hz POUT = 5dBm: –155.5dBm/Hz Integrated LO Buffer and LO Quadrature Phase Generator High Impedance DC Interface to Baseband Inputs with 0.5V Common Mode Voltage* 50Ω Single-Ended LO and RF Ports 3.3V Operation Fast Turn-Off/On: 10ns/17ns Temperature Sensor (Thermistor) 24-Lead UTQFN 4mm × 4mm Package APPLICATIONS n n n n n LTE, GSM/EDGE, W-CDMA, TD-SCDMA, CDMA2K, WiMax Basestations Image Reject Upconverters Point-to-Point Microwave Links Broadcast Modulator Military Radio TYPICAL APPLICATION 200MHz to 6000MHz Direct Conversion Transmitter Application 3.3V 1nF + 4.7μF 2 RF = 200MHz TO 6000MHz PA 0 EN Q-CHANNEL Q-DAC BASEBAND GENERATOR VI LINOPT 1nF 50Ω VCO/SYNTHESIZER 1nF LTC2630 55881 TA01a ACPR, AltCPR and ACPR, AltCPR with Optimized LINOPT Voltage vs RF Output Power at 2.14GHz for W-CDMA 1, 2 and 4 Carriers –40 ACPR ACPR (OPT) AltCPR –50 AltCPR (OPT) DOWNLINK TEST MODEL 64 DPCH –60 fBB = 140MHz, fLO = 2280MHz –70 4C 2C 1C VCC I-DAC VI I-CHANNEL 90 LTC5588-1 6.8pF 0.2pF ACPR, AltCPR (dBc) –80 –90 –20 –15 –5 0 5 –10 RF OUTPUT POWER PER CARRIER (dBm) 55881 TA01b 55881fb 1 LTC5588-1 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION GNDRF 18 VCC2 G N D R F 26 17 GNDRF 16 RF 15 NC 14 GNDRF 13 NC 7 LINOPT 8 GND 9 10 11 12 BBMQ BBPQ GNDRF GND TOP VIEW BBMI BBPI VCC1 GND GND Supply Voltage .........................................................3.8V Common Mode Level of BBPI, BBMI, and BBPQ, BBMQ...................................................0.55V Voltage on Any Pin...........................–0.3V to VCC + 0.3V TJMAX .................................................................... 150°C Operating Temperature Range .................–40°C to 85°C Storage Temperature Range .................. –65°C to 150°C 24 23 22 21 20 19 EN 1 GND 2 LOP 3 LOM 4 GND 5 NC 6 GND 25 PF24 PACKAGE VARIATION: PF24MA 24-LEAD (4mm 4mm) PLASTIC UTQFN TJMAX = 150°C, θJA = 43°C/W, θJC = 7°C/W (AT EXPOSED PAD) EXPOSED PADS (PINS 25, 26) ARE GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC5588IPF-1#PBF TAPE AND REEL LTC5588IPF-1#TRPBF PART MARKING 5881T PACKAGE DESCRIPTION 24-Lead (4mm × 4mm) Plastic UTQFN TEMPERATURE RANGE –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS SYMBOL fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT PARAMETER RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd-Order Intercept Output 3rd-Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) (Notes 4, 5) (Notes 4, 6) CONDITIONS VCC = 3.3V, EN = 3.3V, TA = 25°C, LOP AC-terminated with 50Ω to ground, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 0.5VDC, I and Q baseband input signal = 100kHz CW, 1VP-P(DIFF) each, I and Q 90° shifted, lower sideband selection, LINOPT pin floating, unless otherwise noted. Test circuit is shown in Figure 8. MIN TYP 200 to 244 200 to 1500 –5.9 –1.9 5.1 77.3 28 –168.3 –27 –53 MAX UNITS MHz MHz dB dBm dBm dBm dBm dBm/Hz dBc dBm , fLO = 240MHz, fRF = 239.9MHz, PLO = 10dBm, C7 = 4.7nH, C8 = 33pF Using U2 = Anaren P/N B0310J50100A00 Balun S22 < –10dB (Note 10) S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q No Baseband AC Input Signal (Note 3) (Note 7) (Note 7) 55881fb 2 LTC5588-1 ELECTRICAL CHARACTERISTICS SYMBOL fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT PARAMETER RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd-Order Intercept Output 3rd-Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd-Order Intercept Output 3rd-Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) (Notes 4, 5) (Notes 4, 6) Optimized (Notes 4, 6, 11) No Baseband AC Input Signal (Note 3) POUT = 5dBm (Note 3) PLOM = 10dBm (Note 7) (Note 7) EN = Low (Note 7) S22 < –10dB S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q (Notes 4, 5) (Notes 4, 6) Optimized (Notes 4, 6, 11) No Baseband AC Input Signal (Note 3) (Note 7) (Note 7) (Notes 4, 5) (Notes 4, 6) No Baseband AC Input Signal (Note 3) POUT = 1dBm (Note 3) (Note 7) (Note 7) S22 < –10dB S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q CONDITIONS S22 < –10dB (Note 10) S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q VCC = 3.3V, EN = 3.3V, TA = 25°C, LOP AC-terminated with 50Ω to ground, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 0.5VDC, I and Q baseband input signal = 100kHz CW, 1VP-P(DIFF) each, I and Q 90° shifted, lower sideband selection, LINOPT pin floating, unless otherwise noted. Test circuit is shown in Figure 8. MIN TYP 350 to 468 200 to 1500 –2.6 1.4 8.6 72 30 –165.2 –159.8 –53 –45 700 to 5000 600 to 6000 0 4.0 12.1 73.6 31.3 35.1 –161.6 –155.1 –45.5 –43.1 –68.9 700 to 5000 600 to 6000 0.4 4.4 12.4 58.8 30.3 32.7 –160.6 –54.4 –40.9 MAX UNITS MHz MHz dB dBm dBm dBm dBm dBm/Hz dBm/Hz dBc dBm MHz MHz dB dBm dBm dBm dBm dBm dBm/Hz dBm/Hz dBc dBm dBm MHz MHz dB dBm dBm dBm dBm dBm dBm/Hz dBc dBm , fLO = 450MHz, fRF = 449.9MHz, PLO = 10dBm, C7 = 2.7nH, C8 = 10pF U2 = Anaren P/N B0310J50100A00 Balun , fLO = 900MHz, fRF = 899.9MHz, PLOM = 0dBm, C7 = 6.8pF C8 = 0.2pF , fLO = 1900MHz, fRF = 1899.9MHz, PLOM = 0dBm, C7 = 6.8pF C8 = 0.2pF fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd-Order Intercept Output 3rd-Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) 55881fb 3 LTC5588-1 ELECTRICAL CHARACTERISTICS SYMBOL fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT fRF(MATCH) fLO(MATCH) GV POUT OP1dB OIP2 OIP3 NFloor IR LOFT PARAMETER RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd Order Intercept Output 3rd Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd-Order Intercept Output 3rd-Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) RF Match Frequency Range LO Match Frequency Range Conversion Voltage Gain Absolute Output Power Output 1dB Compression Output 2nd-Order Intercept Output 3rd-Order Intercept RF Output Noise Floor Image Rejection Carrier Leakage (LO Feedthrough) (Notes 4, 5) (Notes 4, 6) Optimized (Notes 4, 6, 11) No Baseband AC Input Signal (Note 3) (Note 7) (Note 7) (Notes 4, 5) (Notes 4, 6) Optimized (Notes 4, 6, 11) No Baseband AC Input Signal (Note 3) (Note 7) (Note 7) S22 < –10dB S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q (Notes 4, 5) (Notes 4, 6) Optimized (Notes 4, 6, 11) No Baseband AC Input Signal (Note 3) POUT = 5dBm (Note 3) PLOM = 10dBm (Note 7) (Note 7) S22 < –10dB S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q CONDITIONS S22 < –10dB S11 < –10dB 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) 1VP-P(DIFF) CW Signal, I and Q VCC = 3.3V, EN = 3.3V, TA = 25°C, LOP AC-terminated with 50Ω to ground, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 0.5VDC, I and Q baseband input signal = 100kHz CW, 1VP-P(DIFF) each, I and Q 90° shifted, lower sideband selection, LINOPT pin floating, unless otherwise noted. Test circuit is shown in Figure 8. MIN TYP 700 to 5000 600 to 6000 0.2 4.2 12.0 58.5 30.9 35.1 –160.6 –155.5 –56.6 –39.6 700 to 5000 600 to 6000 –0.2 3.8 11.4 61.1 29.2 39.5 –160.5 –48.8 –35.5 700 to 5000 600 to 6000 –1.0 3.0 10.5 67.6 23.5 27.5 –160.1 –36.8 –37.5 700 to 5000 600 to 6000 –9.1 –5.1 MAX UNITS MHz MHz dB dBm dBm dBm dBm dBm dBm/Hz dBm/Hz dBc dBm MHz MHz dB dBm dBm dBm dBm dBm dBm/Hz dBc dBm MHz MHz dB dBm dBm dBm dBm dBm dBm/Hz dBc dBm MHz MHz dB dBm 55881fb , fLO = 2140MHz, fRF = 2139.9MHz, PLOM = 0dBm, C7 = 6.8pF C8 = 0.2pF , fLO = 2600MHz, fRF = 2599.9MHz, PLOM = 0dBm, C7 = 6.8pF C8 = 0.2pF , fLO = 3500MHz, fRF = 3499.9MHz, PLOM = 0dBm, C7 = 6.8pF C8 = 0.2pF fLO = 5800MHz, fRF = 5799.9MHz, PLOM = 0dBm, C7 = 6.8pF C8 = 0.2pF , S22, < –10dB fRF(MATCH) RF Match Frequency Range S11, < –10dB fLO(MATCH) LO Match Frequency Range Conversion Voltage Gain 20 • Log (VRF(OUT)(50Ω)/VIN(DIFF)(I or Q)) GV Absolute Output Power 1VP-P(DIFF) CW Signal, I and Q POUT 4 LTC5588-1 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS (Notes 4, 5) (Notes 4, 6) No Baseband AC Input Signal (Note 3) (Note 7) (Note 7) –1dB Bandwidth, RSOURCE = 25Ω, Single Ended Single Ended Single Ended Externally Applied No Hard Clipping, Single Ended 3.15 275 OP1dB Output 1dB Compression OIP2 Output 2nd-Order Intercept OIP3 Output 3rd-Order Intercept NFloor RF Output Noise Floor IR Image Rejection LOFT Carrier Leakage (LO Feedthrough) Baseband Inputs (BBPI, BBMI, BBPQ, BBMQ) Baseband Bandwidth BWBB Baseband Input Current Ib(BB) Input Resistance RIN(SE) DC Common Mode Voltage VCMBB Amplitude Swing VSWING Power Supply (VCC1, VCC2) Supply Voltage VCC Supply Current ICC(ON) Supply Current, Sleep Mode ICC(OFF) Turn-On Time tON Turn-Off Time tOFF Image Rejection Settling tON(IR) LO Suppression Settling tON(LO) tON(PHASE) Phase Settling VLINOPT(ON) LINOPT Voltage VLINOPT(OFF) LINOPT Voltage, Sleep Mode Enable Pin Enable Input High Voltage Input High Current Sleep Input Low Voltage Input Low Current Temperature Sensor (Thermistor) (Note 14) Thermistor Resistance RT Temperature Slope VCC = 3.3V, EN = 3.3V, TA = 25°C, LOP AC-terminated with 50Ω to ground, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 0.5VDC, I and Q baseband input signal = 100kHz CW, 1VP-P(DIFF) each, I and Q 90° shifted, lower sideband selection, LINOPT pin floating, unless otherwise noted. Test circuit is shown in Figure 8. MIN TYP 1.9 35.4 17.9 –156.7 –32.3 –30.2 430 –136 –3 0.5 0.86 3.3 303 33 17 10 80 85 70 2.56 3.3 2 80 1 33 1.385 11 3.45 325 900 MAX UNITS dBm dBm dBm dBm/Hz dBc dBm MHz μA kΩ V VP-P V mA μA ns ns ns ns ns V V V nA V μA kΩ Ω/°C EN = High EN = 0V EN = Low to High (Notes 8, 13) EN = High to Low (Notes 9, 13) EN = Low to High, VGND 55881fb 15 LTC5588-1 PIN FUNCTIONS EN (Pin 1): Enable Input. When the enable pin voltage is higher than 2V, the IC is on. When the input voltage is less than 1V, the IC is off. GND (Pins 2, 5, 8, 11, 12, 14, 17, 19, 20, 23, Exposed Pad Pins 25 and 26): Ground. Pins 2, 5, 8, 11, 20, 23 and exposed pad Pin 25 (group 1) are connected together internally while Pins 12, 14, 17, 19 and exposed pad Pin 26 (group 2) are tied together and serve as the ground return for the RF balun. For best overall performance all ground pins should be connected to RF ground. For best OIP2 performance it is recommended to connect group 1 and group 2 only at second and lower level ground layers of the PCB, not the top layer. A thermistor (temperature variable resistor) of 1.4kΩ at 25°C and VCC = 3.3V with temperature coefficient of 11Ω/°C is connected between group 1 and group 2. LOP (Pin 3): Positive LO Input. An AC-coupling capacitor (1nF) in series with 50Ω to ground provides the best OIP2 performance. LOM (Pin 4): Negative LO Input. An AC-coupled 50Ω LO signal source can be applied to this pin. NC (Pins 6, 13, 15): No Electrical Connection. LINOPT (Pin 7): Linearity Optimization Input. An external voltage can be applied to this pin to optimize the linearity (OIP3) under a specific application condition. Its optimum voltage depends on the LO frequency, temperature, supply voltage, baseband frequency and signal bandwidth. The typical input voltage range is from 2V to 3.7V. The pin can be left floating for good overall linearity performance. BBMQ, BBPQ (Pins 9, 10): Baseband Inputs of the Q Channel. The input impedance of each input is about –3kΩ. It should be externally biased to a 0.5V common mode level. Do not apply common mode voltage beyond 0.55VDC. RF (Pin 16): RF Output. The RF output is a DC-coupled single-ended output with 50Ω output impedance at RF frequencies. An AC-coupling capacitor of 6.2pF (C7), should be used at this pin for 0.7GHz to 3.5GHz operation. VCC1, VCC2 (Pins 24, 18): Power Supply. It is recommended to use 2 × 1nF and 2 × 4.7μF capacitors for decoupling to ground on these pins. BBPI, BBMI (Pins 21, 22): Baseband Inputs of the I Channel. The input impedance of each input is about –3kΩ. It should be externally biased to a 0.5V common mode level. Do not apply common mode voltage beyond 0.55VDC. BLOCK DIAGRAM GND 20 BBPI 21 BBMI 22 23 25 VCC1 VCC2 24 18 13 NC 15 VI I CHANNEL 0° 90° GND 16 RF BBPQ 10 BBMQ 9 VI Q CHANNEL 2 5 GND 8 11 3 4 6 7 12 14 17 19 26 1 EN LOP LOM NC LINOPT GNDRF 55881 BD 55881fb 16 LTC5588-1 APPLICATIONS INFORMATION The LTC5588-1 consists of I and Q input differential voltage-to-current converters, I and Q upconverting mixers, an RF output balun, an LO quadrature phase generator and LO buffers. External I and Q baseband signals are applied to the differential baseband input pins, BBPI, BBMI and BBPQ, BBMQ. These voltage signals are converted to currents and translated to RF frequency by means of double-balanced upconverting mixers. The mixer outputs are combined at the inputs of the RF output balun, which also transforms the output impedance to 50Ω. The center frequency of the resulting RF signal is equal to the LO signal frequency. The LO input drives a phase shifter which splits the LO signal into in-phase and quadrature signals. These LO signals are then applied to on-chip buffers which drive the upconverting mixers. In most applications, the LOM input is driven by the LO source via a 1nF coupling capacitor, while the LOP input is terminated with 50Ω to RF ground via a 1nF coupling capacitor. The RF output is single ended and internally 50Ω matched across a wide RF frequency range from 700MHz to 5GHz with better than 10dB return loss using C7 = 6.8pF and C8 = 0.2pF (S22 < –10dB). See Figure 8. For 240MHz operation, C7 = 4.7nH and C8 = 33pF is recommended. For 450MHz, C7 = 2.7nH and C8 = 10pF is recommended. Note that the frequency of the best match is set lower than the band center frequency to compensate the gain roll-off of the on-chip RF output balun at lower frequency. At 240MHz and 450MHz operations, the image rejection and the large-signal noise performance is better using higher LO drive levels. However, if the drive level causes internal clipping, the LO leakage degrades. Using a balun such as Anaren P/N B0310J50100A00 increases the LO drive level without internal clipping and provides a relatively broadband LO port impedance match. Baseband Interface The baseband inputs (BBPI, BBMI, BBPQ, BBMQ) present a single-ended input impedance of about –3kΩ. Because of the negative input impedance, it is important to keep the source resistance at each baseband input low enough such that the total input impedance remains positive across the baseband frequency. Each of the four baseband inputs has a capacitor of 4pF in series with 14Ω connected to ground and a PNP emitter follower in parallel (see Figure 1). The baseband bandwidth depends on the source impedance. For a 25Ω source impedance (50Ω terminated with 50Ω), the baseband bandwidth (–1dB) is about 430MHz. If a 2.7nH series inductor is inserted at each of the four baseband inputs, the –1dB baseband bandwidth can be increased to about 650MHz. VCC2 = 3.3V BALUN FROM Q CHANNEL LOMI LOPI LTC5588-1 RF VCC1 = 3.3V BBPI 14Ω 4pF VCM = 0.5V 4pF 14Ω BBMI GNDRF 55881 F01 GND Figure 1. Simplified Circuit Schematic of the LTC5588-1 (Only I Channel is Shown) 55881fb 17 LTC5588-1 APPLICATIONS INFORMATION It is recommended to compensate the baseband input impedance in the baseband lowpass filter design in order to achieve best gain flatness vs baseband frequency. The S-parameters for (each of) the baseband inputs is given in Table 1. Table 1. Single-Ended BB Input Impedance vs Frequency for EN = High and VDC = 0.5V FREQUENCY (MHz) 0.1 1 2 4 8 16 30 60 100 140 200 250 300 350 400 450 500 600 700 800 900 1000 BB INPUT IMPEDANCE –3700 –3900-j340 –3700-j950 –3200-j1500 –2100-j1900 –860-j1600 –300-j990 –87-j520 –35-j308 –16-j226 –6-j154 –1.4-j120 1.4-j102 4.4-j87 5.4-j74 7-j66 8.3-j58 9.4-j47 10-j38 10-j32 10.5-j27 10.5-j23 REFLECTION COEFFICIENT MAG ANGLE 1.03 –0.13 1.03 –0.13 1.03 –0.37 1.03 –0.68 1.03 –1.38 1.03 –2.79 1.03 –5.3 1.03 –10.6 1.04 –18.2 1.03 –24.8 1.02 –36 1.01 –45 0.99 –52 0.96 –59 0.94 –67 0.90 –73 0.87 –80 0.82 –92 0.77 –102 0.74 –113 0.71 –122 0.69 –129 The circuit is optimized for a common mode voltage of 0.5V which should be externally applied. The baseband pins should not be left floating to cause the internal PNP’s base current to pull the common mode voltage higher than the 0.55V limit, generating excessive current flow. If it occurs for an extended period, damage to the IC may result. In shutdown mode it is recommended to terminate to ground or to a 0.5V source with a value lower than 200Ω. The PNP’s base current is about –136μA ranging from –250μA to –50μA. It is recommended to drive the baseband inputs differentially to reduce even-order distortion products. When a DAC is used as the signal source, a reconstruction filter should be placed between the DAC output and the LTC5588-1 baseband inputs to avoid aliasing. Figure 2 shows a typical baseband interface for zero-IF repeater application. A 5th-order lowpass ladder filter is used with –0.3dB cut-off of 60MHz. C1A, C1B, C3A and C3B are configured in a single-ended fashion in order to suppress common mode noise. L3A and L3B (0402 size) are used to compensate for passband droop due to the finite quality factor of the inductors L1A, L1B, L2A and L2B (0603 size). R3A and R3B improves the out-of-band noise performance. R3A = R3B = 0Ω (L3A and L3B omitted) provides best out-of-band noise performance but no passband droop compensation. In that case, L1A, L1B, L2A and L2B may have to be increased in size (higher quality factor) to limit passband droop. 10mA ±10mA L1A 250nH L2A 250nH 0.5VDC L3A 100nH BBPI R3A 71.5 R1A 71.5 DAC R1B 71.5 C1A 47pF C1B 47pF L1B 250nH C2 39pF L2B 250nH C3A 47pF C3B 47pF R2A 165 R2B 165 R2C 249 R3B 71.5 L3B 100nH BBMI 0.5VDC 55881 F02 10mA ±10mA GND Figure 2: Baseband Interface with 5th-Order Filter and 0.5VCM DAC (Only I Channel is Shown) 55881fb 18 LTC5588-1 APPLICATIONS INFORMATION At each baseband pin, a 0.146V to 0.854V swing is developed corresponding to a DAC output current of 0mA to 20mA. A 3dB lower gain can be achieved using R1A = R1B = 49.9Ω; R2A = R2B = Open; R2C = 100Ω; R3A = R3B = 51Ω; L1A = L1B = L2A = L2B = 180nH; C1A = C1B = C3A = C3B = 68pF; C2 = 56pF . LO Section The internal LO chain consists of a quadrature phase shifter followed by LO buffers. The LOM input can be driven single ended with 50Ω input impedance, while the LOP input should be terminated with 50Ω through a DC blocking capacitor. The LOP and LOM inputs can also be driven differentially when an exceptionally low large-signal output noise floor is required. A simplified circuit schematic for the LOP and LOM inputs is given in Figure 3. Table 2 lists LOM port input impedance vs frequency at EN = High and PLOM = 0dBm. For EN = Low and PLOM = 0dBm the input impedance is given in Table 3. The LOM port input impedance is shown for EN = High and Low at PLOM = 10dBm in Table 4 and Table 5, respectively. The circuit schematic of the demo board is shown in Figure 8. A 50Ω termination can be connected to the LOP port (J1). The LOM port (J2) can also be terminated with a 50Ω while the LO power is applied to the LOP (J1) port. In that case, the image rejection may be degraded. At 2.14GHz, the large-signal noise figure is about 2dB better for difVCC1 ferential LO drive (using BD1631J50100A00) with a LO power below 10dBm. The balun (U2) can be installed by removing C5 and C6 (see Figure 8). Using Anaren P/N B0310J50100A00 improves image, LO leakage and large-signal noise performance at 240MHz and 450MHz. For this particular balun, an external blocking capacitor is required. Figure 4 shows the return loss vs RF frequency for the 240MHz and 450MHz frequency bands. Figure 5 shows the corresponding gain vs RF frequency where the gain curve peaks at a higher frequency compared to the frequency with best match. Note that the overall bandwidth degrades tuning the matching frequency lower. A similar technique can be used for 700MHz and 900MHz if gain flatness is important. Table 2. LOM Port Input Impedance vs Frequency for EN = High and PLOM = 0dBm (LOP Terminated with 50Ω AC to Ground) FREQUENCY (GHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 LOM INPUT IMPEDANCE 98-j65 87-j58 79-j51 69-j40 63-j32 59-j27 55-j24 52-j21 50-j19 48-j18 44-j16 41-j15 39-j14 38-j13 37-j12 36-j7.8 32-j2.4 28+j1.0 25+j2.4 23+j4.1 21+j6.2 19+j7.9 17+j8.7 REFLECTION COEFFICIENT MAG 0.499 0.462 0.421 0.354 0.296 0.256 0.225 0.203 0.188 0.18 0.178 0.185 0.194 0.2 0.199 0.189 0.225 0.288 0.35 0.372 0.417 0.472 0.519 ANGLE –29.8 –34.3 –38.8 –45.8 –52.4 –58.4 –64.9 –72.5 –79.6 –86.9 –101 –111 –118 –123 –128 –146 –171 176 173 168 162 159 157 55881fb LOP LOM + – 2.35V (3.3V IN SHUTDOWN) 55881 F03 3.5 4.0 4.5 5.0 5.5 6.0 Figure 3: Simplified Circuit Schematic for the LOP and LOM inputs 19 LTC5588-1 APPLICATIONS INFORMATION Table 3. LOM Port Input Impedance vs Frequency for EN = Low and PLOM = 0dBm (LOP Terminated with 50Ω AC to Ground) FREQUENCY (GHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LOM INPUT IMPEDANCE 95-j69 84-j61 76-j53 67-j41 61-j33 57-j28 54-j24 51-j21 48-j19 47-j18 43-j16 40-j15 39-j14 38-j13 37-j12 35-j7.6 31-j2.2 27+j1.3 24+j2.9 22+j4.7 21+j7.0 18+j8.7 16+j9.7 REFLECTION COEFFICIENT MAG 0.511 0.472 0.43 0.36 0.3 0.259 0.228 0.205 0.191 0.183 0.182 0.19 0.2 0.207 0.205 0.2 0.238 0.303 0.363 0.387 0.427 0.481 0.524 ANGLE –31.4 –36.2 –41 –48.5 –55.6 –61.9 –68.7 –76.5 –83.6 –90.9 –105 –114 –121 –125 –131 –149 –172 175 171 166 160 157 154 Table 4. LOM Port Input Impedance vs Frequency for EN = High and PLOM = 10dBm (LOP Terminated with 50Ω AC to Ground) FREQUENCY (GHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LOM INPUT IMPEDANCE 96-j64 86-j57 77-j51 69-j41 62-j33 58-j28 55-j24 52-j21 50-j19 48-j18 44-j16 41-j15 39-j14 38-j14 37-j12 36-j7.9 32-j2.7 28+j0.8 24+j2.0 23+j3.6 21+j5.9 19+j7.5 16+j8.5 REFLECTION COEFFICIENT MAG 0.494 0.455 0.42 0.356 0.3 0.258 0.229 0.203 0.192 0.179 0.176 0.185 0.196 0.202 0.201 0.188 0.225 0.292 0.348 0.373 0.42 0.468 0.518 ANGLE –30.6 –35.1 –40.2 –46.6 –54.1 –59.1 –66.6 –73.1 –80.6 –87.5 –102 –112 –119 –123 –128 –146 –170 176 172 168 162 159 157 55881fb 20 LTC5588-1 APPLICATIONS INFORMATION Table 5. LOM Port Input Impedance vs Frequency for EN = Low and PLOM = 10dBm (LOP Terminated with 50Ω AC to Ground) MAG 0.48 0.444 0.414 0.345 0.293 0.251 0.225 0.199 0.191 0.18 0.181 0.192 0.205 0.211 0.212 0.202 0.244 0.31 0.363 0.389 0.433 0.479 0.525 ANGLE –32.1 –36.9 –42 –49.3 –57.4 –63.2 –71.2 –78.8 –86.6 –93.6 –108 –117 –123 –127 –132 –150 –172 175 171 166 160 157 154 –10 200 VOLTAGE GAIN (dB) 0 FREQUENCY (GHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 LOM INPUT IMPEDANCE 92-j61 83-j55 75-j50 66-j39 60-j32 56-j27 53-j23 50-j20 48-j19 46-j17 42-j15 40-j14 38-j14 37-j13 36-j12 35-j7.5 31-j2.2 27+j1.3 24+j2.7 22+j4.4 20+j6.8 18+j8.5 16+j9.5 REFLECTION COEFFICIENT –2 –4 –6 3.3V, 85°C 3.3V, 25°C 3.15V, 25°C 3.45V, 25°C 3.3V, –40°C 400 300 500 RF FREQUENCY (MHz) 600 55881 F05 –8 Figure 5. Low Band Voltage Gain vs RF Frequency Using Figure 4 Matching The third harmonic content of the LO can degrade image rejection severely, it is recommended to keep the 3rd-order harmonic of the LO signal lower than the desirable image rejection minus 6dB. Although the second harmonic content of the LO is less sensitive, it can still be significant. The large-signal noise figure can be improved with higher LO input power. However, if the LO input power is too large to cause the internal LO signal clipping in the phase-shifter section, the image rejection can be degraded rapidly. This clipping point depends on the supply voltage, LO frequency, temperature and single ended vs differential LO drive. At fLO = 2140MHz, VCC = 3.3V, T = 25°C and singleended LO drive, this clipping point is at about 16.7dBm. For 3.15V it lowers to 16.1dBm. For differential drive it is about 21.6dBm. The differential LO port input impedance for EN = High and PLO = 10dBm is given in Table 6. –10 RETURN LOSS (dB) –20 –30 RF PORT, EN = HIGH, C7 = 4.7nH, C8 = 33pF RF PORT, EN = LOW, C7 = 4.7nH, C8 = 33pF RF PORT, EN = HIGH, C7 = 2.7nH, C8 = 10pF RF PORT, EN = LOW, C7 = 2.7nH, C8 = 10pF LO PORT, EN = HIGH, USING B0310J50100A00 LO PORT, EN = LOW, USING B0310J50100A00 –40 200 300 400 FREQUENCY (MHz) 500 600 55881 F04 Figure 4. RF and LO Port Return Loss vs Frequency for Low Band Match (See Figure 8) 55881fb 21 LTC5588-1 APPLICATIONS INFORMATION Table 6: Differential LO Input Impedance vs Frequency for EN = High and PLO = 10dBm FREQUENCY (MHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LO DIFFERENTIAL INPUT IMPEDANCE 134-j48 126-j51 119-j46 109-j45 100-j40 97-j36 94-j36 90-j35 84-j34 83-j33 77-j36 76-j37 73-j38 74-j37 74-j35 78-j28 74-j15 67-j2.9 58+j7.3 51+j15 42+j18 34+j20 27+j16 REFLECTION COEFFICIENT MAG 0.247 0.247 0.223 0.215 0.194 0.181 0.184 0.186 0.198 0.198 0.237 0.243 0.262 0.254 0.251 0.199 0.173 0.197 0.275 0.338 0.433 0.515 0.596 ANGLE –43 –50 –55 –66 –79 –84 –90 –96 –104 –107 –111 –111 –113 –113 –115 –120 –145 –174 168 158 156 156 160 FREQUENCY (MHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Table 7: Differential LO Input Impedance vs Frequency for EN = Low and PLO = 10dBm LO DIFFERENTIAL INPUT IMPEDANCE 131-j48 125-j52 117-j46 107-j45 98-j40 95-j36 92-j35 88-j34 83-j33 82-j32 75-j35 76-j35 72-j36 74-j35 73-j33 77-j25 73-j12 66-j0.2 56+j10 49+j18 39+j21 32+j22 25+j18 REFLECTION COEFFICIENT MAG 0.243 0.250 0.221 0.215 0.197 0.183 0.186 0.188 0.200 0.199 0.237 0.240 0.259 0.248 0.245 0.191 0.172 0.206 0.293 0.362 0.459 0.538 0.619 ANGLE –45 –52 –58 –69 –81 –87 –93 –99 –107 –110 –114 –113 –115 –115 –118 –125 –152 180 164 154 153 153 158 55881fb 22 LTC5588-1 APPLICATIONS INFORMATION RF Section After upconversion, the RF outputs of the I and Q mixers are combined. An on-chip balun performs internal differential to single-ended conversion, while transforming the output signal to 50Ω as shown in Figure 1. Table 8 shows the RF port output impedance vs frequency for EN = High. Table 8. RF Output Impedance vs Frequency for EN = High FREQUENCY (MHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 1.9 2.0 2.5 3.0 3.2 3.5 4.0 4.5 5.0 5.5 6.0 RF OUTPUT IMPEDANCE 7.8+j11 8.7+j13 9.7+j16 12+j21 16+j25 19+j29 24+j32 30+j34 35+j35 41+j34 52+j28 58+j18 58+j7.1 55+j0.2 52-j2.7 50-j4.3 39-j5.9 32-j1.9 30-j0.2 27+j2.2 23+j4.5 22+j6.8 19+j11 17+j20 15+j27 REFLECTION COEFFICIENT MAG 0.742 0.723 0.702 0.660 0.609 0.560 0.509 0.457 0.409 0.359 0.266 0.180 0.098 0.042 0.032 0.043 0.142 0.227 0.255 0.298 0.365 0.406 0.475 0.541 0.613 ANGLE 154 149 143 133 123 114 106 98 91 85 70 57 39 3.4 –52 –92 –149 –173 –180 172 167 161 151 133 120 The RF port output impedance for EN = Low is given in Table 9. Table 9. RF Output Impedance vs Frequency for EN = Low FREQUENCY (MHz) 0.2 0.25 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 1.9 2.0 2.5 3.0 3.2 3.5 4.0 4.5 5.0 5.5 6.0 RF OUTPUT IMPEDANCE 7.2+j11 8.0+j13 9.0+j16 12+j21 15+j25 19+j29 23+j32 29+j34 35+j35 40+j34 51+j28 57+j18 57+j7.0 53+j0.4 51-j2.4 48-j4.0 38-j4.9 31-j0.7 29+1.0 27+j3.6 24+j5.6 22+j6.9 19+j11 17+j20 15+j28 REFLECTION COEFFICIENT MAG 0.761 0.742 0.720 0.675 0.622 0.571 0.518 0.464 0.414 0.363 0.266 0.175 0.090 0.030 0.025 0.044 0.153 0.240 0.266 0.308 0.365 0.405 0.478 0.563 0.628 ANGLE 155 149 144 133 123 115 107 99 92 86 72 60 43 7.0 –74 –111 –155 –177 –177 169 164 161 151 132 118 55881fb 23 LTC5588-1 APPLICATIONS INFORMATION Linearity Optimization The LINOPT pin (Pin 7) can be used to optimize the linearity of the RF circuitry. Figure 6 shows the simplified schematic of the LINOPT pin interface. The nominal DC bias voltage of the LINOPT pin is 2.56V and the typical voltage window to drive the LINOPT pin for optimum linearity is 2V to 3.7V. Since its input impedance for EN = High is about 150Ω, an external buffer may be required to output a current in the range of –2mA to 8mA. The LINOPT voltage for optimum linearity is a function of LO frequency, temperature, supply voltage, baseband frequency, high side or low side LO injection, process, signal bandwidth and RF output level. For zero-IF systems the spectral regrowth is typically limited by the OIP2 performance. In that case, optimizing the LINOPT pin voltage may not improve the spectral regrowth. The spectral regrowth for systems with an IF (for example 140MHz) will be set by the OIP3 performance and optimizing LINOPT voltage can improve the spectral regrowth significantly (see Figure 13). Enable Interface Figure 7 shows a simplified schematic of the EN pin interface. The voltage necessary to turn on the LTC5588-1 is 2V. To disable (shut down) the chip, the enable voltage must be below 1V. If the EN pin is not connected, the chip is enabled. This EN = High condition is assured by the 100k on-chip pull-up resistor. VCC1 75Ω LINOPT 100Ω 250Ω INTERNAL ENABLE SIGNAL 55881 F06 Figure 6. LINOPT Pin Interface VCC1 100k EN INTERNAL ENABLE CIRCUIT 55881 F07 Figure 7. EN Pin Interface 55881fb 24 LTC5588-1 APPLICATIONS INFORMATION Evaluation Board Figure 8 shows the evaluation board schematic. A good ground connection is required for the exposed pad. If this is not done properly, the RF performance will degrade. Additionally, the exposed pad provides heat sinking for the part and minimizes the possibility of the chip overheating. Resistors R1 and R2 reduce the charging current in capacitors C1 and C2 (see Figure 8) and will reduce supply ringing during a fast power supply ramp-up with inductive wiring connecting VCC and GND. For EN = High, the J9 BBMI C12 OPT R11 OPT R4 OPT TP1 J5 EN R3 OPT J1 LOP C5 1nF 1 6 U2 OPT 5 4 2 3 4 5 6 R12 OPT R14 1Ω R13 OPT J3 BBMQ C9 OPT C10 R9 OPT OPT 55881 F08 voltage drop over R1 and R2 is about 0.15V. The supply voltages applied directly to the chip can be monitored by measuring at the test points TP1 and TP2. If a power supply is used that ramps up slower than 7V/μs and limits the overshoot on the supply below 3.8V, R1 and R2 can be omitted. To facilitate turn-on and turn-off time measurements, the microstrip between J5 and J7 can be used connecting J5 to a pulse generator, J7 to an oscilloscope with 50Ω input impedance, removing R5 and inserting a 0Ω resistor for R3. J8 BBPI C11 R10 OPT OPT R6 OPT J7 EN C1 4.7μF R5 0Ω C3 1nF VCC R1 1Ω R2 1.3Ω TP2 EN 24 23 22 21 20 19 VCC1 BBMI BBPI GND GND GNDRF C4 1nF C2 4.7μF EN GND LOP LOM GND NC LINOPT GNDRF BBMQ BBPQ GND GND U1 LTC5588-1 VCC2 GNDRF RF NC GNDRF NC 18 17 16 15 14 13 C8 0.2pF C7 6.8pF J6 RF OUT NC GND BP BALUN UNBP GND BP 1 2 3 C14 1nF J2 LOM GND C6 1nF LINOPT 25 C13 100nF 7 8 9 10 11 12 26 BOARD NUMBER: DC1524A J4 BBPQ R8 OPT R7 OPT Figure 8. Evaluation Circuit Schematic 55881fb 25 LTC5588-1 APPLICATIONS INFORMATION Figures 9 and 10 show the component side and the bottom side of the evaluation board. An enlarged view of the component side around the IC placement shows all pins related to GND (group 1) and all pins related to GNDRF (group 2) are not connected via the top layer of the component side in Figure 11. It is possible to use the part without a split-paddle PCB island, but this may degrade OIP2 by a few dB at some frequencies and reduce LO leakage slightly. Due to self heating, the board temperature on the bottom side underneath the exposed die paddle for EN = high and VCC = 3.3V is –29.5°C at –40°C, 37.8°C at 25°C and 98.1°C at 85°C ambient temperatures. The on-chip temperature can be obtained using the built-in thermistor. The on-chip thermistor is internally connected between GNDRF and GND, requiring AC grounding Pins 12, 14, 17, 19 and the exposed pad pin 26. The thermistor is 1.4kΩ at 25°C and VCC = 3.3V, and has a temperature coefficient of 11Ω/°C. Switching from EN = Low to EN = High causes a 1.5mV DC voltage increase on the (AC grounded) GNDRF due to the internal IR drop. Figure 10. Bottom Side of Evaluation Board Figure 9. Component Side of Evaluation Board Figure 11. Enlarged View of the Component Side of the Evaluation Board 55881fb 26 LTC5588-1 APPLICATIONS INFORMATION The LTC5588-1 is recommended for basestation applications using various modulation formats. Figure 14 shows a typical application. The LTC2630 can be used to drive the LINOPT pin via a SPI interface. At 3.3V supply, the maximum LINOPT voltage is about 3.125V. Using an extra buffer like the LTC6246 in unity-gain configuration can increase the maximum LINOPT voltage to about 3.17V. An LTC2630 with a 5V supply can drive the full 2V to 3.7V range for the LINOPT pin. –40 Figure 12 shows the ACPR, AltCPR and ACPR, AltCPR with Optimized LINOPT voltage vs RF Output Power at 2.14GHz for W-CDMA 1, 2 and 4 Carriers. A 4-Carriers W-CDMA spectrum is shown in Figure 13 with and without LINOPT voltage optimization. ACPR, AltCPR (dBc) ACPR ACPR (OPT) AltCPR –50 AltCPR (OPT) DOWNLINK TEST MODEL 64 DPCH –60 fBB = 140MHz, fLO = 2280MHz –70 4C 2C 1C –80 –90 –20 –15 –5 0 5 –10 RF OUTPUT POWER PER CARRIER (dBm) 55881 TA Figure 12. ACPR, AltCPR and ACPR, AltCPR with Optimized LINOPT Voltage vs RF Output Power at 2.14GHz for W-CDMA 1, 2 and 4 Carriers –20 DOWNLINK TEST MODEL 64 DPCH POWER IN 30kHz BW (dBm) –40 –60 –80 fBB = 140MHz fLO = 2280MHz OPTIMIZED NOT OPTIMIZED 2.125 2.145 2.155 2.135 RF FREQUENCY (GHz) 2.165 55881 F13 –100 –120 2.115 Figure 13. 4-Carrier W-CDMA Spectrum with and without LINOPT Voltage Optimization 55881fb 27 LTC5588-1 PACKAGE DESCRIPTION PF Package Variation: PF24MA 24-Lead Plastic UTQFN (4mm × 4mm) (Reference LTC DWG # 05-08-1834 Rev Ø) 2.50 REF 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 0.41 0.05 0.41 0.05 1.24 0.05 0.41 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW—EXPOSED PAD 0.55 4.00 PIN 1 TOP MARK (NOTE 6) 0.10 0.05 R = 0.05 TYP 2.50 REF 23 24 0.40 1 2 4.00 0.10 2.45 0.10 0.41 0.10 0.41 0.10 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.25 45 CHAMFER 1.24 0.10 R = 0.125 TYP (PF24MA) UTQFN 0908 REV Ø 0.125 REF 0.00 – 0.05 0.41 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.10 0.25 0.05 0.50 BSC 55881fb 28 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC5588-1 REVISION HISTORY REV A DATE 2/11 DESCRIPTION Updated Features and Description sections Add θJC value to Pin Configuration Additional information added to Electrical Characteristics section Added Typical Performance Characteristics curves Revised Applications Information to replace Figure 1 and text. B 3/11 Added Note 14 to Electrical Characteristics section. PAGE NUMBER 1 2 5 14, 15 17, 26 5 55881fb 29 LTC5588-1 TYPICAL APPLICATION 24 21 I-DAC 22 VI I-CHANNEL 1 EN 10 Q-DAC BASEBAND GENERATOR 9 Q-CHANNEL VI 3 1nF 50Ω VCO/SYNTHESIZER 4 1nF LINOPT 7 6 3.3V 4 DAC LTC2630 5 55881 F14 18 LTC5588-1 VCC 1nF + 4.7μF 2 6.8pF 3.3V RF = 200MHz TO 6000MHz PA 0 90 12,14,17, 19, 26 0.2pF 2, 5, 8, 11, 20 23, 25 1 2 3 LD SCK SDI Figure 14. 200MHz to 6000MHz Direct Conversion Transmitter Application RELATED PARTS PART NUMBER Infrastructure LT®5518 LT5528 LT5558 LT5568 LT5571 LT5572 LTC5598 1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator 1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator 600MHz to 1100MHz High Linearity Direct Quadrature Modulator 700MHz to 1050MHz High Linearity Direct Quadrature Modulator 620MHz to 1100MHz High Linearity Direct Quadrature Modulator 1.5GHz to 2.5GHz High Linearity Direct Quadrature Modulator 5MHz to 1600MHz High Linearity Direct Quadrature Modulator 22.8dBm OIP3 at 2GHz, –158.2dBm/Hz Noise Floor, 3kΩ 2.1VDC Baseband Interface, 5V/128mA Supply 21.8dBm OIP3 at 2GHz, –159.3dBm/Hz Noise Floor, 50Ω 0.5VDC Baseband Interface, 5V/128mA Supply 22.4dBm OIP3 at 900MHz, –158dBm/Hz Noise Floor, 3kΩ 2.1VDC Baseband Interface, 5V/108mA Supply 22.9dBm OIP3 at 850MHz, –160.3dBm/Hz Noise Floor, 50Ω 0.5VDC Baseband Interface, 5V/117mA Supply 21.7dBm OIP3 at 900MHz, –159dBm/Hz Noise Floor, Hi-Z 0.5VDC Baseband Interface, 5V/97mA Supply 21.6dBm OIP3 at 2GHz, –158.6dBm/Hz Noise Floor, Hi-Z 0.5VDC Baseband Interface, 5V/120mA Supply 27.7dBm OIP3 at 140MHz, –160dBm/Hz Noise Floor with POUT = 5dBm IIP3 = 26.4dBm, 8dB Conversion Gain,