LT6220CS8

LT6220/LT6221/LT6222 Single/Dual/Quad 60MHz, 20V/µs, Low Power, Rail-to-Rail Input and Output Precision Op Amps FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Gain Bandwidth Product: 60MHz Input Common Mode Range Includes Both Rails Output Swings Rail-to-Rail Low Quiescent Current: 1mA Max Input Offset Voltage: 350µV Max Input Bias Current: 150nA Max Wide Supply Range: 2.2V to 12.6V Large Output Current: 50mA Typ Low Voltage Noise: 10nV√Hz Typ Slew Rate: 20V/µs Typ Common Mode Rejection: 102dB Typ Power Supply Rejection: 105dB Typ Open-Loop Gain: 100V/mV Typ Operating Temperature Range: – 40°C to 85°C Single in the 8-Pin SO and 5-Pin Low Profile (1mm) ThinSOTTM Packages Dual in the 8-Pin SO and (3mm x 3mm) DFN Packages Quad in the 16-Pin SSOP Package The LT®6220/LT6221/LT6222 are single/dual/quad, low power, high speed rail-to-rail input and output operational amplifiers with excellent DC performance. The LT6220/ LT6221/LT6222 feature reduced supply current, lower input offset voltage, lower input bias current and higher DC gain than other devices with comparable bandwidth. Typically, the LT6220/LT6221/LT6222 have an input offset voltage of less than 100µV, an input bias current of less than 15nA and an open-loop gain of 100V/mV. The parts have an input range that includes both supply rails and an output that swings within 10mV of either supply rail to maximize the signal dynamic range in low supply applications. The LT6220/LT6221/LT6222 maintain performance for supplies from 2.2V to 12.6V and are specified at 3V, 5V and ±5V supplies. The inputs can be driven beyond the supplies without damage or phase reversal of the output. The LT6220 is housed in the 8-pin SO package with the standard op amp pinout as well as the 5-pin SOT-23 package. The LT6221 is available in 8-pin SO and DFN (3mm × 3mm low profile dual fine pitch leadless) packages with the standard op amp pinout. The LT6222 features the standard quad op amp configuration and is available in the 16-Pin SSOP package. The LT6220/ LT6221/ LT6222 can be used as plug-in replacements for many op amps to improve input/output range and performance. , LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. APPLICATIO S ■ ■ ■ ■ ■ ■ Low Voltage, High Frequency Signal Processing Driving A/D Converters Rail-to-Rail Buffer Amplifiers Active Filters Video Amplifiers Fast Current Sensing Amplifiers TYPICAL APPLICATIO 30pF Stepped-Gain Photodiode Amplifier 50 VOS Distribution, VCM = 0V (S8, PNP Stage) VS = 5V, 0V 45 VCM = 0V 40 VS+ PERCENT OF UNITS (%) 10k 3.24k 35 30 25 20 15 10 VS+ 100k IPD PHOTODIODE ~4pF VS+ 1pF – LT6220 VS– 33k LT1634-1.25 VOUT 5 0 –250 –150 150 –50 0 50 INPUT OFFSET VOLTAGE (µV) 250 622012 G01 + VS– VS = ±1.5V TO ± 5V 622012 TA01 U sn622012 622012fs U U 1 LT6220/LT6221/LT6222 ABSOLUTE AXI U RATI GS Total Supply Voltage (VS– to VS+) ......................... 12.6V Input Voltage (Note 2) .............................................. ±VS Input Current (Note 2) ........................................ ±10mA Output Short Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ...–40°C to 85°C Specified Temperature Range (Note 5) ....–40°C to 85°C PACKAGE/ORDER I FOR ATIO TOP VIEW VOUT 1 VS– 2 +IN 3 +– 4 –IN 5 VS+ ORDER PART NUMBER LT6220CS5 LT6220IS5 S5 PART* MARKING LTAFP OUT A 1 –IN A 2 +IN A 3 S5 PACKAGE 5-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 250°C/W (NOTE 10) TOP VIEW OUT A 1 –IN A 2 +IN A 3 VS – 8 A B 7 6 5 VS+ OUT B –IN B +IN B NC –IN +IN VS– 1 2 3 4 – + 4 DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 190°C/W TJMAX = 125°C, θJA = 160°C/W (NOTE 10) EXPOSED PAD INTERNALLY CONNECTED TO V S– (PCB CONNECTION OPTIONAL) ORDER PART NUMBER LT6221CDD LT6221IDD DD PART* MARKING LADZ ORDER PART NUMBER LT6221CS8 LT6221IS8 Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container. 2 U U W WW U W (Note 1) Maximum Junction Temperature .......................... 150°C (DD Package) ................................................... 125°C Storage Temperature .............................–65°C to 150°C (DD Package) ....................................–65°C to 125°C Lead Temperature (Soldering, 10 sec.)................. 300°C TOP VIEW 8 VS + A B VS– 4 7 OUT B 6 –IN B 5 +IN B ORDER PART NUMBER LT6220CS8 LT6220IS8 S8 PART MARKING 6220 6220I TOP VIEW 1 2 3 4 5 6 7 8 B C A D 16 OUT D 15 –IN D 14 +IN D 13 VS– 12 +IN C 11 –IN C 10 OUT C 9 NC S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 190°C/W TOP VIEW 8 7 6 5 NC VS+ VOUT NC OUT A –IN A +IN A VS + +IN B –IN B OUT B NC GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 150°C, θJA = 135°C/W S8 PART MARKING 6221 6221I ORDER PART NUMBER LT6222CGN LT6222IGN SSOP PART MARKING 6222 6222I sn622012 622012fs LT6220/LT6221/LT6222 ELECTRICAL CHARACTERISTICS TA = 25°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted SYMBOL VOS PARAMETER Input Offset Voltage CONDITIONS VCM = 0V VCM = 0V (DD Package) VCM = 0V (S5 Package) VCM = VS VCM = VS (S5 Package) VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VCM = 0V VCM = 0V (DD Package) VCM = 1V VCM = VS VCM = 1V VCM = VS VCM = 1V VCM = VS 0.1Hz to 10Hz f = 10kHz f = 10kHz VS = 5V, VO = 0.5V to 4.5V, RL = 1k at VS/2 VS = 5V, VO = 1V to 4V, RL = 100Ω at VS/2 VS = 3V, VO = 0.5V to 2.5V, RL = 1k at VS/2 VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VS = 2.5V to 10V, VCM = 0V 35 3.5 30 85 82 79 76 0 84 79 No Load ISINK = 5mA ISINK = 20mA No Load ISOURCE = 5mA ISOURCE = 20mA VS = 5V VS = 3V VS = 5V, Frequency = 1MHz VS = 5V, AV = –1, RL= 1k, VO = 4V VS = 5V, AV = 1, VO = 4Vp-p VS = 5V, AV = 1, RL= 1k, VO = 2VP-P, fC = 500kHz 0.01%, VS = 5V, VSTEP = 2V, AV = 1, RL= 1k VS = 5V, AV = 2, RL= 1k VS = 5V, AV = 2, RL= 1k 20 20 35 10 105 105 2.2 5 100 325 5 130 475 45 35 0.9 60 20 1.6 –77.5 300 0.3 0.3 1 2.5 40 200 650 40 250 900 MIN TYP 70 150 200 0.5 0.5 30 15 100 150 15 250 15 20 15 15 0.5 10 0.8 2 100 10 90 102 102 100 100 VS MAX 350 700 850 2.5 3 195 120 600 1100 150 600 175 250 100 100 UNITS µV µV µV mV mV µV µV µV µV nA nA nA nA nA nA µVP-P nV/√Hz pA/√Hz pF V/mV V/mV V/mV dB dB dB dB V dB dB V mV mV mV mV mV mV mA mA mA MHz V/µs MHz dBc ns % Deg sn622012 622012fs ∆VOS Input Offset Voltage Shift Input Offset Voltage Match (Channel-to-Channel) (Note 9) IB Input Bias Current Input Bias Current Match (Channel-to-Channel) (Note 9) IOS Input Offset Current Input Noise Voltage en in CIN AVOL Input Noise Voltage Density Input Noise Current Density Input Capacitance Large Signal Voltage Gain CMRR Common Mode Rejection Ratio CMRR Match (Channel-to-Channel) (Note 9) Input Common Mode Range PSRR Power Supply Rejection Ratio PSRR Match (Channel-to-Channel) (Note 9) Minimum Supply Voltage (Note 6) VOL Output Voltage Swing LOW (Note 7) VOH Output Voltage Swing HIGH (Note 7) ISC IS GBW SR FPBW HD tS ∆G ∆θ Short-Circuit Current Supply Current Per Amplifier Gain-Bandwidth Product Slew Rate Full Power Bandwidth Harmonic Distortion Settling Time Differential Gain (NTSC) Differential Phase (NTSC) 3 LT6220/LT6221/LT6222 ELECTRICAL CHARACTERISTICS SYMBOL VOS PARAMETER Input Offset Voltage The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C temperature range. VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted. CONDITIONS VCM = 0V VCM = 0V (DD Package) VCM = 0V (S5 Package) VCM = VS VCM = VS (S5 Package) VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN TYP 90 180 230 0.5 0.5 30 15 110 180 1.5 3.5 20 275 15 20 15 15 MAX 500 850 1250 3 3.5 280 190 850 1400 5 10 175 800 200 300 125 125 UNITS µV µV µV mV mV µV µV µV µV µV/°C µV/°C nA nA nA nA nA nA V/mV V/mV V/mV dB dB dB dB ∆VOS Input Offset Voltage Shift VOS TC IB Input Offset Voltage Match (Channel-to-Channel) VCM = 0V (Note 9) VCM = 0V (DD Package) Input Offset Voltage Drift (Note 8) (S5 Package) Input Bias Current Input Bias Current Match (Channel-to-Channel) (Note 9) VCM = 1V VCM = VS – 0.2V VCM = 1V VCM = VS – 0.2V VCM = 1V VCM = VS – 0.2V VS = 5V, VO = 0.5V to 4.5V, RL = 1k at VS/2 VS = 5V, VO = 1V to 4V, RL = 100Ω at VS/2 VS = 3V, VO = 0.5V to 2.5V, RL = 1k at VS/2 VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VS = 2.5V to 10V, VCM = 0V IOS AVOL Input Offset Current Large Signal Voltage Gain 30 3 25 82 78 77 73 0 81 76 90 9 80 100 100 100 100 VS 104 104 2.2 8 110 375 8 150 600 2.5 50 220 750 50 300 1100 CMRR Common Mode Rejection Ratio CMRR Match (Channel-to-Channel) (Note 9) Input Common Mode Range V dB dB V mV mV mV mV mV mV mA mA PSRR Power Supply Rejection Ratio PSRR Match (Channel-to-Channel) (Note 9) Minimum Supply Voltage (Note 6) VOL Output Voltage Swing LOW (Note 7) No Load ISINK = 5mA ISINK = 20mA No Load ISOURCE = 5mA ISOURCE = 20mA VS = 5V VS = 3 V VS = 5V, Frequency = 1MHz VS = 5V, AV = –1, RL = 1k, VO = 4VP-P ● ● ● ● ● ● ● ● ● ● ● VOH Output Voltage Swing HIGH (Note 7) ISC IS GBW SR Short-Circuit Current Supply Current Per Amplifier Gain-Bandwidth Product Slew Rate 20 20 30 9 40 30 1 60 18 1.4 mA MHz V/µs sn622012 622012fs 4 LT6220/LT6221/LT6222 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VOS Input Offset Voltage The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C temperature range. VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply unless otherwise noted. (Note 5) CONDITIONS VCM = 0V VCM = 0V (DD Package) VCM = 0V (S5 Package) VCM = VS VCM = VS (S5 Package) VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN TYP 125 300 350 0.75 1 30 30 175 300 1.5 3.5 25 300 15 20 20 20 MAX 700 1300 2000 3.5 4.5 300 210 1200 2200 7.5 15 200 900 250 350 150 150 UNITS µV µV µV mV mV µV µV µV µV µV/°C µV/°C nA nA nA nA nA nA V/mV V/mV V/mV dB dB dB dB ∆VOS Input Offset Voltage Shift VOS TC IB Input Offset Voltage Match (Channel-to-Channel) VCM = 0V (Note 9) VCM = 0V (DD Package) Input Offset Voltage Drift (Note 8) (S5 Package) Input Bias Current Input Bias Current Match (Channel-to-Channel) (Note 9) VCM = 1V VCM = VS – 0.2V VCM = 1V VCM = VS – 0.2V VCM = 1V VCM = VS – 0.2V VS = 5V, VO = 0.5V to 4.5V, RL = 1k at VS/2 VS = 5V, VO = 1.5V to 3.5V, RL = 100Ω at VS/2 VS = 3V, VO = 0.5V to 2.5V, RL= 1k at VS/2 VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VS = 5V, VCM = 0V to 3.5V VS = 3V, VCM = 0V to 1.5V VS = 2.5V to 10V, VCM = 0V IOS AVOL Input Offset Current Large Signal Voltage Gain 25 2.5 20 81 77 76 72 0 79 74 70 8 60 100 100 100 100 VS 104 104 2.2 10 120 220 10 160 325 2.5 60 240 450 60 325 650 CMRR Common Mode Rejection Ratio CMRR Match (Channel-to-Channel) (Note 9) Input Common Mode Range V dB dB V mV mV mV mV mV mV mA mA PSRR Power Supply Rejection Ratio PSRR Match (Channel-to-Channel) (Note 9) Minimum Supply Voltage (Note 6) VOL Output Voltage Swing LOW (Note 7) No Load ISINK = 5mA ISINK = 10mA No Load ISOURCE = 5mA ISOURCE = 10mA VS = 5V VS = 3 V VS = 5V, Frequency = 1MHz VS = 5V, AV = –1, RL = 1k, VO = 4V ● ● ● ● ● ● ● ● ● ● ● VOH Output Voltage Swing HIGH (Note 7) ISC IS GBW SR Short-Circuit Current Supply Current Per Amplifier Gain-Bandwidth Product Slew Rate 12.5 12.5 25 8 30 25 1.1 50 15 1.5 mA MHz V/µs sn622012 622012fs 5 LT6220/LT6221/LT6222 ELECTRICAL CHARACTERISTICS TA = 25°C, VS = ±5V, VCM = 0V, VOUT = 0V, unless otherwise noted. SYMBOL VOS PARAMETER Input Offset Voltage CONDITIONS VCM = – 5V VCM = – 5V (DD Package) VCM = – 5V (S5 Package) VCM = 5V VCM = 5V (S5 Package) VCM = – 5V to 3.5V MIN TYP 80 150 200 0.7 0.7 70 100 150 20 250 15 20 15 15 0.5 10 0.8 2 35 3.5 82 77 VS VS+ = 2.5V to 10V, VS–= 0V, VCM = 0V No Load ISINK = 5mA ISINK = 20mA No Load ISOURCE = 5mA ISOURCE = 20mA 25 Frequency = 1MHz AV = – 1, RL = 1k, VO = ±4V, Measure at VO = ±2V VO = 8VP-P AV = 1, RL= 1k, VO = 2Vp-p, fc = 500kHz 0.01%, VSTEP = 5V, AV = 1, RL = 1k AV = 2 , RL = 1 k AV = 2 , RL = 1 k – MAX 500 750 900 2.5 3 675 850 1300 150 700 175 250 100 100 UNITS µV µV µV mV mV µV µV µV nA nA nA nA nA nA µVP-P nV/√Hz pA/√Hz pF V/mV V/mV dB dB ∆VOS Input Offset Voltage Shift Input Offset Voltage Match (Channel-to-Channel) VCM = – 5V VCM = – 5V (DD Package) IB Input Bias Current Input Bias Current Match (Channel-to-Channel) IOS Input Offset Current Input Noise Voltage en in CIN AVOL CMRR Input Noise Voltage Density Input Noise Current Density Input Capacitance Large Signal Voltage Gain Common Mode Rejection Ratio CMRR Match (Channel-to-Channel) Input Common Mode Range PSRR VOL Power Supply Rejection Ratio PSRR Match (Channel-to-Channel) Output Voltage Swing LOW (Note 7) VCM = – 4V VCM = 5V VCM = – 4V VCM = 5V VCM = – 4V VCM = 5V 0.1Hz to 10Hz f = 10kHz f = 10kHz f = 100kHz VO = – 4V to 4V, RL = 1k VO = – 2V to 2V, RL = 100Ω VCM = – 5V to 3.5V 95 10 102 100 VS 105 105 5 100 325 5 130 475 50 1 60 20 0.8 –77.5 375 0.15 0.6 1.5 40 200 650 40 250 900 + V dB dB mV mV mV mV mV mV mA mA MHz V/µs MHz dBc ns % Deg 84 79 VOH Output Voltage Swing HIGH (Note 7) ISC IS GBW SR FPBW HD tS ∆G ∆θ Short-Circuit Current Supply Current Per Amplifier Gain-Bandwidth Product Slew Rate Full Power Bandwidth Harmonic Distortion Settling Time Differential Gain (NTSC) Differential Phase (NTSC) sn622012 622012fs 6 LT6220/LT6221/LT6222 The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C temperature range. VS = ±5V, VCM = 0V, VOUT = 0V, unless otherwise noted. SYMBOL VOS PARAMETER Input Offset Voltage CONDITIONS VCM = – 5V VCM = – 5V (DD Package) VCM = – 5V (S5 Package) VCM = 5V VCM = 5V (S5 Package) VCM = – 5V to 3.5V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN TYP 100 180 230 0.75 0.75 90 90 180 1.5 3.5 20 275 15 20 15 15 MAX 650 900 1300 3 3.5 850 1100 1500 5 10 175 800 200 300 125 125 UNITS µV µV µV mV mV µV µV µV µV/°C µV/°C nA nA nA nA nA nA V/mV V/mV dB dB ∆VOS Input Offset Voltage Shift Input Offset Voltage Match (Channel-to-Channel) VCM = – 5V (Note 9) VCM = – 5V (DD Package) VOS TC IB Input Offset Voltage Drift (Note 8) (S5 Package) Input Bias Current Input Bias Current Match (Channel-to-Channel) (Note 9) IOS AVOL CMRR Input Offset Current Large Signal Voltage Gain Common Mode Rejection Ratio CMRR Match (Channel-to-Channel) (Note 9) Input Common Mode Range PSRR VOL Power Supply Rejection Ratio PSRR Match (Channel-to-Channel) (Note 9) Output Voltage Swing LOW (Note 7) No Load ISINK = 5mA ISINK = 20mA No Load ISOURCE = 5mA ISOURCE = 20mA VS+ = 2.5V to 10V, VS– = 0V, VCM = 0V VCM = – 4V VCM = 4.8V VCM = – 4V VCM = 4.8V VCM = – 4V VCM = 4.8V VO = – 4V to 4V, RL = 1k VO = – 2V to 2V, RL =100Ω VCM = – 5V to 3.5V 30 3 80 75 V S– 81 76 90 9 100 100 V S+ 104 104 8 110 375 8 150 600 50 220 750 50 300 1100 2 V dB dB mV mV mV mV mV mV mA mA MHz V/µs ● ● ● ● ● ● ● ● ● ● VOH Output Voltage Swing HIGH (Note 7) ISC IS GBW SR Short-Circuit Current Supply Current Per Amplifier Gain-Bandwidth Product Slew Rate Frequency = 1MHz AV = – 1, RL = 1k, VO = ±4V, Measure at VO = ±2V 20 40 1.2 60 18 ● ● sn622012 622012fs 7 LT6220/LT6221/LT6222 The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C temperature range. VS = ±5V, VCM = 0V, VOUT = 0V, unless otherwise noted. (Note 5) SYMBOL VOS PARAMETER Input Offset Voltage CONDITIONS VCM = – 5V VCM = – 5V (DD Package) VCM = – 5V (S5 Package) VCM = 5V VCM = 5V (S5 Package) VCM = – 5V to 3.5V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN TYP 150 300 350 0.75 1 90 175 300 1.5 3.5 25 300 15 20 20 20 MAX 800 1300 2000 3.5 4.5 950 1350 2200 7.5 15 200 900 250 350 150 150 UNITS µV µV µV mV mV µV µV µV µV/°C µV/°C nA nA nA nA nA nA V/mV V/mV dB dB ∆VOS Input Offset Voltage Shift VOS TC IB Input Offset Voltage Match (Channel-to-Channel) VCM = – 5V (Note 9) VCM = – 5V (DD Package) Input Offset Voltage Drift (Note 8) (S5 Package) Input Bias Current Input Bias Current Match (Channel-to-Channel) (Note 9) VCM = –4V VCM = 4.8V VCM = –4V VCM = 4.8V VCM = –4V VCM = 4.8V VO = – 4V to 4V, RL = 1k VO = – 1V to 1V, RL = 100Ω VCM = – 5V to 3.5V IOS AVOL CMRR Input Offset Current Large Signal Voltage Gain Common Mode Rejection Ratio CMRR Match (Channel-to-Channel) (Note 9) Input Common Mode Range 25 2.5 79 74 –5 79 74 70 8 100 100 5 104 104 10 120 220 10 160 325 60 240 450 60 325 650 2.25 V dB dB mV mV mV mV mV mV mA mA MHz V/µs PSRR VOL Power Supply Rejection Ratio PSRR Match (Channel-to-Channel) (Note 9) Output Voltage Swing LOW (Note 7) VS+ = 2.5V to 10V, VS– = 0V, VCM = 0V No Load ISINK = 5mA ISINK = 10mA No Load ISOURCE = 5mA ISOURCE = 10mA ● ● ● ● ● ● ● ● ● ● VOH Output Voltage Swing HIGH (Note 7) ISC IS GBW SR Short-Circuit Current Supply Current Gain-Bandwidth Product Slew Rate Frequency = 1MHz AV = – 1, RL = 1k, VO = ±4V, Measure at VO = ±2V 12.5 30 1.4 50 15 ● ● Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes. If the differential input voltage exceeds 1.4V, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 4: The LT6220C/LT6221C/LT6222C and LT6220I/LT6221I/LT6222I are guaranteed functional over the temperature range of –40°C and 85°C. Note 5: The LT6220C/LT6221C/LT6222C are guaranteed to meet specified performance from 0°C to 70°C. The LT6220C/LT6221C/LT6222C are designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT6220I/LT6221I/LT6222I are guaranteed to meet specified performance from –40°C to 85°C. Note 6: Minimum supply voltage is guaranteed by power supply rejection ratio test. Note 7: Output voltage swings are measured between the output and power supply rails. Note 8: This parameter is not 100% tested. Note 9: Matching parameters are the difference between amplifiers A and D and between B and C on the LT6222; between the two amplifiers on the LT6221. Note 10: Thermal resistance (θJA) varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. If desired, the thermal resistance can be substantially reduced by connecting Pin 2 of the LT6220CS5/LT6220IS5 or the underside metal of DD packages to a larger metal area (VS– trace). sn622012 622012fs 8 LT6220/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS VOS Distribution, VCM = 0V (S8, PNP Stage) 50 VS = 5V, 0V 45 VCM = 0V 40 50 PERCENT OF UNITS (%) PERCENT OF UNITS (%) 35 30 25 20 15 10 5 0 –250 –150 150 –50 0 50 INPUT OFFSET VOLTAGE (µV) 250 622012 G01 35 30 25 20 15 10 5 0 –1000 –600 600 –200 0 200 INPUT OFFSET VOLTAGE (µV) 1000 622012 G02 PERCENT OF UNITS (%) VOS Distribution, VCM = 5V (SOT5, NPN Stage) 50 SUPPLY CURRENT PER AMPLIFIER (mA) VS = 5V, 0V 45 VCM = 5V 40 PERCENT OF UNITS (%) OFFSET VOLTAGE (µV) 35 30 25 20 15 10 5 0 –3000 –1800 1800 –600 0 600 INPUT OFFSET VOLTAGE (µV) 3000 Input Bias Current vs Common Mode Voltage 400 300 VS = 5V, 0V TA = 25°C TA = – 55°C 0.6 0.5 INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (µA) 200 100 0 –100 –200 –300 –400 –500 –600 0 1 3 4 5 2 COMMON MODE VOLTAGE (V) 6 622012 G07 OUTPUT SATURATION VOLTAGE (V) TA = 125°C UW 622012 G04 VOS Distribution, VCM = 0V (SOT5, PNP Stage) VS = 5V, 0V 45 VCM = 0V 40 50 VOS Distribution, VCM = 5V (S8, NPN Stage) VS = 5V, 0V 45 VCM = 5V 40 35 30 25 20 15 10 5 0 –2000 –1200 1200 –400 0 400 INPUT OFFSET VOLTAGE (µV) 2000 622012 G03 Supply Current vs Supply Voltage 3 700 500 300 Offset Voltage vs Input Common Mode Voltage VS = 5V, 0V TYPICAL PART 2 TA = 125°C TA = 25°C 1 TA = – 55°C 0 TA = – 55°C 100 –100 TA = 125°C –300 –500 –700 TA = 25°C 0 1 2 3 4 5 6 7 8 9 10 11 12 TOTAL SUPPLY VOLTAGE (V) 622012 G05 0 4 1 3 2 INPUT COMMON MODE VOLTAGE (V) 5 622012 G06 Input Bias Current vs Temperature VS = 5V, 0V Output Saturation Voltage vs Load Current (Output Low) 10 VS = 5V, 0V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –55 –25 35 5 65 TEMPERATURE (°C) 95 125 PNP ACTIVE VCM = 1V NPN ACTIVE VCM = 5V 1 TA = 125°C 0.1 TA = 25°C 0.01 TA = – 55°C 0.1 1 10 LOAD CURRENT (mA) 100 622012 G09 0.001 0.01 622012 G08 sn622012 622012fs 9 LT6220/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS Output Saturation Voltage vs Load Current (Output High) 10 VS = 5V, 0V CHANGE IN OFFSET VOLTAGE (mV) OUTPUT SHORT-CIRCUIT CURRENT (mA) OUTPUT SATURATION VOLTAGE (V) 1 0.1 TA = 25°C 0.01 TA = 125°C TA = – 55°C 0.1 1 10 LOAD CURRENT (mA) 100 622012 G10 0.001 0.01 Open-Loop Gain 1000 CHANGE IN OFFSET VOLTAGE (µV) 800 600 400 200 0 –200 –400 –600 –800 –1000 0 0.5 1.5 2 1 OUTPUT VOLTAGE (V) 2.5 3 RL = 100Ω RL = 1k CHANGE IN OFFSET VOLTAGE (µV) 600 400 200 0 –200 –400 –600 –800 RL = 1k RL = 100Ω CHANGE IN OFFSET VOLTAGE (µV) VS = 3V, 0V RL TO GND Offset Voltage vs Output Current 2.0 VS = ± 5V 10 CHANGE IN OFFSET VOLTAGE (mV) CHANGE IN OFFSET VOLTAGE (µV) 1.5 1.0 0.5 0 –0.5 TA = 125°C –1.0 –1.5 –2.0 –75 –60 –45 –30 –15 0 15 30 45 60 75 OUTPUT CURRENT (mA) 622012 G16 NOISE VOLTAGE (nV/√Hz) TA = – 55°C TA = 25°C 10 UW 622012 G13 Minimum Supply Voltage 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 1 1.5 2 2.5 3 3.5 4 4.5 TOTAL SUPPLY VOLTAGE (V) 5 5.5 TA = – 55°C TA = 25°C TA = 125°C 70 60 50 40 30 20 10 0 –10 –20 –30 –40 –50 –60 –70 Output Short-Circuit Current vs Power Supply Voltage TA = 25°C TA = 125°C TA = – 55°C SINKING TA = – 55°C SOURCING TA = 125°C 5 TA = 25°C 1.5 2 4 2.5 4.5 3.5 3 POWER SUPPLY VOLTAGE (± V) 622012 G11 622012 G12 Open-Loop Gain 1000 800 VS = 5V, 0V RL TO GND 1000 800 600 400 200 0 –200 –400 –600 –800 0 0.5 1 1.5 2 2.5 3 3.5 4 OUTPUT VOLTAGE (V) 4.5 6 –1000 Open-Loop Gain VS = ±5V RL TO GND RL = 1k RL = 100Ω –1000 –5 –4 –3 –2 –1 0 1 2 3 OUTPUT VOLTAGE (V) 4 5 622012 G14 622012 G15 Warm-Up Drift vs Time 40 35 30 25 20 15 10 5 8 6 4 2 0 –2 –4 –6 –8 –10 0 LT6222 GN16 VS = ±5V LT6220 SOT5 VS = ±5V LT6221 S8 VS = ±5V LT6222 GN16 VS = ±2.5V LT6220 SOT5 VS = ±2.5V LT6221 S8 VS = ±2.5V Input Noise Voltage vs Frequency VS = 5V, 0V NPN ACTIVE VCM = 4.25V PNP ACTIVE VCM = 2.5V 0.1 1 10 FREQUENCY (kHz) 100 622012 G18 5 10 15 20 25 30 35 40 45 50 TIME AFTER POWER-UP (SECONDS) 622012 G17 0 0.01 sn622012 622012fs LT6220/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS Input Current Noise vs Frequency 3.0 VS = 5V, 0V OUTPUT NOISE VOLTAGE (nV) 800 600 2.5 NOISE CURRENT (pA/√Hz) GAIN BANDWIDTH (MHz) 2.0 1.5 1.0 0.5 0 0.01 PNP ACTIVE VCM = 2.5V NPN ACTIVE VCM = 4.25V 0.1 1 10 FREQUENCY (kHz) 100 622012 G19 Gain Bandwidth and Phase Margin vs Temperature 90 80 GAIN BANDWIDTH (MHz) 80 70 70 60 50 GAIN BANDWIDTH PRODUCT VS = ±2.5V VS = ±5V 70 VS = ±5V VS = ±2.5V 60 50 40 30 SLEW RATE (V/µs) GAIN (dB) PHASE MARGIN –55 –25 35 65 5 TEMPERATURE (°C) Gain vs Frequency (AV = 1) 15 12 9 6 GAIN (dB) GAIN (dB) AV = 1 CL = 10pF RL = 1k 6 VS = ±2.5V VS = ± 5V 3 0 –3 –6 –9 –12 1 10 FREQUENCY (MHz) 100 622012 G25 OUTPUT IMPEDACNE (Ω) 3 0 –3 –6 –9 –12 –15 0.1 UW 95 622012 G22 0.1Hz to 10Hz Output Voltage Noise VS = 5V, 0V 90 80 70 60 50 Gain Bandwidth and Phase Margin vs Supply Voltage TA = 25°C GAIN BANDWIDTH PRODUCT 400 200 0 –200 –400 –600 –800 0 1 2 3 4567 TIME (SECONDS) 8 9 10 PHASE MARGIN (DEG) 70 PHASE MARGIN 60 50 40 30 20 0 1 2345678 TOTAL SUPPLY VOLTAGE (V) 9 10 622012 G20 622012 G21 Gain and Phase vs Frequency 120 100 PHASE VS = ±5V VS = ±2.5V GAIN VS = ±2.5V 80 60 25 30 Slew Rate vs Temperature AV = –1 RF = RG = 1k RL = 1k VS = ± 5V 60 PHASE MARGIN (DEG) 50 40 30 20 10 0 –10 –20 10k 100k PHASE (DEG) 40 20 0 VS = ±5V VS = ±2.5V 20 –20 –40 –60 –80 20 125 1M 10M FREQUENCY (Hz) 100M 622012 G23 15 –55 –25 5 35 65 TEMPERATURE (°C) 95 125 622012 G24 Gain vs Frequency (AV = 2) 15 12 9 100 10 1 1000 Output Impedance vs Frequency VS = ± 2.5V AV = 10 VS = ±2.5V VS = ± 5V AV = 2 RF = RG = 1k CF = 20pF CL = 10pF RL = 1k 1 10 FREQUENCY (MHz) 100 622012 G26 AV = 2 0.1 0.01 AV = 1 –15 0.1 0.001 0.1 1 10 FREQUENCY (MHz) 100 620012 G27 sn622012 622012fs 11 LT6220/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS Common Mode Rejection Ratio vs Frequency 120 COMMON MODE REJECTION RATIO (dB) POWER SUPPLY REJECTION RATIO (dB) VS = 5V, 0V 100 80 60 40 20 0 0.01 OVERSHOOT (%) 0.1 1 10 FREQUENCY (MHz) Series Output Resistor vs Capacitive Load VS = 5V, 0V 45 AV = 2 RL = ∞, UNLESS NOTED 40 DISTORTION (dBc) 50 DISTORTION (dBc) OVERSHOOT (%) 35 30 25 20 15 10 5 0 10 ROS = 20Ω ROS = RL = 50Ω 100 1000 CAPACITIVE LOAD (pF) 10000 622012 G32 ROS = 10Ω Maximum Undistorted Output Signal vs Frequency 5.0 4.5 4.0 AV = –1 3.5 3.0 2.5 2.0 1.5 V = 5V, 0V S RL = 1k 1.0 0 0.1 1 0.01 FREQUENCY (MHz) 1V/DIV OUTPUT VOLTAGE SWING (VP-P) 12 UW 622012 G28 Power Supply Rejection Ratio vs Frequency 120 VS = 5V, 0V 100 80 60 40 20 0 0.001 POSITIVE SUPPLY Series Output Resistor vs Capacitive Load 50 VS = 5V, 0V 45 AV = 1 RL = ∞, UNLESS NOTED 40 35 30 25 20 15 10 5 ROS = 20Ω ROS = RL = 50Ω ROS = 10Ω NEGATIVE SUPPLY 100 0.01 0.1 1 FREQUENCY (MHz) 10 100 622012 G29 0 10 100 1000 CAPACITIVE LOAD (pF) 10000 622012 G31 Distortion vs Frequency VS = 5V, 0V –40 AV = 1 VOUT = 2VP-P –50 –60 –70 –80 –90 –100 –110 0.01 RL = 150Ω, 3RD RL = 1k, 2ND RL = 1k, 3RD RL = 150Ω, 2ND –30 –30 –40 –50 –60 –70 –80 –90 –100 10 622012 G33 Distortion vs Frequency VS = 5V, 0V AV = 2 VOUT = 2VP-P RL = 150Ω, 3RD RL = 150Ω, 2ND RL = 1k, 3RD RL = 1k, 2ND 0.1 1 FREQUENCY (MHz) –110 0.01 0.1 1 FREQUENCY (MHz) 10 622012 G34 5V Large-Signal Response 5V Small-Signal Response AV = 2 50mV/DIV 2.5V 0V VS = 5V, 0V AV = 1 RL = 1k 100ns/DIV 622012 G36 VS = 5V, 0V AV = 1 RL = 1k 50ns/DIV 622012 G37 10 622012 G35 sn622012 622012fs LT6220/LT6221/LT6222 TYPICAL PERFOR A CE CHARACTERISTICS ± 5V Large-Signal Response ± 5V Small-Signal Response Output Overdriven Recovery 2V/DIV 0V VS = ± 5V AV = 1 RL = 1k 200ns/DIV APPLICATIO S I FOR ATIO Circuit Description The LT6220/LT6221/LT6222 have an input and output signal range that covers from the negative power supply to the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage comprises two differential amplifiers, a PNP stage, Q1/Q2, and an NPN stage, Q3/Q4, that are active over different ranges of common mode input voltage. The PNP stage is active between the negative supply to approximately 1.2V below the positive supply. As the input voltage moves closer toward the positive supply, the transistor Q5 will steer the V+ V+ V– ESDD2 D1 + I2 +IN ESDD1 D6 D5 –IN ESDD4 V– Q16 Q17 Q18 V+ ESDD3 D8 D7 Q4 Q19 V– Figure 1. LT6220/LT6221/LT6222 Simplified Schematic Diagram sn622012 622012fs U W UW 622012 G38 50mV/DIV 0V VIN 1V/DIV 0V VOUT 2V/DIV 0V VS = ±5V AV = 1 RL = 1k 50ns/DIV 622012 G39 VS = 5V, 0V AV = 2 RL = 1k 200ns/DIV 622012 G40 UU tail current, I1, to the current mirror, Q6/Q7, activating the NPN differential pair and the PNP pair becomes inactive for the rest of the input common mode range up to the positive supply. Also, at the input stage, devices Q17 to Q19 act to cancel the bias current of the PNP input pair. When Q1/Q2 are active, the current in Q16 is controlled to be the same as the current Q1/Q2. Thus, the base current of Q16 is nominally equal to the base current of the input devices. The base current of Q16 is then mirrored by devices Q17-Q19 to cancel the base current of the input devices Q1/Q2. R3 R4 R5 + I1 Q11 Q12 Q13 C2 Q15 D2 Q5 VBIAS CC + I3 OUT V– Q3 Q1 D3 Q2 BUFFER AND OUTPUT BIAS Q9 Q8 C1 Q10 D4 Q7 Q6 R1 R2 Q14 622012 F01 13 LT6220/LT6221/LT6222 APPLICATIO S I FOR ATIO A pair of complementary common emitter stages Q14/Q15 that enable the output to swing from rail-to-rail construct the output stage. The capacitors C2 and C3 form the local feedback loops that lower the output impedance at high frequency. These devices are fabricated by Linear Technology’s proprietary high speed complementary bipolar process. Power Dissipation The LT6222, with four amplifiers, is housed in a small 16-lead SSOP package and typically has a thermal resistance (θJA) of 135°C/W. It is necessary to ensure that the die’s junction temperature does not exceed 150°C. The junction temperature, TJ, is calculated from the ambient temperature, TA, power dissipation, PD, and thermal resistance, θJA: TJ = TA + (PD • θJA) The power dissipation in the IC is the function of the supply voltage, output voltage and the load resistance. For a given supply voltage, the worst-case power dissipation PD(MAX) occurs when the maximum supply current and the output voltage is at half of either supply voltage for a given load resistance. PD(MAX) is given by: PD(MAX) = VS • IS(MAX) ( ) ⎛V ⎞ + ⎜ S ⎟ / RL ⎝ 2⎠ 2 Example: For an LT6222 in a 16-lead SSOP package operating on ±5V supplies and driving a 100Ω load, the worst-case power dissipation is given by: PD(MAX) /Amp = (10 • 1.8mA ) + (2.5) / 100 = 0.018 + 0.0625 = 80.5mW If all four amplifiers are loaded simultaneously, then the total power dissipation is 322mW. The maximum ambient temperature at which the part is allowed to operate is: TA = TJ – (PD(MAX) • 135°C/W) = 150°C – (0.322W • 135°C/W) = 106.5°C 2 14 U Input Offset Voltage The offset voltage will change depending upon which input stage is active. The PNP input stage is active from the negative supply rail to 1.2V below the positive supply rail, then the NPN input stage is activated for the remaining input range up to the positive supply rail during which the PNP stage remains inactive. The offset voltage is typically less than 70µV in the range that the PNP input stage is active. Input Bias Current The LT6220/LT6221/LT6222 employ a patent pending technique to trim the input bias current to less than 150nA for the input common mode voltage of 0.2V above the negative supply rail to 1.2V below the positive rail. The low input offset voltage and low input bias current of the LT6220/LT6221/LT6222 provide precision performance especially for high source impedance applications. Output The LT6220/LT6221/LT6222 can deliver a large output current, so the short-circuit current limit is set around 50mA to prevent damage to the device. Attention must be paid to keep the junction temperature of the IC below the absolute maximum rating of 150°C (refer to the Power Dissipation section) when the output is in continuous short circuit. The output of the amplifier has reversebiased diodes connected to each supply. If the output is forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to several hundred milliamperes, no damage will occur to the device. Overdrive Protection When the input voltage exceeds the power supplies, two pair of crossing diodes, D1 to D4, will prevent the output from reversing polarity. If the input voltage exceeds either power supply by 700mV, diode D1/D2 or D3/D4 will turn on to keep the output at the proper polarity. For the phase reversal protection to perform properly, the input current must be limited to less than 5mA. If the amplifier is sn622012 622012fs W UU LT6220/LT6221/LT6222 APPLICATIO S I FOR ATIO severely overdriven, an external resistor should be used to limit the overdriven current. The LT6220/LT6221/LT6222’s input stages are also protected against a large differential input voltage of 1.4V or higher by a pair of back-to-back diodes, D5/D8, to prevent the emitter-base breakdown of the input transistors. The current in these diodes should be limited to less than 10mA when they are active. The worse-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity-gain configuration. In addition, the amplifier is protected against ESD strikes up to 3kV on all pins by a pair of protection diodes on each pin that are connected to the power supplies as shown in Figure 1. Capacitive Load The LT6220/LT6221/LT6222 are optimized for high bandwidth, low power and precision applications. They can drive a capacitive load up to 100pF in a unity-gain configuration and more for higher gain. When driving a larger TYPICAL APPLICATIO S Stepped-Gain Photodiode Amplifier The circuit of Figure 2 is a stepped gain transimpedance photodiode amplifier. At low signal levels, the circuit has a high 100kΩ gain, but at high signal levels the circuit automatically and smoothly changes to a low 3.2kΩ gain. The benefit of a stepped gain approach is that it maximizes dynamic range, which is very useful on limited supplies. Put another way, in order to get 100kΩ sensitivity and still handle a 1mA signal level without resorting to gain reduction, the circuit would need a 100V negative voltage supply. The operation of the circuit is quite simple. At low photodiode currents (below 10µA) the output and inverting input of the op amp will be no more than 1V below ground. The LT1634 in parallel with R3 and Q2 keep a constant current though Q2 of about 20µA. R4 maintains quiescent current through the LT1634 and pulls Q2’s emitter above ground, so Q1 is reverse biased and no current flows through R2. So for small signals, the only feedback path is R1 (and C1) and the circuit is a simple transimpedance amplifier with 100kΩ gain. VS+ R2 3.24k C2 30pF PHILIPS BCV62 3 VS+ R1 100k IPD PHOTODIODE ~4pF VS+ 4 R4 10k U capacitive load, a resistor of 10Ω to 50Ω should be connected between the output and the capacitive load to avoid ringing or oscillation. The feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. Graphs on capacitive loads show the transient response of the amplifier when driving capacitive load with specified series resistors. Feedback Components When feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. For instance, the LT6220/ LT6221/LT6222, set up with a noninverting gain of 2, two 5k resistors and a capacitance of 5pF (part plus PC board), will probably oscillate. The pole is formed at 12.7MHz that will reduce phase margin by 52 degrees when the crossover frequency of the amplifier is around 10MHz. A capacitor of 10pF or higher connecting across the feedback resistor will eliminate any ringing or oscillation. C1 1pF Q1 Q2 W U UU – LT6220 2 VS– 1 R3 33k LT1634-1.25 VOUT + VS– VS = ±1.5V TO ± 5V 622012 F02 Figure 2. Stepped-Gain Photodiode Amplifier sn622012 622012fs 15 LT6220/LT6221/LT6222 PACKAGE DESCRIPTIO As the signal level increases though, the output of the op amp goes more negative. At 12.5µA of photodiode current, the 100kΩ gain dictates that the LT6220 output will be about 1.25V below ground. However, at that point the emitter of Q2 will be at ground, and the base of Q1 will be 1V below ground. Thus, Q1 turns on and photodiode current starts to flow through R2. The transimpedance gain is therefore now reduced to R1||R2, or about 3.1kΩ. The circuit response is shown in Figure 3. Note the smooth transition between the two operating gains, as well as the linearity. PHOTO CURRENT 100µA/DIV GAIN (dB) VOUT 0.5V/DIV 5µs/DIV Figure 3. Stepped-Gain Photodiode Amplifier Response Single 3V Supply, 1MHz, 4th Order Butterworth Filter The circuit shown in Figure 4 makes use of the low voltage operation and the wide bandwidth of the LT6221 to create a DC accurate 1MHz 4th order lowpass filter powered from a 3V supply. The amplifiers are configured in the inverting mode for the lowest distortion and the output can swing rail-to-rail for maximum dynamic range. Figure 5 displays the frequency response of the filter. Stopband attenuation is greater than 100dB at 50MHz. 909Ω 909Ω VIN 220pF 2.67k 1/2 LT6221 470pF VS/2 622012 F04 Figure 4. 3V, 1MHz, 4th Order Butterworth Filter sn622012 622012fs 16 + – + – U 20 0 –20 –40 –60 –80 –100 –120 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 622012 F05 Figure 5. Frequency Response of Filter Differential-In/Differential-Out Amplifier The circuit of Figure 6 shows the LT6222 applied as a buffered differential-in differential-out amplifier with a gain of 2. Op amps A and B are configured as simple unitygain buffers, offering high input impedance to upstream circuitry. Resistors R1 and R2 perform an averaging function on the common mode input voltage and R3 attenuates it by a factor of 2/3 and references it to the voltage source VOCM. The resultant voltage, VMID = 2/3 • VICM, is placed at the noninverting inputs of op amps C and D. The other four resistors set gains of +3 from the noninverting input and –2 through the inverting path. Thus the output voltage of the upper path is: –OUT = 3 • (2/3 • VICM + 1/3 • VOCM) – 2 • (VICM + VDIFF/2) = 2VICM + VOCM – 2VICM – VDIFF = VOCM – VDIFF 622012 F03 47pF 1.1k 1.1k 2.21k 22pF 3V 1/2 LT6221 VOUT LT6220/LT6221/LT6222 PACKAGE DESCRIPTIO and the output of the lower path is: +OUT = 3 • (2/3 • VICM + 1/3 • VOCM) – 2 • (VICM – VDIFF/2) = 2VICM + VOCM – 2VICM + VDIFF = VOCM + VDIFF Note that the input common mode voltage does not appear in the output as either a common mode or a difference mode term. However the voltage VOCM does appear in the output terms, and with the same polarity, so it sets up the output DC level. Also, the differential input voltage VDIFF appears fully at both outputs with opposite polarity, giving PACKAGE DESCRIPTIO 0.675 ± 0.05 3.5 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (NOTE 6) U U rise to the effective differential gain of 2. Calculations show that using 1% resistors gives worst-case input common mode feedthrough better than –31dB, whether looking at the output common mode or difference mode. Considering the 6dB of gain, worst-case common mode rejection ratio is 37dB. (Remember this is assuming 1% resistors. Of course, this can be improved with more precise resistors.) Results achieved on the bench with typical 1% resistors showed 67dB of CMRR at low frequency and 40dB CMRR at 1MHz. Gains other than 2 can be achieved by setting R3 = α • (R1||R2), R5 = α • R4 and R7 = α • R6 where gain = α. DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD8) DFN 1203 0.200 REF 0.75 ± 0.05 4 0.25 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE sn622012 622012fs 17 LT6220/LT6221/LT6222 PACKAGE DESCRIPTIO U S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635) 0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 TYP 5 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 1.00 MAX DATUM ‘A’ 0.01 – 0.10 0.09 – 0.20 (NOTE 3) 1.90 BSC S5 TSOT-23 0302 3.85 MAX 2.62 REF 0.30 – 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 sn622012 622012fs 18 LT6220/LT6221/LT6222 PACKAGE DESCRIPTIO U S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .045 ±.005 .050 BSC 8 .189 – .197 (4.801 – 5.004) NOTE 3 7 6 5 .160 ±.005 .228 – .244 (5.791 – 6.197) .150 – .157 (3.810 – 3.988) NOTE 3 1 2 3 4 .053 – .069 (1.346 – 1.752) 0°– 8° TYP .004 – .010 (0.101 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .245 MIN .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0303 GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0165 ± .0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE .0532 – .0688 (1.35 – 1.75) 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 sn622012 622012fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT6220/LT6221/LT6222 TYPICAL APPLICATIO U 5.6pF VICM + VDIFF/2 +IN R5 2k + A 1/4 LT6222 R4 1k VS+ – R1 2k VMID R2 2k R6 1k – D 1/4 LT6222 R3 2k –OUT + VOCM VICM – VDIFF/2 –IN + C 1/4 LT6222 +OUT + B 1/4 LT6222 – VS– 5.6pF 622012 F06 – R7 2k VS = ±1.3V TO ± 6V BW ≅ 11MHz Figure 6. Buffered Gain of 2 Differential-In/Differential-Out Amplifier RELATED PARTS PART NUMBER LT1498/LT1499 DESCRIPTION Dual/Quad 10MHz, 6V/µs Rail-to-Rail Input/ Output CLOAD Op Amps COMMENTS High DC Accuracy, 475µV VOS(MAX) Max Supply Current 2.2mA/Amp, Wide Supply Range, 2.2V to 30V LT1800/LT1801/LT1802 Single/Dual/Quad 80MHz, 25V/µs, 350µV VOS(MAX), 250nA IBIAS(MAX), Max Supply Current 2mA/Amp Low Power Rail-to-Rail Input/Output Precision Op Amps LT1803/LT1804/LT1805 Single/Dual/Quad 85MHz, 100V/µs Rail-to-Rail Input/Output Op Amps LT1806/LT1807 LT1809/LT1810 Single/Dual 325MHz, 140V/µs Rail-to-Rail Input/ Output Op Amps 2mV VOS(MAX), Max Supply Current 3mA/Amp High DC Accuracy, 550µV VOS(MAX) Max Low Noise 3.5nV/√Hz Low Distortion – 80dBc at 5MHz, Power Down (LT1806) Single/Dual 180MHz, Rail-to-Rail Input/Output Op Amps 350V/µs Slew Rate, Low Distortion –90dBc at 5MHz, Power Down (LT1809) sn622012 622012fs 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● LT/TP 0204 1K • PRINTED IN USA FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003