LT6350IMS8PBF

FEATURES n n n n n n n n n n n n n n LT6350 Low Noise Single-Ended to Differential Converter/ADC Driver DESCRIPTION The LT®6350 is a rail-to-rail input and output low noise single-ended to differential converter/ADC driver featuring fast settling time. It converts a high or low impedance, single-ended input signal to a low impedance, balanced, differential output suitable for driving high performance differential succesive approximation register (SAR) ADCs. The two op amp topology features very low noise op amps, that can support SNR >110dB in a 1MHz bandwidth. The input op amp is trimmed for constant low input-referred voltage offset over the input range to prevent VOS steps from degrading distortion. On a single 5V supply, the outputs can drive ADCs from 55mV to 4.945V on each input. With the addition of a negative supply, the LT6350 can drive ADCs from 0V to 4.945V on each input. Output common mode voltage is set by applying a voltage to the +IN2 pin. The LT6350 draws 4.8mA from a 5V supply and consumes just 60μA in shutdown mode. The LT6350 is available in a compact 3mm × 3mm, 8-pin leadless DFN package and also in an 8-pin MSOP package and operates over a –40°C to 125°C temperature range. Rail-to-Rail Input and Outputs Fast Settling Time: 240ns, 0.01%, 8VP-P Output Step 1.9nV/√Hz Input-Referred Op Amp Noise High Impedance Input –3dB Bandwidth: 33MHz 2.7V to 12V Supply Operation No External Gain-Resistors Required 4.8mA Supply Current Low Power Shutdown Low Distortion (HD2/HD3): –102dBc/–97dBc at 100kHz, VOUTDIFF = 4VP-P Low Offset Voltage: ±400μV Max High DC Linearity: 1 VS = 5V RL = 2k RF + RG = 2k FOR AVDIFF > 2 DIFFERENTIAL GAIN (dB) 5 AV1 = 10 20 AV1 = 5 10 0 AV1 = 2 AV1 = 1 –5 0 –10 TA = 85°C TA = 25°C TA = – 40°C 1 10 100 FREQUENCY (MHz) 1000 6350 G38 –15 0.1 –10 0.1 1 10 100 FREQUENCY (MHz) 1000 6350 G19 OP AMP2 FREQUENCY RESPONSE MAGNITUDE (dB) OP AMP2 FREQUENCY RESPONSE MAGNITUDE (dB) Closed Loop Small Signal Frequency Response, Op Amp 2 5 0 –5 –10 PHASE –15 –20 –25 0.1 MAGNITUDE VS = 5V 500 400 OP AMP2 PHASE (DEG) 300 200 100 0 –100 1000 6350 G20 Closed Loop Magnitude and Group Delay Response, Op Amp 2 5 MAGNITUDE 0 GROUP DELAY –5 6 7 8 60 50 OUTPUT BALANCE (dB) 40 30 20 10 –15 0.1 4 100 6350 G40 Output Balance vs Frequency VS = 5V OP AMP2 GROUP DELAY (ns) –10 5 1 10 100 FREQUENCY (MHz) 1 10 FREQUENCY (MHz) 0 0.1 10 1 FREQUENCY (MHz) 100 6350 G41 Small Signal Step Response OUT2, CL = 56pF EACH OUTPUT TO GND 5 Large Signal Step Response 80 OUT2 4 DIFFERENTIAL OUTPUT SLEW RATE (V/μS) Differential Slew Rate vs Temperature VS = 5V OUT1 TIED TO –IN1 70 50Ω SOURCE IMPEDANCE RL = 1k 60 50 40 OUT2 RISING (OUT1 FALLING) 30 20 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 6350 G34 3586 G35 OUT1, NO LOAD 20mV/DIV OUTPUT VOLTAGE (V) 3 V+ = 5V, V – = 0V V+IN2 = 2.5V NO LOAD OUT1 RISING (OUT2 FALLING) 2 OUT2, NO LOAD 1 OUT1, CL = 56pF EACH OUTPUT TO GND 0 VS = 5V 200ns/DIV 6350 G33 OUT1 200ns/DIV 6350f 9 LT6350 TYPICAL PERFORMANCE CHARACTERISTICS + – + Harmonic Distortion vs Frequency –50 –60 DISTORTION (dBc) –70 –80 –90 –100 –110 –120 1k 100k 10k FREQUENCY (Hz) 1M 6350 G47 TA = 25°C, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RF = SHORT, RG = OPEN, RL = OPEN. See Figure 1. Harmonic Distortion vs Output Amplitude –60 fIN = 100kHz RL = 2k V + = 5V, V – = 0V, VOUTCM = 2.5V –80 –40.0 –50.0 V + = 5V, V – = 0V, VOUTCM = 2.5V DISTORTION (dBc) –60.0 –70.0 HD3 HD2 –90.0 V + = 5V, V – = –2V, VOUTCM = 2V –110 4 5 6 VOUTDIFF (VP-P) 6350 G45 Harmonic Distortion vs Output Amplitude fIN = 1MHz RL = 2k V+ = 5V, V – = 0V, VOUTCM = 2.5V RL = 2k –70 DISTORTION (dBc) VOUTDIFF = 8VP-P –90 HD3 –100 HD2 HD3 VOUTDIFF = 4VP-P HD2 –80.0 V + = 5V, V – = –2V, VOUTCM = 2V 2 3 5 6 4 VOUTDIFF (VP-P) 7 8 6350 G46 –100.0 7 8 PIN FUNCTIONS –IN1 (Pin 1): Inverting Input. Normally used to take feedback from OUT1. +IN2 (Pin 2): High Impedance Input. Normally used as a reference input. V+ (Pin 3): Positive Power Supply. OUT1 (Pin 4): Noninverting Output. In phase with +IN1. OUT2 (Pin 5): Inverting Output. V– (Pin 6): Negative Power Supply. Can be ground. SHDN (Pin 7): Shutdown. If tied high or left floating, the part is enabled. If tied low, the part is disabled and draws less than 70μA of supply current. +IN1 (Pin 8): High Impedance Input. Normally used as the single-ended input. Exposed Pad (Pin 9, DD8 Package Only): Tie to V – 6350f 10 LT6350 BLOCK DIAGRAM +IN1 8 SHDN 7 V– 6 OUT2 5 + OP AMP 1 BIAS – 1k 1k _ OP AMP 2 + 1 – IN1 2 +IN2 3 V+ 4 OUT1 6350 BD DC TEST CIRCUIT VSHDN V+IN1 + – V+ 0.1μF VOUT2 – RL + – V1 +IN1 SHDN V+ OUT2 + – – IN1 RF +IN2 V– RG R1 499Ω V2 0.1μF 0.1μF + – Figure 1. DC Test Circuit. + – V– OUT1 LT6350 VOUTDIFF + VOUT1 6350 TC 6350f 11 LT6350 OPERATION The LT6350 is a low noise single-ended to differential converter /ADC driver. It converts a high or low impedance, single-ended input signal to a low impedance, balanced differential output suitable for driving high performance differential sucessive approximation register (SAR) ADCs. The closed loop –3dB bandwidth for the typical gain-of-two configuration is 33MHz. The LT6350 uses a two op amp topology as shown in the Block Diagram: at the input is one fully uncommitted op amp with both inputs and output brought out to pins. This is followed by an op amp internally hardwired and optimally compensated as a unity-gain inverter with its input connected to the output of the first op amp. The noninverting input of the inverting op amp is brought out to a pin and is used to set the output common mode voltage level. The outputs of the two op amps are therefore 180° out-of-phase and provide a low impedance differential drive for differential-input analog to digital converters. The outputs of the LT6350 can swing rail-to-rail and can source or sink a transient 45mA of current. The outputs are designed to drive 40pF to ground or 20pF differentially. Load capacitances larger than 40pF should be decoupled from each output with at least 25Ω of series resistance. The LT6350 features very low noise op amps to support signal-to-noise ratios >110dB. BASIC CONNECTIONS A typical use of the LT6350 is to convert a high impedance, single-ended input signal into a low impedance differential output. The configuration for such an application is shown in Figure 2. Here, the input op amp is wired as a noninverting buffer with a high input impedance at +IN1. At the outputs, VOUT1 follows the input, and VOUT2 provides an inverted copy of VOUT1 for an overall differential gain of two. The input op amp has a rail-to-rail input stage, and both outputs are rail-to-rail, typically swinging to within 55mV of the rails at each output in this configuration allowing 8VP-P differential outputs from a single 5V rail. This provides a simple interface to differential input ADCs that accept a mid-rail input common mode voltage. 4.5V VIN 0.5V 5V 0.1μF +IN1 SHDN V+ VOUT2 4.5V OUT2 0.5V + – VIN 0.5V-4.5V + – – IN1 +IN2 2.5V 0.1μF 0.5V 6350 F02 Figure 2. Basic Connections DESIGN EQUATIONS AND ALTERNATIVE CONNECTIONS Because the input op amp presents its output and both its inputs to LT6350 pins, alternative configurations are possible. Consider the general configuration shown in Figure 3. Ordinary op amp analysis gives the equations for VOUT1 and VOUT2 given the input voltages V1, V2, VIN and VA: VOUT1 = VIN • (1+RF /RG) – V1 • (RF/RG) VOUT1 = VA • (1+RF /RG) + V1 VOUT2 = – VOUT1 + 2 • V2 If we define the differential and common mode output voltages as: VOUTDIFF ≡ VOUT1 – VOUT2 and VOUTCM ≡ (VOUT1 + VOUT2)/2, then combining the expressions for VOUT1 and VOUT2 with the definitions gives the resulting differential and common mode output voltages: VOUTDIFF = 2 • (VIN • (1+RF/RG)–V1 • (RF/RG)–V2) (1) VOUTDIFF = 2 • (VA • (1+RF /RG) + V1 – V2) VOUTCM = V2 (2) (3) 6350f 12 + – LT6350 V– OUT1 VOUT1 4.5V LT6350 OPERATION Notice that the output common mode voltage is determined simply by the voltage at +IN2. However, since the voltage applied at +IN2 does not affect the voltage at the VOUT1 output, a differential offset voltage will develop for VA = 0 when V1 does not equal V2. The value of the offset voltage will be 2 • (V1 – V2), as can be seen in Equation 2. For lowest differential offset, therefore, the input signal to pin +IN1, VIN , should be centered around the common mode voltage applied to pin +IN2. Often this voltage is provided by the ADC reference output. When the input is so centered and V1 = V2, Equation 2 reduces to: VOUTDIFF = 2 • VA • (1+RF /RG) The simple connection described in the Basic Connections section can be seen as a special case of the general circuit in Figure 3 where RF is a short circuit, RG is an open circuit, and the voltage at VIN is centered around the voltage V2. If differential gain greater than two is needed, the values of RF and RG can be adjusted in accordance with Equation (2). Additional information about feedback networks is given in the next section and in the Input Amplifier (Op Amp 1) Feedback Components section. Inverting Gain Connections/Interfacing to High Voltage Signals Although the previous examples have assumed the input signal is applied at +IN1, it is also possible to use the input op amp in an inverting configuration by fixing the voltage VIN and applying the input signal at V1 of Figure 3. Using the input op amp in the inverting configuration fixes its input common mode voltage at the voltage VIN , which allows the input signal at V1 to traverse a swing beyond the LT6350 supply rails. To avoid unwanted differential offsets in this configuration VIN should be chosen such that: VIN = V2/(1+(RF /RG)) Then Equation (1) reduces to: VOUTDIFF = –2 • V1 • (RF/RG)) Choosing RF = RG with the input at V1 leads to the gain of –2 configuration. A practical application for the inverting gain configuration is interfacing a high voltage op amp to a 5V differential SAR ADC. As seen in Figure 4, an industrial application might have SIGNAL –15V HIGH VOLTAGE OP AMP OUTHVMAX OUTHVNOM OUTHVMIN sensed signals coming through an op amp running from ±15V rails. The LT6350 can easily interface the high voltage op amp to a 5V ADC by using the inverting gain configuration. For a clean interface, three conditions must be met: 1. VOUTDIFF = 0 when OUTHV is centered at OUTHVNOM. 2. VOUT1 = VOUTCM = V2 when OUTHV is centered at OUTHVNOM. 3. Full-scale signals at OUTHV are translated at the output of the LT6350 into the appropriate full-scale range for the ADC. Applying the above constraints to the design Equations (1) to (3) gives values for the ratio of RF to RG and for the value of VIN : RF /RG = (OUTMAX − OUTMIN )/(OUTHVMAX − OUTHVMIN ) VIN = V 2 / (1+ (RF / RG )) + (OUTHVNOM )/(1+ (RG /RF )) +IN1 8 –IN1 1 OP AMP 1 4 OUT1 RINT RF RS RG – +IN2 2 RINT + – OP AMP 2 + – + VA VIN – + V2 5 OUT2 6350 F03 + – V1 + – Figure 3. General Configuration OUTMAX V2 +IN1 OP AMP 1 8 + +15V OUTMIN 4 OUT1 RINT RINT + – VIN – OP AMP 2 RF 1 –IN1 +IN2 2 OUTHV RG – + OUTMAX V2 V2 5 OUT2 + – OUTMIN 6350 F04 Figure 4. Interfacing to High Voltage Signals 6350f 13 LT6350 APPLICATIONS INFORMATION INPUT AMPLIFIER (OP AMP 1) CHARACTERISTICS Figure 5 shows a simplified schematic of the LT6350’s input amplifier. The input stage has NPN and PNP differential pairs operating in parallel. This topology allows the inputs to swing all the way from the negative supply rail to the positive supply rail. Both differential pairs are operational when the common mode voltage is at least 1.3V from either rail. As the common mode voltage swings higher than V + – 1.3V, current source I1 saturates, and current in PNP differential pair Q1/Q4 drops to zero. Feedback is maintained through the NPN differential pair Q2/Q3, but the input stage transconductance, gm , is reduced by a factor of 2. A similar effect occurs with I2 when the common mode voltage swings within 1.3V of the negative rail. A precision, two-point algorithm is used to maintain near constant offset voltage over the entire input range (see Offset Considerations). Negative input bias current flows into the +IN1 and –IN1 inputs when the input common mode is centered between the rails. The magnitude of this current increases when the input common mode voltage is within 1.3V of the negative rail and only Q1/Q4 are active. The polarity of the current reverses when the input common mode voltage is within 1.3V of the positive rail and only Q2/Q3 are active. Typical total change in input bias current over the entire input common mode range is approximately 4μA. These changes in input bias current will generate corresponding changes in voltage across the source and gain-setting resistors. Because the LT6350 input offset current is less than the input bias current, matching the effective source and feedback resistances at the input pins will reduce total offset errors generated by changes in input bias current and will keep distortion to a minimum. INPUT AMPLIFIER (OP AMP 1) FEEDBACK COMPONENTS When feedback resistors are used to set gain in op amp 1, care should be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input, –IN1, does not degrade stability. For instance, to set the LT6350 in a differential gain of +4, RF and RG of Figure 3 could be set to 1kΩ. If the total capacitance at –IN1 (LT6350 plus PC board) were 3pF a new pole would , be formed in the loop response at 106MHz, which could lead to ringing in the step response. A capacitor connected across the feedback resistor and having the same value + R1 I1 R2 V+ VBIAS Q11 – Q5 Q6 V– DESD1 +IN1 V+ DESD2 Q1 Q2 D1 D2 Q9 DESD4 Q8 Q7 V– R3 I2 R4 R5 D3 V– 6350 F05 Q4 Q3 V+ CM DIFFERENTIAL DRIVE GENERATOR V+ DESD5 OUT1 DESD6 –IN1 DESD3 V– V+ Q10 Figure 5. Input Amplifier (Op Amp 1) Simplified Schematic 6350f 14 LT6350 APPLICATIONS INFORMATION as the total –IN1 parasitic capacitance will eliminate any ringing or oscillation. Special care should be taken during layout, including using the shortest possible trace lengths and stripping the ground plane under the –IN1 pin, to minimize the parasitic capacitance introduced at that pin. Input bias current induced DC voltage offsets in the input op amp can be minimized by matching the parallel impedance of RF and RG to the impedance of the source that drives +IN1. For example, in the typical gain-of-two application, when the input op amp is configured as a unity gain buffer, choosing RF = RS will minimize the differential offset at the output. Since nonzero values of RF will contribute to the total output noise, RF may be bypassed with a capacitor to reduce the noise bandwidth. INVERTING AMPLIFIER (OP AMP 2) CHARACTERISTICS The operational amplifier at pins OUT1, +IN2 and OUT2 is internally configured as a unity gain inverter and provides on pin OUT2 an inverted copy of the voltage at pin OUT1. The voltage applied to pin +IN2 sets the output common mode voltage in accordance with Equation (3). The range of useful output common mode voltages is limited by the full-scale input range of A/D converters; values of output common mode near mid-rail are most useful. The op amp used for the inverting buffer therefore differs from the input op amp primarily in that its input common mode range is not rail-to-rail: the inverting op amp has an input stage that functions over the input range from V – + 1.5V to V + – 0.1V. The inverting op amp uses tightly matched, 1k on-chip resistors to set the gain of –1. Note that during output swings, current flows through these resistors, increasing the total power dissipation of the LT6350. The worst case increase over quiescent power dissipation can be found by assuming that the full power supply voltage appears between OUT1 and OUT2. In this case the extra power dissipated in the internal feedback network will be VS2/2kΩ. Since the inverting op amp is permanently configured with a noise gain of two, the internal frequency compensation has been adjusted such that the GBW product of the inverting op amp is higher than that of the input op amp. This allows the closed loop bandwidths of the two op amps to match more closely when the LT6350 is used in the typical differential gain of two configuration and increases the closed loop differential bandwidth in that application. The input referred voltage offset of the inverting op amp, which is equivalent to output common mode voltage offset, and which could contribute to differential voltage offset in accordance with Equation (2), is trimmed during manufacture to within ±125μV. To minimize the offset contribution of the input bias current into pin +IN2, an external 499Ω resistor should be installed at pin +IN2 for all applications. For more information, see the Setting The Output Common Mode and Offset Considerations sections. INPUT PROTECTION There are back-to-back diodes across the + and – inputs of both LT6350 op amps. The inputs of the LT6350 do not have internal resistors in series with the input transistors, a technique often used to protect the input transistors from excessive current flow during a differential overdrive condition. Adding series input resistors would significantly degrade the low noise performance. Therefore, if the voltage across the op amp input stages is allowed to exceed ±0.7V, steady state current conducted though the protection diodes should be externally limited to ±20mA. The input diodes are rugged enough to handle transient currents due to amplifier slew rate overdrive or momentary clipping without protection resistors. 6350f 15 LT6350 APPLICATIONS INFORMATION Driving the input signal sufficiently beyond the power supply rails will cause the input transistors to saturate. When saturation occurs, the amplifier loses a stage of phase inversion and the output tries to invert. Diodes D1 and D2 (Figure 5) forward bias and hold the output within a diode drop of the input signal. With very heavy input overdrive the output of op amp 1 could invert. To avoid this inversion, limit the input overdrive to 0.5V beyond the power supply rails. OUTPUT VOLTAGE RANGE The outputs of the LT6350 typically swing to within 55mV of the upper and lower supply rails when driving a purely capacitive load such as at the switched-capacitor input stage of a SAR ADC. The LT6350 can therefore share a single 5V supply with the SAR ADC and drive a full 8VP-P differential around an input common mode voltage between 2.055V and 2.945V. A modest negative supply can be added to allow the LT6350 to swing all the way to 0V in systems where the ADC requires a true 0V-referenced signal or when the input common mode range of the ADC is restricted to be lower than 2.055V. Some SAR ADCs use 2V as the input common mode voltage with a full-scale input signal range at each input of 0V to 4V. The outputs of the LT6350 can swing 7.78VP-P differentially around a 2V common mode voltage, which is a loss of only 0.24dB of the full-scale range of such ADCs. INTERFACING THE LT6350 TO A/D CONVERTERS When driving an ADC, an additional single-pole passive RC filter added between the outputs of the LT6350 and the inputs of the ADC can sometimes improve system performance. This is because the sampling process of ADCs creates a charge transient at the ADC inputs that is caused by the switching in of the ADC sampling capacitor. This momentarily shorts the output of the amplifier as charge is transferred between amplifier and sampling capacitor. For an accurate representation of the input signal, the amplifier must recover and settle from this load transient before the acquisition period has ended. An RC network at the outputs of the driver helps decouple the sampling transient of the ADC from the amplifier reducing the demands on the amplifier’s output stage (see Figure 6). The resistors at the inputs to the ADC minimize the sampling transients that charge the RC filter capacitors. VIN + – +IN1 SHDN +5V 0.1μF RFILT V+ CCM 5V RS AIN+ ADC AIN– RS RFILT 2V 0.1μF CCM 6350 F06 OUT2 + – – IN1 +IN2 Figure 6. Driving an ADC 16 + – V– OUT1 LT6350 CDIFF 6350f LT6350 APPLICATIONS INFORMATION The capacitance serves to provide the bulk of the charge during the sampling process, while the two resistors at the outputs of the LT6350 are used to dampen and attenuate any charge injected by the ADC. The RC filter can also be used to the additional benefit of band limiting broadband output noise. See the Noise Considerations section for more information. The selection of the RC time constant depends on the ADC; but generally, longer time constants will improve SNR at the expense of longer settling time. Excessive settling time can introduce gain errors and can cause distortion if the filter components are not perfectly linear. Note also that too small of a resistor will not properly dampen the load transient of the sampling process, prolonging the time required for settling. 16-bit applications typically require a minimum settling time of eleven RC time constants of a first order filter. Note that the filter’s series resistance also serves to decouple the LT6350 outputs from load capacitance. The outputs of the LT6350 are designed to drive a maximum of 40pF to ground or 20pF differentially; higher values of filter capacitor should always be decoupled with filter resistors of at least 25Ω. High quality resistors and capacitors should be used in the RC filter since these components can contribute to distortion. For lowest distortion, choose capacitors with a high quality dielectric, such as a C0G multilayer ceramic capacitor. Metal film surface mount resistors are more linear than carbon types. SETTING THE OUTPUT COMMON MODE VOLTAGE The output common mode voltage is set by the voltage applied to pin +IN2 in accordance with Equation (3). The usable output common mode range is determined by the input common mode range of the inverting op amp and is from V – + 1.5V to V +. In single supply applications, the optimal common mode input range to the ADC is often determined by the ADC’s reference. If the ADC has an output pin for setting the input common mode voltage, it can be directly tied to the +IN2 pin, as long as it is capable of providing the input current into +IN2 as listed in the Electrical Characteristics Table. Alternatively, +IN2 may be driven by an external precision reference such as the LT1790. For lowest offset, the +IN2 pin should see 499Ω of driving resistance in all applications (see Offset Considerations). If the driving resistance is nominally less than 499Ω, additional resistance can be added to make up the difference. The resistor noise bandwidth can be reduced by bypassing the +IN2 pin to the ground plane with a chip ceramic capacitor of at least 0.1μF (see the Typical Application on the front page). The bypass capacitance also helps prevent AC signals on this pin from being inadvertently converted to differential signals. SHDN If the SHDN pin (Pin 7), is pulled low within 300mV of the negative supply rail, the LT6350 will power down. The pin is connected through a diode to an internal current source of 20μA. When pulled below the shutdown threshold, the 20μA current will flow from the pin. If the pin is left open or pulled high (above V – + 2V), the part will enter normal active operation, and the current into the pin will be very small due to the reverse-biased diode. 6350f 17 LT6350 APPLICATIONS INFORMATION In shutdown, all biasing current sources are shut off, and the output pins, OUT1 and OUT2, each appear as open collectors with non-linear capacitors in parallel and steering diodes to either supply. Because of the non-linear capacitance, the outputs still have the ability to sink and source small amounts of transient current if driven with significant voltage transients. The input protection diodes between +IN1 and +IN2 can still conduct if voltage transients at the input exceed 700mV. All other inputs also have ESD protection diodes that can conduct when the applied voltage exceeds 700mV. Using the SHDN feature to wire-OR outputs together is not recommended. The turn-on and turn off times between the shutdown and active states are typically 400ns. ESD The LT6350 has ESD protection diodes on all inputs and outputs. The diodes are reverse biased during normal operation. If input pins are driven beyond either supply, large currents will flow through these diodes. If the current is transient and limited to 100mA or less, no damage to the device will occur. OFFSET CONSIDERATIONS For excellent offset and distortion performance, both the common mode and differential mode output voltage offsets are trimmed during manufacturing. Figure 7 shows the contributors to DC offset voltage in the LT6350. RS IOS1 OP AMP 1 +IN1 VOS1 IB1 + 2 IB1 – IOS1 2 VOSOUT1 RINT RINT + – The resulting DC offset voltages at pin OUT1 and OUT2 can be calculated: VOSOUT1 = VOS1•(1+RF/RG) + IB1•(RF-RS•(1+RF/RG)) – (IOS1/2)•(RF+RS•(1+RF/RG)) VOSOUT2 = –VOSOUT1 + 2•VOS2 + IB2•(RINT –2•R+IN2) – (IOS2/2)•(RINT + 2•R+IN2) Using the above equations and Equations (2) and (3), the output common mode and output differential mode offsets can be found. The common mode offset is found to be: VOSCM = VOS2 + IB2•((RINT/2) – R+IN2) – (IOS2/2) •((RINT/2) + R+IN2) + – RG –IN1 RF IOS2 OP AMP 2 2 – IOS2 IB2 + + VOSOUT2 2 IB2 – + – VOS2 +IN2 R+IN2 6350 F07 Figure 7. Offset Model 6350f 18 LT6350 APPLICATIONS INFORMATION Because the input bias current into op amp 2 is much larger than the offset current, choosing R+IN2 to be RINT/2 greatly reduces the offset contribution of op amp 2’s input currents on all units. With R+IN2 = RINT/2, VOSCM reduces to: VOSCM = VOS2 – (IOS2/2) • RINT VOSCM is trimmed to within ±125μV with a 499Ω resistor installed at +IN2. The value of VOS1 is trimmed to bring VOSDIFF to ± 125μV. Because linear modulation of VOS1 with input common mode could degrade the common mode rejection ratio specification of op amp 1, and nonlinear modulation of VOS1 could cause nonlinear gain error (distortion), VOS1 is trimmed to a low constant value over as wide an input common mode range as possible. A precision, two-point trim algorithm is used that results in VOS1 within ±125μV over the input range V – + 1.3V ≤ V+IN1 ≤ V + and VOS1 within ±300μV over the input range V – ≤ V+IN1 ≤ V +. A negative supply below –1.3V can be used to extend the input range for which VOS1 is within ±125μV all the way down to ground. As a result of the trim procedure, the lowest offsets, both common mode and differential mode, will occur with a 499Ω resistor at +IN2. This resistor can be bypassed with a capacitor to eliminate its noise contribution. The gainsetting resistor network (RG and RF) impedance should be matched to that of the source to minimize op amp 1’s input bias current contributions to the offsets. NOISE CONSIDERATIONS A model showing the sources of output noise in the LT6350 is shown in Figure 8. The total output noise resulting from all contributors is governed by the equation: eno = √(4 • [e2n1 + (in1RS)2 + e2nRS](1 + (RF / RG))2 + 4 • (in1RF)2 + 4e2nRF (1 + (RF / RG)) + 4e2n2 + 4e2nR+IN2 + 2e2nRINT + (in2RINT)2 + 4 • (in2R+IN2)2 ) The LT6350 uses very low noise op amps, resulting in a total differential output spot noise at 10kHz of 8.2nV/√Hz when the LT6350 is in the non-inverting gain-of-two configuration shown in Figure 2. This is equivalent to the voltage noise of a 1015Ω resistor at the +IN1 input. For source resistors larger than about 1k, voltage noise due to the source resistance will start to dominate output noise. Source resistors larger than about 13k will interact with the input current noise and result in output noise that is resistor noise and amplifier current noise dominant. in1 +IN1 en1 OP AMP 1 eno1 RINT enRINT enRINT RINT + eno – eno2 6350 F08 –IN1 RS enRS enRF + – in1 RF in2 OP AMP 2 +IN2 en2 – + in2 enRG RG enR+IN2 R+IN2 Figure 8. Noise Model Note that the parallel combination of gain-setting resistors RF and RG behaves like the source resistance, RS , from the point of view of noise calculations, and the value should be kept below about 1k to avoid increasing the output noise. Lower-value gain and feedback resistors, 6350f 19 LT6350 APPLICATIONS INFORMATION RG and RF, will always result in lower output noise at the expense of increased distortion due to increased loading of op amp 1. Note that op amp 1 is loaded internally by the 1k input resistor to op amp 2, and therefore external loading should not be much heavier than 1k to avoid degrading distortion performance. When using RF equal to RS (for low offsets) in the gainof-two configuration, wideband noise can be substantially reduced by bypassing across RF. For lowest output noise always bypass at the +IN2 pin with a capacitor of at least 0.1uF as seen in the Typical Application schematic on the front page. Alternatively, for systems that can tolerate output voltage offsets, omitting R+IN2 and RF will minimize output noise at the expense of larger output offset voltage. Using a single pole passive RC filter network at the output of the LT6350, as shown in Figure 6, reduces the output noise bandwidth and thereby increases the signal to noise ratio of the system. For example, in a typical system with output signals of 8VP-P, and a signal bandwidth of 100kHz, an RC output filter with RFILT = 100Ω and CDIFF = 6.8nF, slightly increases the output spot noise from 8.2nV√Hz to 8.4nV√Hz, but will reduce the total integrated noise from 47μV (33MHz noise bandwidth) to 3.6μV (184kHz noise bandwidth) and improve the SNR from 96dB to 118dB. Keep in mind that long RC time constants in the output filter can increase the settling time at the inputs of the ADC; incomplete settling can cause gain errors or increase apparent crosstalk in multiplexed systems. OUTPUT PHASE BALANCE The topology of the LT6350 is that of a noninverting stage followed by an inverting stage. This topology presents a high impedance single-ended input and provides low impedance differential outputs. The output of the inverting buffer, OUT2, is slightly delayed with respect to the output of the noninverting buffer, OUT1. In the LT6350, the delay from OUT1 to OUT2 over an input bandwidth from DC to the differential f–3dB frequency is a nearly constant 6.8ns, as shown in the group delay plot in the Typical Performance Characteristics section of this data sheet. The delay is equivalent to a small phase offset from the nominal 180° phase of the differential outputs. The size of the phase offset grows with frequency. The phase imbalance causes a small frequency-dependent common mode component to appear at the outputs. A practical measure of this effect can be found in the balance specification, which is defined to be the change in output common mode level caused by the presence of an output differential signal: Balance ≡ ((VOUTDIFF/VIN)/(VOUTCM /VIN)) The balance of the LT6350 at any frequency, f, can be approximated from the delay, td, between outputs: Balance (dB) ≅ 20 • log((4)/(2 • π • f • td)) The approximation is very good from low frequencies up to frequencies where the balance approaches 20dB, about 10MHz for the LT6350. At DC, the balance is limited by the matching of the internal resistors that set the gain in the inverting buffer. 1% matching of the resistors limits the balance to 52dB at DC. At frequencies near the f–3dB point of the differential transfer function, additional phase lag and gain rolloff also contribute to balance. See the balance plot in the Typical Performance Characteristics for a detailed picture of Balance vs Input Frequency. 6350f 20 LT6350 APPLICATIONS INFORMATION BOARD LAYOUT AND BYPASS CAPACITORS/DC1538A DEMOBOARD For single-supply applications it is recommended that a high quality X5R or X7R, 0.1μF bypass capacitor be placed directly between the V + and the V – pin; the V – pin (including the Exposed Pad on the DD8 package) should be tied directly to a low impedance ground plane with minimal routing. For split power supplies, it is recommended that additional high quality X5R or X7R, 0.1μF capacitors be used to bypass pin V + to ground and V – to ground, again with minimal routing. Small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self-resonant frequency than do leaded capacitors, and perform best with the LT6350. The +IN2 pin should be bypassed to ground with a high quality ceramic capacitor of at least 0.1μF, both to reduce the noise bandwidth of the recommended DC offset balance resistor and to prevent changes in the common mode reference voltage from being converted into a differential output signal. Stray parasitic capacitance at the –IN1 pin should be kept to a minimum to prevent degraded stability resulting in excessive ringing or oscillations. Traces at –IN1 should be kept as short as possible, and any ground plane should be stripped from under the pin and pin traces. Because the outputs operate differentially, load impedances seen by both outputs (stray or intended) should be as balanced and symmetric as possible. This will help preserve the balanced operation that minimizes the generation of even-order harmonic distortion in the output stage and maximizes the rejection of common mode signals and noise. The DC1538A demoboard has been designed for the evaluation of the LT6350 following the above layout practices. Its schematic and component placement are shown in Figures 9 and 10. 6350f 21 LT6350 APPLICATIONS INFORMATION +IN2 E1 V+ R8 30.1k R1 10k JP5 3 +IN2 2 EXT GND C10 1μF 1 2 3 C3 OPT 8 +IN1 7 SHDN V– V– 6 V+ OUT2 GND E7 R6 OPT C6 OPT NPO OUT1FILT OUT1 4 R9 10Ω C11 OPT NPO OUT1 E9 R12 0Ω C9 OPT NPO R10 0Ω C7 OPT NPO E10 3 C8 0.1μF R14 OPT J4 BNC 5 +IN1 E3 JP2 +COUPLING 1 J1 +IN1 BNC R5 OPT C4 OPT R2 0Ω AC 2 R15 20k SHDN E2 JP3 +IN1CM 3 +IN2 DC 3 2 C2 1μF NC V+ 1 SHDN JP1 OUT2 E2 R3 10Ω C1 OPT R4 NPO 0Ω C5 OPT NPO ENABLE SHDN OUT2FILT E5 1 J2 BNC + – GND E6 LT6350CMS8 JP4 –COUPLING –IN1 E8 J3 OPT –IN1 BNC R13 OPT C16 OPT R11 0Ω AC 1 2 DC 3 C12 1μF R7 499Ω –IN1 1 +IN2 2 GND E11 JP6 SINGLE SUPPLY V– SPLIT SUPPLY 1 2 3 V– E12 V– C13 1μF V+ V+ E13 C14 0.1μF V+ C23 10μF C21 10μF C15 0.1μF C17 1μF C18 1μF 6350 F09 C19 0.1μF C20 10μF LT6350 BYPASS Figure 9. DC1538A Demoboard Schematic 22 + – V– V+ C22 10μF 6350f LT6350 APPLICATIONS INFORMATION Figure 10. DC1538A Demoboard Layout 6350f 23 LT6350 APPLICATIONS INFORMATION Figure 11. DC1539A Demoboard Layout DRIVING THE LTC239X-16 / DC1539A DEMOBOARD The DC1539A demoboard, shown in Figure 11, has been developed to demonstrate the interfacing of the LT6350 to the LTC239x-16 family of 16-bit SAR ADCs. Spurious-free dynamic range of 102.2dB is achievable on the DC1539A as seen in the FFT in Figure 12. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 100 MAGNITUDE (dB) f = 20kHz V + = 5V, V – = – 5V VOUTDIFF = 7.3VP-P V+IN2 = 2.05V SNR = 94.9dB SINAD = 93.8dB THD = 100.2dB SFDR = 102.2dB 200 300 FREQUENCY (kHz) 400 500 6350 F12 Figure 12. 8192-point FFT LT6350 Driving the LTC2393-16 on the DC1539A Demoboard 6350f 24 LT6350 APPLICATIONS INFORMATION 100kHz, 3RD-ORDER BUTTERWORTH FILTER The LT6350 can be configured as a single-ended to differential filter incorporating feedback from the inverting output. Figure 13 shows the schematic of the configuration with values giving a 3rd Order Butterworth characteristic having a 100kHz –3dB point with a differential gain of four. Figure 14 shows the filter output response to 10MHz. As an option, to match the source impedance and preserve the low DC errors of the LT6350, connect a 2.10k series resistor at +IN1. To reduce the resistor noise, the +IN1 pin can be bypassed with a 0.1μF capacitor. For similar topologies please consult the LT1567 data sheet and design guide. 5V 2.5V 8 7 +IN1 SHDN 3 V+ 0.1μF 5 OUT2 VOUT2 20 0 –20 GAIN (dB) –40 –60 –80 –100 1K 10K 100K 1M FREQUENCY (Hz) 10M 6350 F14 Figure 14. 100KHz, 3rd Order Butterworth Filter Response Low Noise, Low Power 1MΩ Single Supply Photodiode Differential Output Transimpedance Amplifier The Typical Application on the back page shows the LT6350 applied as a differential output transimpedance amplifier. The LT6350 forces the BF862 ultralow noise JFET source to 3V, with R2 ensuring that the JFET has an IDRAIN of 1mA. The JFET acts as a source follower, buffering the input of the LT6350 and making it suitable for the high impedance feedback element R1. The BF862 has a minimum IDSS of 10mA and a pinchoff voltage between –0.3V and –1.2V. The JFET gate and OUT1 therefore sit at a point slightly higher than one pinchoff voltage below 3V, about midsupply at 2.5V. When the photodiode is illuminated, the current must come from OUT1 through R1 as in a normal transimpedance amplifier. Amplifier output noise density is dominated at low frequency by the 130nV/√Hz of the feedback resistor, rising to 210nV/√Hz at 1MHz. Note that because the JFET has a high gm, approximately 1/30Ω, its attenuation looking into R2 is only about 1%. The closed-loop bandwidth using a 3pF photodiode was measured at approximately 1.35MHz. With the output taken differentially, the gain and the noise are both doubled. + – + – LT6350 – IN1 1 1000pF +IN2 2 V– 6 OUT1 4 VOUT1 499Ω 2.5V C5 1000pF 0.1μF 174Ω 2210Ω 0.01μF R3 523Ω + – VIN 4750Ω 6350 F13 Figure 13. 100KHz, 3rd Order Butterworth Filter 6350f 25 LT6350 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 0.38 ± 0.10 8 3.00 ±0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 1.65 ± 0.10 (2 SIDES) (DD) DFN 1203 0.200 REF 0.75 ±0.05 4 0.25 ± 0.05 2.38 ±0.10 (2 SIDES) 1 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 6350f 26 LT6350 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 8 7 65 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 0° – 6° TYP 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.254 (.010) GAUGE PLANE 1 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 1.10 (.043) MAX 23 4 0.86 (.034) REF 0.65 (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS8) 0307 REV F 6350f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LT6350 TYPICAL APPLICATION Low Noise, Low Power 1MΩ Single Supply Photodiode Transimpedance Amplifier 5V 20k 3V 0.1μF 4.99k 2.5V 24.9k +IN1 SHDN V+ OUT2 VOUT1 500mV/DIV VOUT2 500mV/DIV 5V 0.1μF VOUT2 + – + – V– OUT1 0.1μF R1 1M VOUT1 6350 TA03 LT6350 IPD OSRAM SFH213 PHILIPS/NXP BF862 LIGHT ASSERT – IN1 +IN2 6350 TA04 2.5V VOUTDIFF = ~ ±200mV + IPD • 2MΩ BW = 1.35MHz R2 3.01k 0.1pF RELATED PARTS PART NUMBER LTC239x-16 LT6202/LT6203 LT1806/LT1807 LTC6403 LT1468/LT1469 LTC6246/LTC6247/ LTC6248 DESCRIPTION 16-Bit SAR ADCs COMMENTS 250ksps to 3Msps Single/Dual 100MHz Rail-to-Rail Input/Output Ultralow Noise, 1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth Low Power Amplifiers Single/Dual 325MHz Low Noise/Low Distortion Rail-toRail Input/Output Amplifiers 200MHz Low Noise, Low Distortion, Fully Differential Input/Output Amplifier/Driver Single/Dual 90MHz, 22V/μs 16-Bit Accurate Op Amp Single/Dual/Quad 180MHz Rail-to-Rail Low Power Op Amps 2.5V Operation, 550μV Maximum VOS, 3.5μV/√Hz 10.8mA Supply Current, –95dBc Distortion at 3MHz, 2VP-P Output ±5V to ±15V operation, VOS ≤ 75μV 1mA/Amplifier, 4.2nV/√Hz 6350f 28 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0110 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010