LT6402-20

FEATURES ■ ■ ■ LT6402-20 300MHz Low Distortion, Low Noise Differential Amplifier/ ADC Driver (AV = 20dB) DESCRIPTIO The LT®6402-20 is a low distortion, low noise differential amplifier/ADC driver for use in applications from DC to 300MHz. The LT6402-20 has been designed for ease of use, with minimal support circuitry required. Exceptionally low input-referred noise and low distortion (with either single-ended or differential inputs) make the LT6402-20 an excellent solution for driving high speed 12-bit and 14-bit ADCs. In addition to the normal unfiltered outputs (+OUT and –OUT), the LT6402-20 has a built-in 75MHz differential low pass filter and an additional pair of filtered outputs (+OUTFILTERED, –OUTFILTERED) to reduce external filtering components when driving high speed ADCs. The output common mode voltage is easily set via the VOCM pin, eliminating an output transformer or ACcoupling capacitors in many applications. The LT6402-20 is designed to meet the demanding requirements of communications transceiver applications. It can be used as a differential ADC driver, a general-purpose differential gain block, or in other applications requiring differential drive. The LT6402-20 can be used in data acquisition systems required to function at frequencies down to DC. The LT6402-20 operates on a 5V supply and consumes 30mA. It comes in a compact 16-lead 3mm × 3mm QFN package and operates over a –40°C to 85°C temperature range. ■ ■ ■ ■ ■ ■ ■ 300 MHz –3dB Bandwidth Fixed Gain of 20dB Low Distortion: 51dBm OIP3, –81dBc HD3 (20MHz, 2VP-P) Low Noise: 12.4dB NF, en = 1.9nV/√Hz (20MHz) Differential Inputs and Outputs Additional Filtered Outputs Adjustable Output Common Mode Voltage DC- or AC-Coupled Operation Minimal Support Circuitry Required Small 0.75mm Profile 16-Lead 3mm × 3mm QFN Package APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Differential ADC Driver for: Imaging Communications Differential Driver/Receiver Single Ended to Differential Conversion Differential to Single Ended Conversion Level Shifting IF Sampling Receivers SAW Filter Interfacing/Buffering , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO 5V 0.1µF Distortion vs Frequency, Differential Input, No RLOAD –40 –50 DISTORTION (dBc) FILTERED OUTPUTS VOUT = 2VP-P 0.1µF –INB –INA 0.1µF 0.1µF IF IN +INB +INA VEE VCC VOCM +OUT LT6402-20 –OUT 10Ω 10Ω VCM AIN+ LTC®2249 AIN– –60 –70 –80 –90 HD3 –100 6402 TA01a 1 U U U HD2 10 FREQUENCY (MHz) 100 64022 G08 640220fa 1 LT6402-20 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW +INA +INB –INA –INB Total Supply Voltage (VCCA/VCCB/VCCC to VEEA/VEEB/VEEC) ...................................................5.5V Input Current (+INA, –INA, +INB, –INB, VOCM, ENABLE)................................................±10mA Output Current (Continuous) +OUT, –OUT ...................................................±100mA +OUTFILTERED, –OUTFILTERED......................±30mA Output Short Circuit Duration (Note 2) ............ Indefinite Operating Temperature Range (Note 3) ... –40°C to 85°C Specified Temperature Range (Note 4) .... –40°C to 85°C Storage Temperature Range................... –65°C to 125°C Junction Temperature ........................................... 125°C Lead Temperature Range (Soldering 10 sec) ........ 300°C 16 15 14 13 VCCC 1 VOCM 2 VCCA 3 VEEA 4 5 +OUT 6 +OUTFILTERED 7 –OUTFILTERED 8 –OUT 17 12 VEEC 11 ENABLE 10 VCCB 9 VEEB UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W EXPOSED PAD IS VEE (PIN 17) MUST BE SOLDERED TO THE PCB ORDER PART NUMBER LT6402CUD-20 LT6402IUD-20 UD PART MARKING* LCBC LCBC Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. DC ELECTRICAL CHARACTERISTICS SYMBOL GDIFF VSWINGMIN VSWINGMAX VSWINGDIFF IOUT VOS TCVOS Output Voltage Swing Output Current Drive Input Offset Voltage PARAMETER Gain CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. MIN ● TYP 20 0.25 MAX 20.9 0.35 0.5 UNITS dB V V V V VP-P VP-P mA Input/Output Characteristics (+INA, +INB, –INA, –INB, +OUT, –OUT, +OUTFILTERED, –OUTFILTERED) Differential (+OUT, –OUT), VIN = ±160mV Differential Single-Ended +OUT, –OUT, +OUTFILTERED, –OUTFILTERED, VIN = ±600mV Differential Single-Ended +OUT, –OUT, +OUTFILTERED, –OUTFILTERED, VIN = ±600mV Differential Differential (+OUT, –OUT), VIN = ±600mV Differential 18.9 ● ● ● ● ● 3.4 3.3 6.1 5.6 ±30 –6.5 –10 3.6 7 ±35 1 2.5 6.5 10 Input Offset Voltage Drift TMIN to TMAX ● µV/°C 640220fa 2 U mV mV W U U WW W LT6402-20 DC ELECTRICAL CHARACTERISTICS SYMBOL IVRMIN IVRMAX RINDIFF CINDIFF CMRR ROUTDIFF COUTDIFF GCM VOCMMIN VOCMMAX VOSCM IBIASCM RINCM CINCM ⎯E⎯N⎯A⎯B⎯L⎯E Pin VIL VIH IIL IIH Power Supply VS IS ISDISABLED PSRR Operating Range Supply Current Supply Current (Disabled) Power Supply Rejection Ratio ⎯EN⎯A⎯B⎯L⎯E = 0.8V ⎯ ⎯EN⎯A⎯B⎯L⎯E = 2V ⎯ 4V to 5.5V ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. PARAMETER Input Voltage Range, MIN Input Voltage Range, MAX Input Resistance Input Capacitance Common Mode Rejection Ratio Output Resistance Output Capacitance Common Mode Gain Output Common Mode Voltage Adjustment Range, MIN Output Common Mode Voltage Adjustment Range, MAX Output Common Mode Offset Voltage VOCM Input Bias Current VOCM Input Resistance VOCM Input Capacitance ⎯E⎯N⎯A⎯B⎯L⎯E Input Low Voltage ⎯EN⎯A⎯B⎯L⎯E Input High Voltage ⎯ ⎯EN⎯A⎯B⎯L⎯E Input Low Current ⎯ ⎯EN⎯A⎯B⎯L⎯E Input High Current ⎯ ⎯EN⎯A⎯B⎯L⎯E = 0.8V ⎯ ⎯EN⎯A⎯B⎯L⎯E = 2V ⎯ ● ● ● ● CONDITIONS Single-Ended Single-Ended ● ● ● MIN 3.9 77 45 TYP MAX 0.9 UNITS V V Ω pF dB Ω pF 100 1 70 0.3 0.8 122 Input Common Mode 0.9V to 3.9V ● Common Mode Voltage Control (VOCM Pin) Differential (+OUT, –OUT), VOCM = 1.2V to 3.6V Differential (+OUT, –OUT), VOCM = 1.4V to 3.4V ● ● 0.9 0.9 1 1.1 1.1 1.2 1.4 V/V V/V V V V V Single-Ended ● 3.6 3.4 –30 4 5 0.8 3 1 0.8 2 0.5 1 4 24 55 5 30 250 90 3 5.5 37 500 30 15 Measured from VOCM to Average of +OUT and –OUT ● ● mV µA MΩ pF V V µA µA V mA µA dB 640220fa 3 LT6402-20 AC ELECTRICAL CHARACTERISTICS SYMBOL –3dBBW 0.1dBBW 0.5dBBW SR ts1% tON tOFF –3dBBWCM SRCM 10MHz Signal Second/Third Harmonic Distortion Third-Order IMD OIP310M NF en10M 20MHz Signal Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) 2VP-P Differential (+OUT, –OUT) 2VP-P Differential Composite (+OUTFILTERED, –OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz 2VP-P Differential Composite (+OUT, –OUT), RL = 400Ω, f1 = 19.5MHz, f2 = 20.5MHz OIP320M NF en20M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100Ω (Note 5) Differential (+OUTFILTERED, –OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz (Note 5) Measured Using DC954A Demo Board –81 –81 –96 –91 51 12.4 1.9 18 dBc dBc dBc dBc dBm dB nV/√Hz dBm Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100Ω (Note 5) 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) 2VP-P Differential (+OUT, –OUT) 2VP-P Differential Composite (+OUTFILTERED, –OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz Differential (+OUTFILTERED, –OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz (Note 5) Measured Using DC954A Demo Board –85 –85 –93 49.5 12.3 1.85 19.5 dBc dBc dBc dBm dB nV/√Hz dBm PARAMETER –3dB Bandwidth Bandwidth for 0.1dB Flatness Bandwidth for 0.5dB Flatness Slew Rate 1% Settling Turn-On Time Turn-Off Time Common Mode Small-Signal –3dB Bandwidth Common Mode Slew Rate 0.1VP-P at VOCM, Measured Single-Ended at +OUT and –OUT 1.3V to 3.4V Step at VOCM Input/Output Characteristics 20mVP-P Differential (+OUT, –OUT) 20mVP-P Differential (+OUT, –OUT) 20mVP-P Differential (+OUT, –OUT) 3.2VP-P Differential (+OUT, –OUT) 1% Settling for a 1VP-P Differential Step (+OUT, –OUT) 200 300 30 80 400 8 100 1 200 250 MHz MHz MHz V/µs ns ns µs MHz V/µs TA = 25°C, VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. CONDITIONS MIN TYP MAX UNITS Common Mode Voltage Control (VOCM Pin) Noise/Harmonic Performance Input/Output Characteristics 640220fa 4 LT6402-20 AC ELECTRICAL CHARACTERISTICS SYMBOL 25MHz Signal Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) 2VP-P Differential (+OUT, –OUT) 2VP-P Differential Composite (+OUTFILTERED, –OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz 2VP-P Differential Composite (+OUT, –OUT), RL = 400Ω, f1 = 24.5MHz, f2 = 25.5MHz OIP325M NF en25M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100Ω (Note 5) Differential (+OUTFILTERED, –OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz (Note 5) Measured Using DC954A Demo Board –80 –80 –86 –84 46 12.5 1.9 16.6 dBc dBc dBc dBc dBm dB nV/√Hz dBm PARAMETER TA = 25°C, VCCA = VCCB = VCCC = 5V,VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. CONDITIONS MIN TYP MAX UNITS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Note 3: The LT6402 is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 4: The LT6402C is guaranteed to meet specified performance from 0°C to 70°C. It is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6402I is guaranteed to meet specified performance from –40°C to 85°C. Note 5: Since the LT6402-20 is a feedback amplifier with low output impedance, a resistive load is not required when driving an ADC. Therefore, typical output power is very small. In order to compare the LT6402-20 with typical gm amplifiers that require 50Ω output loading, the LT6402-20 output voltage swing driving an ADC is converted to OIP3 and P1dB as if it were driving a 50Ω load. TYPICAL PERFORMANCE CHARACTERISTICS Frequency Response RLOAD = 400Ω 30 25 20 GAIN (dB) 15 10 5 VIN = 20mVP-P UNFILTERED: RLOAD = 400Ω –5 FILTERED: RLOAD = 300Ω (EXTERNAL) + 100Ω (INTERNAL, FILTERED OUTPUTS) –10 10 100 1000 1 FREQUENCY (MHz) 64022 G01 Frequency Response vs CLOAD, RLOAD = 400Ω 35 30 VIN = 20mVP-P UNFILTERED OUTPUTS 30 25 20 GAIN (dB) 15 Frequency Response RLOAD = 100Ω UNFILTERED 25 GAIN (dB) FILTERED 20 15 10 5 0 1 0pF 1.6pF 5pF 10pF 10 100 FREQUENCY (MHz) 1000 34022 G02 UNFILTERED FILTERED 10 5 0 –5 –10 1 VIN = 20mVP-P UNFILTERED: RLOAD = 100Ω FILTERED: RLOAD = 100Ω (INTERNAL, FILTERED OUTPUTS) 10 100 FREQUENCY (MHz) 1000 64022 G03 0 640220fa 5 LT6402-20 TYPICAL PERFOR A CE CHARACTERISTICS Third Order Intermodulation Distortion vs Frequency Differential Input, No RLOAD –60 2 TONES, 2VP-P COMPOSITE –65 1MHz TONE SPACING THIRD ORDER IMD (dBc) THIRD ORDER IMD (dBc) –70 –75 –80 –85 –90 –95 FILTERED OUTPUTS UNFILTERED OUTPUTS –60 OUTPUT IP3 (dBm) –100 –105 –110 5 10 20 25 15 FREQUENCY (MHz) 30 35 Output Third Order Intercept vs Frequency, Differential Input, RLOAD = 400Ω 60 55 FILTERED OUTPUTS OUTPUT IP3 (dBm) DISTORTION (dBc) 50 45 40 35 30 UNFILTERED OUTPUTS 2 TONES, 2VP-P COMPOSITE 1MHz TONE SPACING –40 –50 –60 –70 –80 –90 –100 5 10 15 20 25 FREQUENCY (MHz) 30 35 DISTORTION (dBc) Distortion vs Output Amplitude 20MHz Differential Input, No RLOAD (Filtered) –70 FILTERED OUTPUTS 20MHz DIFFERENTIAL INPUT NO RLOAD DISTORTION (dBc) –70 –72 –74 DISTORTION (dBc) –80 HD2 –76 –78 –80 OUTPUT 1dB COMPRESSION (dBm) –75 –85 HD3 –90 –95 0 1 2345678 OUTPUT AMPLITUDE (dBm) 6 UW 64022 G04 Third Order Intermodulation Distortion vs Frequency Differential Input, RLOAD = 400Ω 2 TONES, 2VP-P COMPOSITE –65 1MHz TONE SPACING –70 –75 –80 –85 –90 –95 FILTERED OUTPUTS UNFILTERED OUTPUTS 50 45 40 35 30 5 10 20 25 15 FREQUENCY (MHz) 30 35 60 55 Output Third Order Intercept vs Frequency, Differential Input, No RLOAD 2 TONES, 2VP-P COMPOSITE 1MHz TONE SPACING FILTERED OUTPUTS UNFILTERED OUTPUTS –100 –105 –110 5 10 15 20 25 FREQUENCY (MHz) 30 35 64022 G05 64022 G06 Distortion vs Frequency, Differential Input, No RLOAD (Filtered) FILTERED OUTPUTS VOUT = 2VP-P –40 –50 –60 –70 –80 –90 –100 1 10 FREQUENCY (MHz) 100 64022 G08 Distortion vs Frequency, Differential Input, No RLOAD (Unfiltered) UNFILTERED OUTPUTS VOUT = 2VP-P HD3 HD3 HD2 HD2 1 10 FREQUENCY (MHz) 100 64022 G10 64022 G07 Distortion vs Output Amplitude 20MHz Differential Input, No RLOAD (Unfiltered) UNFILTERED OUTPUTS 20MHz DIFFERENTIAL INPUT NO RLOAD 25 20 15 10 5 0 –5 –10 0 1 2345678 OUTPUT AMPLITUDE (dBm) 9 10 Output 1dB Compression vs Frequency 400Ω LOAD 100Ω LOAD HD2 HD3 –82 –84 9 10 – 86 UNFILTERED OUTPUTS 1 10 100 FREQUENCY (Hz) 1000 64022 G14 64022 G12 64022 G13 640220fa LT6402-20 TYPICAL PERFOR A CE CHARACTERISTICS Noise Figure vs Frequency INPUT REFERRED NOISE VOLTAGE (nV/√Hz) 30 8 7 6 5 4 3 2 1 0 10 100 FREQUENCY (MHz) 1000 64022 G16 25 NOISE FIGURE (dB) ISOLATION (dB) 20 15 10 MEASURED USING DC954A DEMO BOARD 10 100 FREQUENCY (MHz) 1000 64022 G15 5 Differential Input Impedance vs Frequency INPUT IMPEDANCE (MAGNITUDE Ω, PHASE°) 400 350 OUTPUT IMPEDANCE (Ω) 300 250 200 150 100 50 0 –50 –100 1 10 100 FREQUENCY (MHz) 1000 64022 G18 INPUT REFLECTION COEFFICIENT (S11) IMPEDANCE MAGNITUDE IMPEDANCE PHASE 0 10 100 FREQUENCY (MHz) 1000 64022 G19 Output Reflection Coefficient vs Frequency 0 OUTPUT REFLECTION COEFFICIENT (S22) –5 –10 PSRR, CMRR (dB) –15 –20 –25 –30 –35 –40 1 10 100 FREQUENCY (MHz) 1000 64022 G21 MEASURED USING DC954A DEMO BOARD 100 90 80 70 60 50 40 30 20 10 0 1 PSRR OUTPUT VOLTAGE (V) UW Input Referred Noise Voltage vs Frequency –30 –40 –50 –60 –70 –80 –90 –100 –110 Isolation vs Frequency UNFILTERED OUTPUTS 1 10 100 FREQUENCY (MHz) 1000 64022 G17 Differential Output Impedance vs Frequency 1000 UNFILTERED OUTPUTS 0 –5 –10 –15 –20 –25 –30 –35 Input Reflection Coefficient vs Frequency MEASURED USING DC954A DEMO BOARD 100 10 1 1 10 100 FREQUENCY (MHz) 1000 34022 G20 PSRR, CMRR vs Frequency 120 110 UNFILTERED OUTPUTS Small-Signal Transient Response RLOAD = 100Ω PER OUTPUT 2.25 2.20 2.15 CMRR TIME (5ns/DIV) 64022 G23 10 100 FREQUENCY (MHz) 1000 64022 G22 640220fa 7 LT6402-20 TYPICAL PERFORMANCE CHARACTERISTICS Large-Signal Transient Response 3.4 3.2 3.0 OUTPUT VOLTAGE (V) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 TIME (10ns/DIV) 64022 G24 Overdrive Recovery Time 4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 –88 0.5 0 –OUT TIME (25ns/DIV) 64022 G25 Distortion vs Output Common Mode Voltage LT6402-20 Driving LTC2249 14-Bit ADC –80 FILTERED OUTPUTS, NO RLOAD VOUT = 20MHz 2VP-P HD3 RLOAD = 100Ω PER OUTPUT RLOAD = 100Ω PER OUTPUT +OUT DISTORTION (dBc) –82 –84 –86 HD2 –90 1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 OUTPUT COMMON MODE VOLTAGE (V) 64022 G26 Turn-On Time 4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0V TIME (125ns/DIV) 64022 G27 Turn-Off Time 4.0 3.5 OUTPUT VOLTAGE (V) 3.0 +OUT 2.5 2.0 –OUT 1.5 1.0 0.5 0 0V TIME (250ns/DIV) 64022 G28 10MHz 8192 Point FFT, LT6402-20 Driving LTC2249 14-Bit ADC 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 5V –100 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 8192 POINT FFT fIN = 10MHz, –1dBFS FILTERED OUTPUTS RLOAD = 1009 PER OUTPUT RLOAD = 1009 PER OUTPUT +OUT –OUT ENABLE 5V ENABLE 64022 G29 20MHz 8192 Point FFT, LT6402-20 Driving LTC2249 14-Bit ADC 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 8192 POINT FFT fIN = 20MHz, –1dBFS FILTERED OUTPUTS 25MHz 8192 Point FFT, LT6402-20 Driving LTC2249 14-Bit ADC 0 8192 POINT FFT –10 fIN = 25MHz, –1dBFS –20 FILTERED OUTPUTS –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 20MHz 2-Tone 32768 Point FFT, LT6402-20 Driving LTC2249 14-Bit ADC 32768 POINT FFT TONE 1 AT 19.5MHz, –7dBFS TONE 2 AT 20.5MHz, –7dBFS FILTERED OUTPUTS 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 FREQUENCY (MHz) 64022 G32 64022 G30 64022 G31 640220fa 8 LT6402-20 PI FU CTIO S VOCM (Pin 2): This pin sets the output common mode voltage. Without additional biasing, both inputs bias to this voltage as well. This input is high impedance. VCCA, VCCB, VCCC (Pins 3, 10, 1): Positive Power Supply (Normally Tied to 5V). All three pins must be tied to the same voltage. Bypass each pin with 1000pF and 0.1µF capacitors as close to the package as possible. Split supplies are possible as long as the voltage between VCC and VEE is 5V. VEEA, VEEB, VEEC (Pins 4, 9, 12): Negative Power Supply (Normally Tied to Ground). All three pins must be tied to the same voltage. Split supplies are possible as long as the voltage between VCC and VEE is 5V. If these pins are not tied to ground, bypass each pin with 1000pF and 0.1µF capacitors as close to the package as possible. +OUT, –OUT (Pins 5, 8): Outputs (Unfiltered). These pins are high bandwidth, low-impedance outputs. The DC output voltage at these pins is set to the voltage applied at VOCM. +OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered Outputs. These pins add a series 50Ω resistor from the unfiltered outputs and three 14pF capacitors. Each output has 14pF to VEE, plus an additional 14pF between each pin (See the Block Diagram). This filter has a –3dB bandwidth of 75MHz. ⎯E⎯N⎯A⎯B⎯L⎯E (Pin 11): This pin is a TTL logic input referenced to the VEEC pin. If low, the LT6402 is enabled and draws typically 30mA of supply current. If high, the LT6402 is disabled and draws typically 250µA. +INA, +INB (Pins 15, 16): Positive Inputs. These pins are normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. –INA, –INB (Pins 14, 13): Negative Inputs. These pins are normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split supplies are used, DO NOT tie the pad to ground. BLOCK DIAGRA –INA 14 –INB 13 +INA 16 +INB 15 W U U U 500Ω 100Ω VCCA 14pF VEEA – A 5 +OUT +OUTFILTERED VEEA 50Ω VCCC 6 VOCM 100Ω + 500Ω + C 14pF 2 – 500Ω 100Ω VCCB VEEC 50Ω –OUTFILTERED 7 –OUT B 8 14pF VEEB + – VEEB 500Ω 100Ω BIAS 3 VCCA 10 VCCB 1 VCCC 11 ENABLE 4 VEEA 9 VEEB 12 VEEC 6402 BD 640220fa 9 LT6402-20 APPLICATIO S I FOR ATIO Circuit Description The LT6402-20 is a low noise, low distortion differential amplifier/ADC driver with: • –3dB bandwidth DC to 300MHz • Fixed gain independent of RLOAD 10V/V (20dB) • Differential input impedance 100Ω • Low output impedance • Built-in, user adjustable output filtering • Requires minimal support circuitry Referring to the block diagram, the LT6402-20 uses a closed-loop topology which incorporates 3 internal amplifiers. Two of the amplifiers (A and B) are identical and drive the differential outputs. The third amplifier is used to set the output common mode voltage. Gain and input impedance are set by the 500Ω and 100Ω resistors in the internal feedback network. Output impedance is low, determined by the inherent output impedance of amplifiers A and B, and further reduced by internal feedback. The LT6402-20 also includes built-in single-pole output filtering. The user has the choice of using the unfiltered outputs, the filtered outputs (75MHz –3dB lowpass), or modifying the filtered outputs to alter frequency response by adding additional components. Many lowpass and bandpass filters are easily implemented with just one or two additional components. The LT6402-20 has been designed to minimize the need for external support components such as transformers or AC-coupling capacitors. As an ADC driver, the LT6402-20 requires no external components except for power-supply bypass capacitors. This allows DC-coupled operation for applications that have frequency ranges including DC. At 10 U the outputs, the common mode voltage is set via the VOCM pin, allowing the LT6402-20 to drive ADCs directly. No output AC-coupling capacitors or transformers are needed. At the inputs, signals can be differential or single-ended with virtually no difference in performance. Furthermore, DC levels at the inputs can be set independently of the output common mode voltage. These input characteristics often eliminate the need for an input transformer and/or AC-coupling capacitors. Input Impedance and Matching Networks Calculation of the input impedance of the LT6402-20 is not straightforward from examination of the block diagram because of the internal feedback network. In addition, the input impedance when driven differentially is different than when driven single-ended. Differential LT6402-20 100Ω Single-Ended 85.9Ω W U U For single-ended 50Ω applications, a 121Ω shunt matching resistor to ground will result in the proper input termination (Figure 1). For differential inputs there are several termination options. If the input source is 50Ω differential, then the input matching can be accomplished by either a 100Ω shunt resistor across the inputs (Figure 3), or equivalent 49.9Ω shunt resistors on each of the inputs to ground (Figure 2). If additional AC gain is desired, an impedance ratio transformer can also be used to better match impedances. 13 14 0.1µF IF IN 121Ω ZIN = 50Ω SINGLE-ENDED 15 16 +INB +INA –INB –INA –OUT LT6402-20 +OUT 8 5 6402 F01 Figure 1. Input Termination for Single-Ended 50Ω Input Impedance 640220fa LT6402-20 APPLICATIO S I FOR ATIO Single-Ended to Differential Operation The LT6402-20’s performance with single-ended inputs is comparable to its performance with differential inputs. This excellent single-ended performance is largely due to the internal topology of the LT6402-20. Referring to the block diagram, if the +INA and +INB pins are driven with a single-ended signal (while –INA and –INB are tied to AC ground), then the +OUT and –OUT pins are driven differentially without any voltage swing needed from amplifier C. Single-ended to differential conversion using more conventional topologies suffers from performance limitations due to the common mode amplifier. Driving ADCs The LT6402-20 has been specifically designed to interface directly with high speed Analog to Digital Converters (ADCs). In general, these ADCs have differential inputs, with an input impedance of 1kΩ or higher. In addition, there is generally some form of lowpass or bandpass filtering just prior to the ADC to limit input noise at the ADC, thereby improving system signal to noise ratio. Both the unfiltered 13 IF IN– 49.9Ω ZIN = 50Ω DIFFERENTIAL 15 IF IN+ 49.9Ω 16 +INB +INA 14 Figure 2. Input Termination for Differential 50Ω Input Impedance 13 IF IN– ZIN = 50Ω DIFFERENTIAL IF IN+ 14 100Ω 15 16 –INB –INA –OUT LT6402-20 +INB +INA +OUT 8 5 6402 F03 Figure 3. Alternate Input Termination for Differential 50Ω Input Impedance U and filtered outputs of the LT6402-20 can easily drive the high impedance inputs of these differential ADCs. If the filtered outputs are used, then cutoff frequency and the type of filter can be tailored for the specific application if needed. Wideband Applications (Using the +OUT and –OUT Pins) In applications where the full bandwidth of the LT6402-20 is desired, the unfiltered output pins (+OUT and –OUT) should be used. They have a low output impedance; therefore, gain is unaffected by output load. Capacitance in excess of 5pF placed directly on the unfiltered outputs results in additional peaking and reduced performance. When driving an ADC directly, a small series resistance is recommended between the LT6402-20’s outputs and the ADC inputs (Figure 4). This resistance helps eliminate any resonances associated with bond wire inductances of either the ADC inputs or the LT6402-20’s outputs. A value between 10Ω and 25Ω gives excellent results. –INB –INA –OUT LT6402-20 +OUT 8 5 6402 F02 W U U –OUT LT6402-20 8 10Ω TO 25Ω ADC 10Ω TO 25Ω +OUT 5 6402 F04 Figure 4. Adding Small Series R at LT6402 Output 640220fa 11 LT6402-20 APPLICATIO S I FOR ATIO Filtered Applications (Using the +OUTFILTERED and –OUTFILTERED Pins) Filtering at the output of the LT6402-20 is often desired to provide either anti-aliasing or improved signal to noise ratio. To simplify this filtering, the LT6402-20 includes an additional pair of differential outputs (+OUTFILTERED and –OUTFILTERED) which incorporate an internal lowpass filter network with a –3dB bandwidth of 75MHz (Figure 5). These pins each have an output impedance of 50Ω. Internal capacitances are 14pF to VEE on each filtered output, plus an additional 14pF capacitor connected differentially between the two filtered outputs. This resistor/capacitor combination creates filtered outputs that look like a series 50Ω resistor with a 42pF capacitor shunting each filtered output to AC ground, giving a –3dB bandwidth of 75MHz. The filter cutoff frequency is easily modified with just a few external components. To increase the cutoff frequency, simply add 2 equal value resistors, one between +OUT and +OUTFILTERED and the other between –OUT and –OUTFILLT6402-20 VEE 50Ω 14pF 7 –OUTFILTERED 50Ω 14pF VEE 5 +OUT 6402 F05 8 –OUT 14pF 50Ω FILTERED OUTPUT (75MHz) 6 +OUTFILTERED 14pF VEE 14pF Figure 5. LT6402-20 Internal Filter Topology –3dB BW ≈75MHz LT6402-20 LT6402-20 VEE 50Ω 14pF 50Ω 7 –OUTFILTERED 50Ω 14pF VEE 14pF 6 +OUTFILTERED 50Ω 5 +OUT 6402 F06 8 –OUT 50Ω FILTERED OUTPUT (150MHz) 50Ω 14pF Figure 6. LT6402-20 Internal Filter Topology Modified for 2x Filter Bandwidth (2 External Resistors) 12 U TERED (Figure 6). These resistors are in parallel with the internal 50Ω resistor, lowering the overall resistance and increasing filter bandwidth. To double the filter bandwidth, for example, add two external 50Ω resistors to lower the series resistance to 25Ω. The 42pF of capacitance remains unchanged, so filter bandwidth doubles. To decrease filter bandwidth, add two external capacitors, one from +OUTFILTERED to ground, and the other from –OUTFILTERED to ground. A single differential capacitor connected between +OUTFILTERED and –OUTFILTERED can also be used, but since it is being driven differentially it will appear at each filtered output as a single-ended capacitance of twice the value. To halve the filter bandwidth, for example, two 42pF capacitors could be added (one from each filtered output to ground). Alternatively one 21pF capacitor could be added between the filtered outputs, again halving the filter bandwidth. Combinations of capacitors could be used as well; a three capacitor LT6402-20 VEE 50Ω 14pF 7 –OUTFILTERED 14pF FILTERED OUTPUT (37.5MHz) 8 –OUT 14pF 6 +OUTFILTERED 14pF 5 +OUT 6402 F07 W U U Figure 7. LT6402-20 Internal Filter Topology Modified for 1/2x Filter Bandwidth (3 External Capacitors) VEE 14pF 8 –OUT 7 –OUTFILTERED 14pF FILTERED OUTPUT 6 +OUTFILTERED VEE 5 +OUT 6402 F08 Figure 8. LT6402-20 Output Filter Modified for Bandpass Filtering (1 External Inductor, 1 External Capacitor) 640220fa LT6402-20 APPLICATIO S I FOR ATIO solution of 14pF from each filtered output to ground plus a 14pF capacitor between the filtered outputs would also halve the filter bandwidth (Figure 7). Bandpass filtering is also easily implemented with just a few external components. An additional 560pF and 62nH, each added differentially between +OUTFILTERED and –OUTFILTERED creates a bandpass filter with a 26MHz center frequency, –3dB points of 23MHz and 30MHz, and 1.6dB of insertion loss (Figure 8). Output Common Mode Adjustment The LT6402-20’s output common mode voltage is set by the VOCM pin. It is a high-impedance input, capable of setting the output common mode voltage anywhere in a range from 1.1V to 3.6V. Bandwidth of the VOCM pin is typically 200MHz, so for applications where the VOCM pin is tied to a DC bias voltage, a 0.1µF capacitor at this pin is recommended. For best distortion performance, the voltage at the VOCM pin should be between 1.8V and 2.6V. When interfacing with most ADCs, there is generally a VOCM output pin that is at about half of the supply voltage of the ADC. For 5V ADCs such as the LTC17XX family, this VOCM output pin should be connected directly (with the addition of a 0.1µF capacitor) to the input VOCM pin of the LT6402-20. For 3V ADCs such as the LTC22XX families, the LT6402-20 will function properly using the 1.65V from the ADC’s VCM reference pin, but improved Spurious Free Dynamic Range (SFDR) and distortion performance can be achieved by level-shifting the LTC22XX’s VCM reference voltage up to at least 1.8V. This can be accomplished as shown in Figure 9 by using a resistor divider between the LTC22XX’s VCM output pin and VCC and then bypassing the LT6402-20’s VOCM pin with a 0.1µF capacitor. For a common mode voltage above 1.9V, AC coupling capacitors are recommended between the LT6402-20 and LTC22XX ADCs because of the input voltage range constraints of the ADC. Large Output Voltage Swings The LT6402-20 has been designed to provide the 3.2VP-P output swing needed by the LTC1748 family of 14-bit low-noise ADCs. This additional output swing improves system SNR by up to 4dB. U Input Bias Voltage and Bias Current The input pins of the LT6402-20 are internally biased to the voltage applied to the VOCM pin. No external biasing resistors are needed, even for AC-coupled operation. The input bias current is determined by the voltage difference between the input common mode voltage and the VOCM pin (which sets the output common mode voltage). For example, if the inputs are tied to 2.5V with the VOCM pin at 2.2V, then a total input bias current of 1mA will flow into the LT6402-20’s +INA and +INB pins. Furthermore, an additional input bias current totaling 1mA will flow into the –INA and –INB inputs. Application (Demo) Boards The DC954A Demo Board has been created for stand-alone evaluation of the LT6402-20 with either single-ended or differential input and output signals. As shown, it accepts a single-ended input and produces a single-ended output so that the LT6402-20 can be evaluated using standard laboratory test equipment. For more information on this Demo Board, please refer to the layout and schematic diagrams found later in this data sheet. There are also additional demo boards available that combine the LT6402-20 with a variety of different Linear Technology ADCs. Please contact the factory for more information on these demo boards. 3V 11k 1.9V 0.1µF 13 14 0.1µF 15 IF IN 121Ω 16 –INB –INA 2 VOCM +OUTFILTERED LT6402-20 –OUTFILTERED +INB +INA 6402 F9 W U U 4.02k 31 1.5V 6 10Ω 10Ω 1 VCM AIN+ LTC22xx AIN– 7 2 Figure 9. Level Shifting 3V ADC VCM Voltage for Improved SFDR 640220fa 13 LT6402-20 TYPICAL APPLICATIO U Top Silkscreen 640220fa 14 LT6402-20 PACKAGE DESCRIPTIO U UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) 0.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ± 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 15 16 0.40 ± 0.10 1 1.45 ± 0.10 (4-SIDES) 2 PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER (UD16) QFN 0904 3.50 ± 0.05 1.45 ± 0.05 2.10 ± 0.05 (4 SIDES) 3.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 640220fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6402-20 TYPICAL APPLICATIO R18 0Ω GND TP1 ENABLE 1 R2 0Ω R4 49.9Ω C2 0.1µF 1 T1 5 1:1 Z-RATIO 1 2 1 J2 +IN 0dB 4 M/A-COM ETC1-1T 3 C1 0.1µF 1 R1 [1] R3 49.9Ω 2 VCC C10 2 0.01µF 1 R5 0Ω 2 2 14 0dB 15 +INB 12 R6 0Ω 13 VEEC –INB 11 ENABLE 10 9 –OUT R10 8 24.9Ω R8 [1] R7 [1] R9 24.9Ω L1 [1] 2 1 C4 0.1µF 1 2 T2 3 4:1 Z-RATIO 4 C8 [1] C3 0.1µF 1 2 1 2 C13 0.01µF C16 [1] 2 1 C22 0.1µF R13 [1] 1 2 C11 [1] R14 0Ω 1 SW1 2 VCC 3 2 R16 0Ω 1 C17 1000pF 2 1 C18 0.01µF J1 –IN C21 0.1µF • +OUTFILTERED 6 1 R11 75Ω MINI5 +8dB CIRCUITS TCM 4-19 • VCC R19 14k J3 VOCM R20 11k J6 TEST IN 5 T3 1:4 1 2 3 C19, 0.1µF 1 2 R21 [1] C6 0.1µF 1 2 • 1 2 4 MINICIRCUITS TCM 4-19 VCC 1 MINI5 CIRCUITS TCM 4-19 TP2 VCC 1 2 1 C14 4.7µF 2 1 C15 1µF NOTES: UNLESS OTHERWISE SPECIFIED, [1] DO NOT STUFF. TP3 GND 1 • RELATED PARTS PART NUMBER LT1993-2 LT1993-4 LT1993-10 LT5514 LT6600-5 LT6600-10 LT6600-20 LT6402-6 LT6402-12 LT6411 DESCRIPTION 800MHz Differential Amplifier/ADC Driver 900MHz Differential Amplifier/ADC Driver 700MHz Differential Amplifier/ADC Driver Ultralow Distortion IF Amplifier/ADC Driver Very Low Noise Differential Amplifier and 10MHz Lowpass Filter Very Low Noise Differential Amplifier and 20MHz Lowpass Filter 300MHz Differential Amplifier/ADC Driver 300MHz Differential Amplifier/ADC Driver COMMENTS AV = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz AV = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz AV = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz Digitally Controlled Gain Output IP3 47dBm at 100MHz 82dB S/N with 3V Supply, SO-8 Package 76dB S/N with 3V Supply, SO-8 Package AV = 6dB, en = 3.8nV/√Hz at 20MHz, 150mV AV = 12dB, en = 2.6nV/√Hz at 20MHz, 150mV Very Low Noise Differential Amplifier and 5MHz Lowpass Filter 82dB S/N with 3V Supply, SO-8 Package 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier 3300V/µs Slew Rate, 16mA Current Consumption, Selectable Gain: AV = –1, +1, +2 640220fa LT 0706 • PRINTED IN USA 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005 U Demo Circuit DC954A Schematic (AC Test Circuit) R17 0Ω VCC VCC VCCB VEEB R12 75Ω –INA –OUTFILTERED LT6402-20 7 J4 –OUT +18.8dB R15 [1] +14dB 2 J5 +OUT 16 +INA VCCC 1 VOCM 2 VCCA 3 +OUT VEEA 4 5 VCC 2 1 C9 2 1000pF 1 2 1 C12 1000pF 2 1 C7 0.01µF C5 0.1µF 1 2 R22 [1] C20, 0.1µF 3 2 T4 4:1 4 J7 TEST OUT 6402 TA02 • • • •