LT6402IUD-6-TR

FEATURES n n n n n n n n n n LT6402-6 300MHz Low Distortion, Low Noise Differential Amplifier/ ADC Driver (AV = 6dB) DESCRIPTION The LT®6402-6 is a low distortion, low noise differential amplifier/ADC driver for use in applications from DC to 300MHz. The LT6402-6 has been designed for ease of use, with minimal support circuitry required. Exceptionally low input-referred noise and low distortion (with either single-ended or differential inputs) make the LT6402-6 an excellent solution for driving high speed 12-bit and 14-bit ADCs. In addition to the normal unfiltered outputs (+OUT and –OUT), the LT6402-6 has a built-in 75MHz differential low pass filter and an additional pair of filtered outputs (+OUTFILTERED, –OUTFILTERED) to reduce external filtering components when driving high speed ADCs. The output common mode voltage is easily set via the VOCM pin, eliminating an output transformer or AC-coupling capacitors in many applications. The LT6402-6 is designed to meet the demanding requirements of communications transceiver applications. It can be used as a differential ADC driver, a general-purpose differential gain block, or in other applications requiring differential drive. The LT6402-6 can be used in data acquisition systems required to function at frequencies down to DC. The LT6402-6 operates on a 5V supply and consumes 30mA. It comes in a compact 16-lead 3mm × 3mm QFN package and operates over a –40°C to 85°C temperature range. 300 MHz –3dB Bandwidth Fixed Gain of 6dB Low Distortion: 49dBm OIP3, –85dBc HD3 (20MHz, 2VP-P) Low Noise: 18.6dB NF en = 3.8nV/√Hz (20MHz) , Differential Inputs and Outputs Additional Filtered Outputs Adjustable Output Common Mode Voltage DC- or AC-Coupled Operation Minimal Support Circuitry Required Small 0.75mm Profile 16-Lead 3mm × 3mm QFN Package APPLICATIONS n n n n n n n Differential ADC Driver for: Imaging Communications Differential Driver/Receiver Single Ended to Differential Conversion Differential to Single Ended Conversion Level Shifting IF Sampling Receivers SAW Filter Interfacing/Buffering L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 5V 0.1μF 0.1μF –INB –INA 0.1μF 0.1μF IF IN +INB +INA VEE 64026 TA01a Distortion vs Frequency, Differential Input, No RLOAD –40 –50 DISTORTION (dBc) –60 –70 –80 –90 HD2 –100 1 10 FREQUENCY (MHz) 100 64026 TA01b FILTERED OUTPUTS VOUT = 2VP-P VCC VOCM +OUT LT6402-6 –OUT 10Ω 10Ω AIN+ VCM LTC®2249 AIN– HD3 64026fa 1 LT6402-6 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW +INA +INB –INA –INB 12 VEEC 17 11 ENABLE 10 VCCB 9 5 +OUT 6 +OUTFILTERED 7 –OUTFILTERED 8 –OUT VEEB Total Supply Voltage (VCCA/VCCB/VCCC to VEEA/VEEB/VEEC) ...................................................5.5V Input Current (+INA, –INA, +INB, –INB, VOCM, ENABLE)................................................±10mA Output Current (Continuous) +OUT, –OUT ...................................................±100mA +OUTFILTERED, –OUTFILTERED ......................±30mA Output Short-Circuit Duration (Note 2) ............ Indefinite Operating Temperature Range (Note 3).... –40°C to 85°C Specified Temperature Range (Note 4) .... –40°C to 85°C Storage Temperature Range................... –65°C to 125°C Junction Temperature ........................................... 125°C 16 15 14 13 VCCC 1 VOCM 2 VCCA 3 VEEA 4 UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W EXPOSED PAD IS VEE (PIN 17) MUST BE SOLDERED TO THE PCB ORDER INFORMATION LEAD FREE FINISH LT6402CUD-6#PBF LT6402IUD-6#PBF LEAD BASED FINISH LT6402CUD-6 LT6402IUD-6 TAPE AND REEL LT6402CUD-6#TRPBF LT6402IUD-6#TRPBF TAPE AND REEL LT6402CUD-6#TR LT6402IUD-6#TR PART MARKING* LBZZ LBZZ PART MARKING* LBZZ LBZZ PACKAGE DESCRIPTION 16-Lead (3mm × 3mm) Plastic QFN 16-Lead (3mm × 3mm) Plastic QFN PACKAGE DESCRIPTION 16-Lead (3mm × 3mm) Plastic QFN 16-Lead (3mm × 3mm) Plastic QFN TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. SYMBOL GDIFF VSWINGMIN VSWINGMAX VSWINGDIFF IOUT VOS Output Voltage Swing Output Current Drive Input Offset Voltage PARAMETER Gain CONDITIONS Differential (+OUT, –OUT), VIN = ±800mV Differential Single-Ended +OUT, –OUT, +OUTFILTERED, –OUTFILTERED, VIN = ±2.2V Differential Single-Ended +OUT, –OUT, +OUTFILTERED, –OUTFILTERED, VIN = ±2.2V Differential Differential (+OUT, –OUT), VIN = ±2.2V Differential l l l l l l DC ELECTRICAL CHARACTERISTICS MIN 5.8 TYP 6 0.25 MAX 6.3 0.35 0.5 UNITS dB V V V V VP-P VP-P mA Input/Output Characteristics (+INA, +INB, –INA, –INB, +OUT, –OUT, +OUTFILTERED, –OUTFILTERED) 3.4 3.3 6.1 5.6 ±30 –6.5 –10 3.6 7 ±35 1 6.5 10 mV mV 64026fa 2 LT6402-6 DC ELECTRICAL CHARACTERISTICS SYMBOL TCVOS IVRMIN IVRMAX RINDIFF CINDIFF CMRR ROUTDIFF COUTDIFF GCM VOCMMIN VOCMMAX VOSCM IBIASCM RINCM CINCM ENABLE Pin VIL VIH IIL IIH Power Supply VS IS ISDISABLED PSRR Operating Range Supply Current Supply Current (Disabled) Power Supply Rejection Ratio ENABLE = 0.8V ENABLE = 2V 4V to 5.5V l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. PARAMETER Input Offset Voltage Drift Input Voltage Range, MIN Input Voltage Range, MAX Input Resistance Input Capacitance Common Mode Rejection Ratio Output Resistance Output Capacitance Common Mode Gain Output Common Mode Voltage Adjustment Range, MIN Output Common Mode Voltage Adjustment Range, MAX Output Common Mode Offset Voltage VOCM Input Bias Current VOCM Input Resistance VOCM Input Capacitance ENABLE Input Low Voltage ENABLE Input High Voltage ENABLE Input Low Current ENABLE Input High Current ENABLE = 0.8V ENABLE = 2V l l l l CONDITIONS TMIN to TMAX Single-Ended Single-Ended l l l l MIN TYP 2.5 MAX –0.1 UNITS μV/°C V V Ω pF dB Ω pF 5.1 170 42 200 1 65 0.3 0.8 240 Input Common Mode –0.1V to 5.1V l Common Mode Voltage Control (VOCM Pin) Differential (+OUT, –OUT), VOCM = 1.2V to 3.6V Differential (+OUT, –OUT), VOCM = 1.4V to 3.4V l l 0.9 0.9 1 1.1 1.1 1.2 1.4 V/V V/V V V V V Single-Ended Measured from VOCM to Average of +OUT and –OUT l 3.6 3.4 –30 4 5 0.8 3 1 0.8 2 0.5 1 4 24 55 5 30 250 90 3 5.5 37 500 30 15 mV μA MΩ pF V V μA μA V mA μA dB l l 64026fa 3 LT6402-6 AC ELECTRICAL CHARACTERISTICS SYMBOL –3dBBW 0.1dBBW 0.5dBBW SR ts1% tON tOFF –3dBBWCM SRCM 10MHz Signal Second/Third Harmonic Distortion Third-Order IMD OIP310M NF en10M 20MHz Signal Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) 2VP-P Differential (+OUT, –OUT) 2VP-P Differential Composite (+OUTFILTERED, –OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz 2VP-P Differential Composite (+OUT, –OUT), RL = 400Ω, f1 = 19.5MHz, f2 = 20.5MHz OIP320M NF en20M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100Ω (Note 5) Differential (+OUTFILTERED, –OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz Measured Using DC954A Demo Board (Note 5) –84 –73 –90 –71 49 18.6 3.8 17.7 dBc dBc dBc dBc dBm dB nV/√Hz dBm Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100Ω (Note 5) 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) 2VP-P Differential (+OUT, –OUT) 2VP-P Differential Composite (+OUTFILTERED, –OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz Differential (+OUTFILTERED, –OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz (Note 5) Measured Using DC954A Demo Board –86 –84 –101 53 18.6 3.8 20.7 dBc dBc dBc dBm dB nV/√Hz dBm PARAMETER –3dB Bandwidth Bandwidth for 0.1dB Flatness Bandwidth for 0.5dB Flatness Slew Rate 1% Settling Turn-On Time Turn-Off Time Common Mode Small-Signal –3dB Bandwidth Common Mode Slew Rate 0.1VP-P at VOCM, Measured Single-Ended at +OUT and –OUT 1.3V to 3.4V Step at VOCM Input/Output Characteristics 100mVP-P Differential (+OUT, –OUT) 100mVP-P Differential (+OUT, –OUT) 100mVP-P Differential (+OUT, –OUT) 3.2VP-P Differential (+OUT, –OUT) 1% Settling for a 1VP-P Differential Step (+OUT, –OUT) 200 300 30 80 400 10 200 1.8 200 250 MHz MHz MHz V/μs ns ns μs MHz V/μs TA = 25°C, VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. CONDITIONS MIN TYP MAX UNITS Common Mode Voltage Control (VOCM Pin) Noise/Harmonic Performance Input/Output Characteristics 64026fa 4 LT6402-6 AC ELECTRICAL CHARACTERISTICS SYMBOL 25MHz Signal Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential (+OUTFILTERED, –OUTFILTERED) 2VP-P Differential (+OUT, –OUT) 2VP-P Differential Composite (+OUTFILTERED, –OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz 2VP-P Differential Composite (+OUT, –OUT), RL = 400Ω, f1 = 24.5MHz, f2 = 25.5MHz OIP325M NF en25M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100Ω (Note 5) Differential (+OUTFILTERED, –OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz (Note 5) Measured Using DC954A Demo Board –84 –69 –88 –67 47 12.6 3.9 17.2 dBc dBc dBc dBc dBm dB nV/√Hz dBm PARAMETER TA = 25°C, VCCA = VCCB = VCCC = 5V,VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted. CONDITIONS MIN TYP MAX UNITS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Note 3: The LT6402 is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 4: The LT6402C is guaranteed to meet specified performance from 0°C to 70°C. It is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6402I is guaranteed to meet specified performance from –40°C to 85°C. Note 5: Since the LT6402-6 is a feedback amplifier with low output impedance, a resistive load is not required when driving an ADC. Therefore, typical output power is very small. In order to compare the LT6402-6 with typical gm amplifiers that require 50Ω output loading, the LT6402-6 output voltage swing driving an ADC is converted to OIP3 and P1dB as if it were driving a 50Ω load. TYPICAL PERFORMANCE CHARACTERISTICS Frequency Response, RLOAD = 400Ω 15 10 UNFILTERED 5 FILTERED GAIN (dB) GAIN (dB) 0 –5 –10 VIN = 100mVP-P –15 UNFILTERED: R LOAD = 400Ω FILTERED: RLOAD = 300Ω –20 (EXTERNAL) + 100Ω (INTERNAL, FILTERED OUTPUTS) –25 10 100 1 FREQUENCY (MHz) 30 25 20 15 GAIN (dB) 10 5 0 –5 –10 –15 1000 64026 G01 Frequency Response vs CLOAD, RLOAD = 400Ω 15 12 9 6 3 0 –3 –6 –9 –12 –15 –18 –21 –24 –27 –30 Frequency Response, RLOAD = 100Ω UNFILTERED OUTPUTS FILTERED OUTPUTS –20 1 0pF 1.6pF 5pF 10pF 10 100 FREQUENCY (MHz) 1000 64026 G02 VIN = 100mVP-P UNFILTERED: RLOAD = 100Ω FILTERED: RLOAD = 100Ω (INTERNAL, FILTERED OUTPUTS) 1 10 100 FREQUENCY (MHz) 1000 64026 G03 64026fa 5 LT6402-6 TYPICAL PERFORMANCE CHARACTERISTICS Third Order Intermodulation Distortion vs Frequency, Differential Input, No RLOAD –45 2 TONES 2VP-P COMPOSITE –55 1MHz TONE SPACING THIRD ORDER IMD (dBc) THIRD ORDER IMD (dBc) –65 –75 –85 –95 –105 FILTERED OUTPUTS UNFILTERED OUTPUTS –40 Third Order Intermodulation Distortion vs Frequency, Differential Input, RLOAD = 400Ω 2 TONES 2VP-P COMPOSITE –50 1MHz TONE SPACING –60 UNFILTERED OUTPUTS –70 –80 –90 –100 FILTERED OUTPUTS OUTPUT IP3 (dBm) 60 55 Output Third Order Intercept vs Frequency, Differential Input, No RLOAD FILTERED OUTPUTS 50 45 UNFILTERED OUTPUTS 40 35 30 25 5 10 5 10 15 20 25 FREQUENCY (MHz) 30 35 5 10 15 20 25 FREQUENCY (MHz) 30 35 25 20 15 FREQUENCY (MHz) 30 35 64026 G06 64026 G04 64026 G05 Output Third Order Intercept vs Frequency, Differential Input, RLOAD = 400Ω 51 47 OUTPUT IP3 (dB) 43 39 35 UNFILTERED OUTPUTS FILTERED OUTPUTS DISTORTION (dBc) –40 –50 Distortion vs Frequency, Differential Input, No RLOAD FILTERED OUTPUTS VOUT = 2VP-P –40 –50 DISTORTION (dBc) –60 –70 Distortion vs Frequency, Differential Input, No RLOAD UNFILTERED OUTPUTS VOUT = 2VP-P –60 –70 –80 –90 HD2 HD3 –80 –90 HD2 HD3 31 2 TONES 2VP-P COMPOSITE 1MHz TONE SPACING 27 25 10 20 15 5 FREQUENCY (MHz) 30 35 64026 G07 –100 1 10 FREQUENCY (MHz) 100 64026 G08 –100 1 10 FREQUENCY (MHz) 100 64026 G09 Distortion vs Output Amplitude, 20MHz Differential Input, No RLOAD –70 –75 –75 DISTORTION (dBc) –80 –85 –90 –95 –100 0 1 2345678 OUTPUT AMPLITUDE (dBm) 9 10 –90 DISTORTION (dBc) HD2 HD3 FILTERED OUTPUTS –70 Distortion vs Output Amplitude, 20MHz Differential Input, No RLOAD UNFILTERED OUTPUTS OUTPUT 1dB COMPRESSION (dBm) 25 20 15 10 5 0 –5 –10 –15 –20 Output 1dB Compression vs Frequency UNFILTERED OUTPUTS 400Ω LOAD 100Ω LOAD HD2 –80 HD3 –85 0 1 2345678 OUTPUT AMPLITUDE (dBm) 9 10 1 10 100 FREQUENCY (MHz) 1000 64026 G12 64206 G10 64026 G11 64026fa 6 LT6402-6 TYPICAL PERFORMANCE CHARACTERISTICS Noise Figure vs Frequency MEASURED USING DC954 DEMO BOARD INPUT REFERRED NOISE VOLTAGE (nV/√Hz) 40 35 NOISE FIGURE (dB) 30 25 20 15 10 10 100 FREQUENCY (MHz) 1000 64026 G13 Input Referred Noise Voltage vs Frequency 35 30 25 20 15 10 5 0 10 100 FREQUENCY (MHz) 1000 64206 G14 Reverse Isolation vs Frequency 0 –20 ISOLATION (dB) –40 –60 –80 UNFILTERED OUTPUTS –100 –120 1 10 100 FREQUENCY (MHz) 1000 64026 G15 Differential Input Impedance vs Frequency INPUT IMPEDANCE (MAGNITUDE Ω, PHASE) 500 400 OUTPUT IMPEDANCE (Ω) 300 200 100 IMPEDANCE PHASE 0 –100 1 10 100 FREQUENCY (MHz) 1000 64026 G16 Differential Output Impedance vs Frequency 100 INPUT REFLECTION COEFFICIENT (S11) UNFILTERED OUTPUTS 0 –5 –10 –15 –20 –25 –30 –35 Input Reflection Coefficient vs Frequency MEASURED USING DC954 DEMO BOARD IMPEDANCE MAGNITUDE 10 1 10 100 FREQUENCY (MHz) 1000 64206 G17 1 10 100 FREQUENCY (MHz) 1000 64026 G18 Output Reflection Coefficient vs Frequency OUTPUT REFLECTION COEFFICIENT (S22) MEASURED USING –5 DC954 DEMO BOARD –10 PSRR, CMRR (dB) –15 –20 –25 –30 –35 –40 1 10 100 FREQUENCY (MHz) 1000 64026 G19 PSRR, CMRR vs Frequency 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10 100 FREQUENCY (MHz) 1000 64026 G20 Small-Signal Transient Response 2.280 2.260 0 UNFILTERED OUTPUTS PSRR VOLTAGE (V) CMRR 2.240 2.220 2.200 2.180 2.160 2.140 2.120 TIME (5ns/DIV) 64026 G21 64026fa 7 LT6402-6 TYPICAL PERFORMANCE CHARACTERISTICS Overdrive Recovery Time 4.0 +OUT 3.5 OUTPUT VOLTAGE (V) 3.0 DISTORTION (dBc) 2.5 2.0 1.5 1.0 0.5 0 TIME (25ns/DIV) 64026 G22 Distortion vs Output Common Mode Voltage, LT6402-6 Driving an LTC2249 14-Bit ADC –60 FILTERED OUTPUTS –65 NO RLOAD VOUT = 20MHz 2VP-P –70 –75 –80 HD2 –85 –90 HD3 VOLTAGE (V) 4.0 Turn-On Time RLOAD = 100Ω 3.5 PER OUTPUT 3.0 +OUT 2.5 2.0 –OUT 1.5 1.0 0.5 ENABLE TIME (125ns/DIV) 64026 G24 RLOAD = 100Ω PER OUTPUT –OUT –95 –100 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 OUTPUT COMMON MODE VOLTAGE (V) 64026 G23 0 Turn-Off Time 4.0 RLOAD = 100Ω PER OUTPUT 3.5 3.0 VOLTAGE (V) 2.5 2.0 –OUT 1.5 1.0 0.5 0 TIME (250ns/DIV) 64026 G25 10MHz 8192 Point FFT, LT6402-6 Driving an LTC2249 14-Bit ADC 0 –10 8192 POINT FFT f = 10MHz, –1dBFS –20 IN FILTERED OUTPUTS –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) 64026 G26 20MHz 8192 Point FFT, LT6402-6 Driving an LTC2249 14-Bit ADC 0 –10 8192 POINT FFT f = 20MHz, –1dBFS –20 IN FILTERED OUTPUTS –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) 64026 G27 +OUT ENABLE AMPLITUDE (dBFS) 25MHz 8192 Point FFT, LT6402-6 Driving an LTC2249 14-Bit ADC 0 –10 8192 POINT FFT f = 25MHz, –1dBFS –20 IN FILTERED OUTPUTS –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) 64026 G28 20MHz 2-Tone 32768 Point FFT, LT6402-6 Driving an LTC2249 14-Bit ADC 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 32768 POINT FFT TONE 1 AT 19.5MHz, –7dBFS TONE 2 AT 20.5MHz, –7dBFS FILTERED OUTPUTS AMPLITUDE (dBFS) AMPLITUDE (dBFS) 2.5 AMPLITUDE (dBFS) 5 7.5 10 12.5 15 17.5 20 22.5 FREQUENCY (MHz) 64026 G29 64026fa 8 LT6402-6 PIN FUNCTIONS VOCM (Pin 2): This pin sets the output common mode voltage. Without additional biasing, both inputs bias to this voltage as well. This input is high impedance. VCCA, VCCB, VCCC (Pins 3, 10, 1): Positive Power Supply (Normally Tied to 5V). All three pins must be tied to the same voltage. Bypass each pin with 1000pF and 0.1μF capacitors as close to the package as possible. Split supplies are possible as long as the voltage between VCC and VEE is 5V. VEEA, VEEB, VEEC (Pins 4, 9, 12): Negative Power Supply (Normally Tied to Ground). All three pins must be tied to the same voltage. Split supplies are possible as long as the voltage between VCC and VEE is 5V. If these pins are not tied to ground, bypass each pin with 1000pF and 0.1μF capacitors as close to the package as possible. +OUT, –OUT (Pins 5, 8): Outputs (Unfiltered). These pins are high bandwidth, low-impedance outputs. The DC output voltage at these pins is set to the voltage applied at VOCM. +OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered Outputs. These pins add a series 50Ω resistor from the unfiltered outputs and three 14pF capacitors. Each output has 14pF to VEE, plus an additional 14pF between each pin (See the Block Diagram). This filter has a –3dB bandwidth of 75MHz. ENABLE (Pin 11): This pin is a TTL logic input referenced to the VEEC pin. If low, the LT6402-6 is enabled and draws typically 30mA of supply current. If high, the LT6402-6 is disabled and draws typically 250μA. +INA, +INB (Pins 15, 16): Positive Inputs. These pins are normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. –INA, –INB (Pins 14, 13): Negative Inputs. These pins are normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split supplies are used, DO NOT tie the pad to ground. 64026fa 9 LT6402-6 BLOCK DIAGRAM 200Ω –INA 14 –INB 13 200Ω VCCA VEEA 14pF +OUT A 5 +OUTFILTERED VEEA 200Ω VCCC 50Ω 6 VOCM 200Ω – + + C 14pF 2 – 200Ω +INA 16 +INB 15 200Ω VCCB VEEC 50Ω 200Ω –OUTFILTERED 7 –OUT B 8 14pF VEEB 200Ω + – VEEB BIAS 3 VCCA 10 VCCB 1 VCCC 11 ENABLE 4 VEEA 9 VEEB 12 VEEC 64026 BD APPLICATIONS INFORMATION Circuit Description The LT6402-6 is a low noise, low distortion differential amplifier/ADC driver with: • –3dB bandwidth DC to 300MHz • Fixed gain independent of RLOAD 2V/V (6dB) • Differential input impedance 200Ω • Low output impedance • Built-in, user adjustable output filtering • Requires minimal support circuitry Referring to the block diagram, the LT6402-6 uses a closed-loop topology which incorporates 3 internal amplifiers. Two of the amplifiers (A and B) are identical and drive the differential outputs. The third amplifier is used to set the output common mode voltage. Gain and input impedance are set by the 200Ω resistors in the internal feedback network. Output impedance is low, determined by the inherent output impedance of amplifiers A and B, and further reduced by internal feedback. The LT6402-6 also includes built-in single-pole output filtering. The user has the choice of using the unfiltered outputs, the filtered outputs (75MHz –3dB lowpass), or modifying the filtered outputs to alter frequency response by adding additional components. Many lowpass and bandpass filters are easily implemented with just one or two additional components. 64026fa 10 LT6402-6 APPLICATIONS INFORMATION The LT6402-6 has been designed to minimize the need for external support components such as transformers or AC-coupling capacitors. As an ADC driver, the LT6402-6 requires no external components except for power-supply bypass capacitors. This allows DC-coupled operation for applications that have frequency ranges including DC. At the outputs, the common mode voltage is set via the VOCM pin, allowing the LT6402-6 to drive ADCs directly. No output AC-coupling capacitors or transformers are needed. At the inputs, signals can be differential or single-ended with virtually no difference in performance. Furthermore, DC levels at the inputs can be set independently of the output common mode voltage. These input characteristics often eliminate the need for an input transformer and/or AC-coupling capacitors. Input Impedance and Matching Networks Calculation of the input impedance of the LT6402-6 is not straightforward from examination of the block diagram because of the internal feedback network. In addition, the input impedance when driven differentially is different than when driven single-ended. DIFFERENTIAL LT6402-6 200Ω SINGLE-ENDED 133Ω IF IN– ZIN = 50Ω DIFFERENTIAL IF IN+ 33Ω 33Ω LT6402-6 15 16 +INB +INA +OUT 13 14 –INB –INA –OUT Single-Ended to Differential Operation The LT6402-6’s performance with single-ended inputs is comparable to its performance with differential inputs. This excellent single-ended performance is largely due to the internal topology of the LT6402-6. Referring to the block diagram, if the +INA and +INB pins are driven with a single-ended signal (while –INA and –INB are tied to AC ground), then the +OUT and –OUT pins are driven differentially without any voltage swing needed from amplifier C. Single-ended to differential conversion using more conventional topologies suffers from performance limitations due to the common mode amplifier. Driving ADCs The LT6402-6 has been specifically designed to interface directly with high speed Analog to Digital Converters (ADCs). In general, these ADCs have differential inputs, with an input impedance of 1kΩ or higher. In addition, there is generally some form of lowpass or bandpass filtering just prior to the ADC to limit input noise at the ADC, thereby improving system signal to noise ratio. Both the unfiltered and filtered outputs of the LT6402-6 can easily drive the For single-ended 50Ω applications, an 80.6Ω shunt matching resistor to ground will result in the proper input termination (Figure 1). For differential inputs there are several termination options. If the input source is 50Ω differential, then the input matching can be accomplished by either a 67Ω shunt resistor across the inputs (Figure 3), or equivalent 33Ω shunt resistors on each of the inputs to ground (Figure 2). 8 5 64026 F02 Figure 2. Input Termination for Differential 50Ω Input Impedance 13 14 0.1μF IF IN 80.6Ω ZIN = 50Ω SINGLE-ENDED 15 16 13 –INB –INA –OUT LT6402-6 +INB +INA +OUT 8 IF IN– ZIN = 50Ω DIFFERENTIAL 5 64026 F01 –INB –INA –OUT LT6402-6 14 8 67Ω 15 +INB +INA IF IN+ 16 +OUT 5 64026 F03 Figure 1. Input Termination for Single-Ended 50Ω Input Impedance Figure 3. Alternate Input Termination for Differential 50Ω Input Impedance 64026fa 11 LT6402-6 APPLICATIONS INFORMATION high impedance inputs of these differential ADCs. If the filtered outputs are used, then cutoff frequency and the type of filter can be tailored for the specific application if needed. Wideband Applications (Using the +OUT and –OUT Pins) In applications where the full bandwidth of the LT6402-6 is desired, the unfiltered output pins (+OUT and –OUT) should be used. They have a low output impedance; therefore, gain is unaffected by output load. Capacitance in excess of 5pF placed directly on the unfiltered outputs results in additional peaking and reduced performance. When driving an ADC directly, a small series resistance is recommended between the LT6402-6’s outputs and the ADC inputs (Figure 4). This resistance helps eliminate any resonances associated with bond wire inductances of either the ADC inputs or the LT6402-6’s outputs. A value between 10Ω and 25Ω gives excellent results. resistor/capacitor combination creates filtered outputs that look like a series 50Ω resistor with a 42pF capacitor shunting each filtered output to AC ground, giving a –3dB bandwidth of 75MHz. The filter cutoff frequency is easily modified with just a few external components. To increase the cutoff frequency, simply add 2 equal value resistors, one between +OUT and +OUTFILTERED and the other between –OUT and –OUTFILTERED (Figure 6). These resistors are in parallel with the internal 50Ω resistor, lowering the overall resistance and increasing filter bandwidth. To double the filter bandwidth, for example, add two external 50Ω resistors to lower the series resistance to 25Ω. The 42pF of capacitance remains unchanged, so filter bandwidth doubles. To decrease filter bandwidth, add two external capacitors, one from +OUTFILTERED to ground, and the other from –OUTFILTERED to ground. A single differential capacitor connected between +OUTFILTERED and –OUTFILTERED LT6402-6 VEE 8 10Ω TO 25Ω 14pF 50Ω 7 –OUTFILTERED ADC 10Ω TO 25Ω +OUT 5 64026 F04 8 –OUT –OUT LT6402-6 14pF 50Ω 6 +OUTFILTERED 14pF VEE 5 +OUT 64026 F05 FILTERED OUTPUT (75MHz) Figure 4. Adding Small Series R at LT6402-6 Output Figure 5. LT6402-6 Internal Filter Topology –3dB BW ≈75MHz Filtered Applications (Using the +OUTFILTERED and –OUTFILTERED Pins) Filtering at the output of the LT6402-6 is often desired to provide either anti-aliasing or improved signal to noise ratio. To simplify this filtering, the LT6402-6 includes an additional pair of differential outputs (+OUTFILTERED and –OUTFILTERED) which incorporate an internal lowpass filter network with a –3dB bandwidth of 75MHz (Figure 5). These pins each have an output impedance of 50Ω. Internal capacitances are 14pF to VEE on each filtered output, plus an additional 14pF capacitor connected differentially between the two filtered outputs. This LT6402-6 VEE 14pF 50Ω 14pF 50Ω 8 –OUT 50Ω 7 –OUTFILTERED FILTERED OUTPUT (150MHz) 6 +OUTFILTERED 14pF VEE 5 +OUT 64026 F06 50Ω Figure 6. LT6402-6 Internal Filter Topology Modified for 2x Filter Bandwidth (2 External Resistors) 64026fa 12 LT6402-6 APPLICATIONS INFORMATION can also be used, but since it is being driven differentially it will appear at each filtered output as a single-ended capacitance of twice the value. To halve the filter bandwidth, for example, two 42pF capacitors could be added (one from each filtered output to ground). Alternatively one 21pF capacitor could be added between the filtered outputs, again halving the filter bandwidth. Combinations of capacitors could be used as well; a three capacitor solution of 14pF from each filtered output to ground plus a 14pF capacitor between the filtered outputs would also halve the filter bandwidth (Figure 7). Bandpass filtering is also easily implemented with just a few external components. An additional 560pF and 62nH, each added differentially between +OUTFILTERED and –OUTFILTERED creates a bandpass filter with a 26MHz center frequency, –3dB points of 23MHz and 30MHz, and 1.6dB of insertion loss (Figure 8). LT6402-6 VEE 14pF 50Ω 7 –OUTFILTERED 14pF 50Ω 6 +OUTFILTERED 14pF VEE 5 +OUT 64026 F07 Output Common Mode Adjustment The LT6402-6’s output common mode voltage is set by the VOCM pin. It is a high-impedance input, capable of setting the output common mode voltage anywhere in a range from 1.1V to 3.6V. Bandwidth of the VOCM pin is typically 200MHz, so for applications where the VOCM pin is tied to a DC bias voltage, a 0.1μF capacitor at this pin is recommended. For best distortion performance, the voltage at the VOCM pin should be between 1.2V and 2.6V. When interfacing with most ADCs, there is generally a VOCM output pin that is at about half of the supply voltage of the ADC. For 5V ADCs such as the LTC17XX family, this VOCM output pin should be connected directly (with the addition of a 0.1μF capacitor) to the input VOCM pin of the LT6402-6. For 3V ADCs such as the LTC22XX families, the LT6402-6 will function properly using the 1.65V from the ADC’s VCM reference pin, but improved Spurious Free Dynamic Range (SFDR) and distortion performance can be achieved by level-shifting the LTC22XX’s VCM reference voltage up to at least 1.8V. This can be accomplished as shown in Figure 9 by using a resistor divider between the LTC22XX’s VCM output pin and VCC and then bypassing the LT6402-6’s VOCM pin with a 0.1μF capacitor. For a common mode voltage above 1.9V, AC coupling capacitors are recommended between the LT6402-6 and LTC22XX ADCs because of the input voltage range constraints of the ADC. 3V 8 –OUT 14pF FILTERED OUTPUT (37.5MHz) 14pF 14pF Figure 7. LT6402-6 Internal Filter Topology Modified for 1/2x Filter Bandwidth (3 External Capacitors) LT6402-6 VEE 14pF 50Ω 7 –OUTFILTERED 0.1μF 15 IF IN 80.6Ω 16 8 –OUT 0.1μF 13 14 –INB –INA 2 VOCM +OUTFILTERED LT6402-6 –OUTFILTERED +INB +INA 14pF 50Ω 6 +OUTFILTERED 14pF VEE 5 +OUT 64026 F08 11k 1.9V 4.02k 31 1.5V 6 10Ω 10Ω 7 2 1 VCM AIN+ LTC22xx AIN– 64026 F09 FILTERED OUTPUT Figure 9. Level Shifting 3V ADC VCM Voltage for Improved SFDR Figure 8. LT6402-6 Output Filter Modified for Bandpass Filtering (1 External Inductor, 1 External Capacitor) 64026fa 13 LT6402-6 APPLICATIONS INFORMATION Large Output Voltage Swings The LT6402-6 has been designed to provide the 3.2VP-P output swing needed by the LTC1748 family of 14-bit low-noise ADCs. This additional output swing improves system SNR by up to 4dB. Input Bias Voltage and Bias Current The input pins of the LT6402-6 are internally biased to the voltage applied to the VOCM pin. No external biasing resistors are needed, even for AC-coupled operation. The input bias current is determined by the voltage difference between the input common mode voltage and the VOCM pin (which sets the output common mode voltage). For example, if the inputs are tied to 2.5V with the VOCM pin at 2.2V, then a total input bias current of 1.5mA will flow into the LT6402-6’s +INA and +INB pins. Furthermore, an additional input bias current totaling 1.5mA will flow into the –INA and –INB inputs. Application (Demo) Boards The DC954A Demo Board has been created for stand-alone evaluation of the LT6402-6 with either single-ended or differential input and output signals. As shown, it accepts a single-ended input and produces a single-ended output so that the LT6402-6 can be evaluated using standard laboratory test equipment. For more information on this Demo Board, please refer to the layout and schematic diagrams found later in this data sheet. There are also additional demo boards available that combine the LT6402-6 with a variety of different Linear Technology ADCs. Please contact the factory for more information on these demo boards. TYPICAL APPLICATION Top Silkscreen 64026fa 14 LT6402-6 PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) 0.70 ± 0.05 3.50 ± 0.05 1.45 ± 0.05 2.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ± 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 15 16 0.40 ± 0.10 1 1.45 ± 0.10 (4-SIDES) 2 PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 3.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) (UD16) QFN 0904 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 64026fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6402-6 TYPICAL APPLICATION Demo Circuit DC954A Schematic (AC Test Circuit) R18 0Ω GND TP1 ENABLE 1 R2 0Ω R4 33Ω C2 0.1μF 1 T1 5 1:1 Z-RATIO 1 2 1 J2 +IN 0dB 4 M/A-COM ETC1-1T 3 C1 0.1μF 1 R1 [1] R3 33Ω 2 VCC C10 2 0.01μF 1 R5 0Ω 2 2 14 0dB 15 +INB 12 R6 0Ω 13 VEEC –INB 11 ENABLE 10 9 –OUT 8 R10 24.9Ω R8 [1] R7 [1] R9 24.9Ω L1 [1] 2 1 C4 0.1μF 1 2 T2 3 4:1 Z-RATIO 4 C8 [1] C3 0.1μF 1 2 1 2 C11 [1] R14 0Ω 1 SW1 R17 0Ω VCC VCC 3 2 2 R16 0Ω 1 C17 1000pF 2 1 C18 0.01μF VCC VCCB VEEB R12 75Ω J1 –IN C21 0.1μF –INA LT6402-6 –OUTFILTERED 7 J4 –OUT • +OUTFILTERED 6 1 R11 75Ω 1 2 C16 [1] 2 1 MINI5 –6dB CIRCUITS TCM 4-19 • 4.8dB R15 [1] 0dB 2 • VCC R19 14k J3 VOCM R20 11k T3 1:4 • J5 +OUT 16 +INA VCCC 1 VOCM 2 VCCA 3 +OUT VEEA 4 5 VCC 2 1 C13 0.01μF C22 0.1μF R13 [1] C9 2 1000pF 1 2 1 C12 1000pF 2 1 C7 0.01μF C5 0.1μF 1 2 R22 [1] C20, 0.1μF 2 1 2 3 T4 4:1 4 J7 TEST OUT J6 TEST IN 5 1 2 C19, 0.1μF 1 2 R21 [1] C6 0.1μF 1 2 • 4 MINICIRCUITS TCM 4-19 VCC 3 1 MINI5 CIRCUITS TCM 4-19 • 64026 TA02 • • TP2 VCC 1 2 1 C14 4.7μF 2 1 C15 1μF NOTES: UNLESS OTHERWISE SPECIFIED, [1] DO NOT STUFF . TP3 GND 1 RELATED PARTS PART NUMBER LT1993-2 LT1993-4 LT1993-10 LT5514 LT6402-12 LT6402-20 LT6411 LT6600-5 LT6600-10 LT6600-20 DESCRIPTION 800MHz Differential Amplifier/ADC Driver 900MHz Differential Amplifier/ADC Driver 700MHz Differential Amplifier/ADC Driver Ultralow Distortion IF Amplifier/ADC Driver 300MHz Differential Amplifier/ADC Driver 300MHz Differential Amplifier/ADC Driver 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier Very Low Noise Differential Amplifier and 5MHz Lowpass Filter Very Low Noise Differential Amplifier and 10MHz Lowpass Filter Very Low Noise Differential Amplifier and 20MHz Lowpass Filter COMMENTS AV = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz AV = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz AV = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz Digitally Controlled Gain Output IP3 47dBm at 100MHz AV = 12dB, en = 2.6nV/√Hz at 20MHz, 150mW AV = 20dB, en = 1.9nV/√Hz at 20MHz, 150mW 3300V/μs Slew Rate, 16mA Current Consumption, Selectable Gain: AV = –1, +1, +2 82dB S/N with 3V Supply, SO-8 Package 82dB S/N with 3V Supply, SO-8 Package 76dB S/N with 3V Supply, SO-8 Package 64026fa LT 1007 REV A • PRINTED IN USA 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006