LT6411CUD

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LT6411 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier DESCRIPTION The LT®6411 is a dual amplifier with individually selectable gains of +1, +2 and –1. The amplifiers have excellent distortion performance for driving ADCs as well as excellent bandwidth and slew rate for video, data transmission and other high speed applications. Single-ended to differential conversion with a system gain of 2 is particularly straightforward by configuring one amplifier with a gain of +1 and the other amplifier with a gain of –1. The LT6411 can be used on split supplies as large as ±6V and on a single supply as low as 4.5V. Each amplifier draws only 8mA of quiescent current when enabled. When disabled, the output pins become high impedance and each amplifier draws less than 350µA. The LT6411 is manufactured on Linear Technology’s proprietary, low voltage, complimentary, bipolar process and is available in the ultra-compact, 3mm × 3mm, 16pin QFN package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 650MHz –3dB Small-Signal Bandwidth 600MHz –3dB Large-Signal Bandwidth High Slew Rate: 3300V/µs Easily Configured for Single-Ended to Differential Conversion 200MHz ±0.1dB Bandwidth User Selectable Gain of +1, +2 and –1 No External Resistors Required 46.5dBm Equivalent OIP3 at 30MHz When Driving an ADC IM3 with 2VP-P Composite, Differential Output: –87dBc at 30MHz, –83dBc at 70MHz –77dB SFDR at 30MHz, 2VP-P Differential Output 6ns 0.1% Settling Time for 2V Step Low Supply Current: 8mA per Ampifier Differential Gain of 0.02%, Differential Phase of 0.01° 50dB Channel Separation at 100MHz Wide Supply Range: ±2.25V (4.5V) to ±6.3V (12.6V) 3mm × 3mm 16-Pin QFN Package APPLICATIONS ■ ■ ■ Differential ADC Driver Single-Ended to Differential Conversion Differential Video Line Driver TYPICAL APPLICATION Differential ADC Driver 5V VCC LT6411 30MHz 2-Tone 32768 Point FFT, LT6411 Driving an LTC®2249 14-Bit ADC 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 32768 POINT FFT TONE 1 AT 29.5MHz, –7dBFS TONE 2 AT 30.5MHz, –7dBFS IM3 = –87dBc 1.9VDC 370Ω 30MHz INPUT 1.9VDC 370Ω + – 370Ω 370Ω 24Ω AIN– LTC2249 14-BIT ADC 80Msps AIN+ 6411 TA01a – + DGND EN VEE 24Ω AMPLITUDE (dBFS) 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 6411 TA01b 6411f 1 LT6411 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW IN2+ IN2– 15 Total Supply Voltage (VCC to VEE) ..........................12.6V Input Current (Note 2)..........................................±10mA Output Current (Continuous) ...............................±70mA EN to DGND Voltage (Note 2) ..................................5.5V Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C Storage Temperature Range................... –65°C to 125°C Junction Temperature ........................................... 125°C IN1– 14 16 VEE 1 VEE 2 VEE 3 NC 4 5 6 7 8 17 IN1+ 13 12 DGND 11 EN 10 VCC 9 VCC OUT2 UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W EXPOSED PAD (PIN 17) IS VEE, MUST BE SOLDERED TO PCB ORDER PART NUMBER LT6411CUD LT6411IUD OUT1 VCC VEE UD PART MARKING* LCGP LCGP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS SYMBOL VOS IIN RIN CIN VCMR PSRR IPSRR AV ERR AV MATCH VOUT PARAMETER Input Referred Offset Voltage Input Current Input Resistance Input Capacitance Maximum Input Common Mode Voltage Minimum Input Common Mode Voltage Power Supply Rejection Ratio Input Current Power Supply Rejection Gain Error Gain Matching Maximum Output Voltage Swing The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, AV = 2, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VDGND = 0V, unless otherwise noted. CONDITIONS VIN = 0V, VOS = VOUT/2 ● ● ● MIN TYP 3 –17 MAX ±10 ±20 ±50 UNITS mV mV µA kΩ pF V V dB VIN = ±1V f = 100kHz 150 500 1 VCC – 1 VEE + 1 VS (Total) = 4.5V to 12V (Note 6) VS (Total) = 4.5V to 12V (Note 6) VOUT = ±2V VOUT = ±2V RL = 1k RL = 150Ω RL = 150Ω ● ● ● 56 62 1 –1.2 ±1 ±4 ±5 µA/V % % V V V ● ● ±3.70 ±3.25 ±3.10 ±3.95 ±3.6 8 22 0.5 11 14 350 350 50 IS Supply Current, Per Amplifier Supply Current, Disabled, per Amplifier VEN = 4V VEN = Open VEN = 0.4V VEN = V+ mA mA µA µA µA µA 6411f ● ● ● ● IEN Enable Pin Current –200 –95 0.5 2 LT6411 ELECTRICAL CHARACTERISTICS SYMBOL ISC SR –3dB BW 0.1dB BW FPBW PARAMETER Output Short-Circuit Current Slew Rate Small-Signal –3dB Bandwidth Gain Flatness ±0.1dB Bandwidth Full Power Bandwidth 2V Differential Full Power Bandwidth 2V Full Power Bandwidth 4V All Hostile Crosstalk ts tr, tf dG dP Settling Time Small-Signal Rise and Fall Time Differential Gain Diffierential Phase The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, AV = 2, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VDGND = 0V, unless otherwise noted. CONDITIONS RL = 0Ω, VIN = ±1V ±1V on ±2V Output Step (Note 9) VOUT = 200mVP-P, Single Ended VOUT = 200mVP-P, Single Ended VOUT = 2VP-P Differential, –3dB VOUT = 2VP-P (Note 7) VOUT = 4VP-P (Note 7) f = 10MHz, VOUT = 2VP-P f = 100MHz, VOUT = 2VP-P 0.1% to VFINAL, VSTEP = 2V 10% to 90%, VOUT = 200mVP-P (Note 8) (Note 8) 270 ● MIN ±50 1700 TYP ±105 3300 650 200 600 525 263 –75 –50 6 550 0.02 0.01 MAX UNITS mA V/µs MHz MHz MHz MHz MHz dB dB ns ps % Deg The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = 0V, AV = 2, No RLOAD, VEN = 0.4V, VDGND = 0V, unless otherwise noted. SYMBOL 1MHz Signal HD IMD31M Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential 2VP-P Differential, RL = 200Ω Differential 2VP-P Differential Composite, f1 = 0.95MHz, f2 = 1.05MHz 2VP-P Differential Composite, f1 = 0.95MHz, f2 = 1.05MHz, RL = 200Ω Differential OIP31M NF en1M P1dB HD IMD310M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point Second/Third Harmonic Distortion Third-Order IMD (Note 10) 2VP-P Differential 2VP-P Differential, RL = 200Ω Differential 2VP-P Differential Composite, RL = 1k, f1 = 9.5MHz, f2 = 10.5MHz 2VP-P Differential Composite, f1 = 9.5MHz, f2 = 10.5MHz, RL = 200Ω Differential OIP310M NF en10M P1dB Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point (Note 10) Differential, f1 = 9.5MHz, f2 = 10.5MHz (Note 10) Single Ended Differential, f1 = 0.95MHz, f2 = 1.05MHz (Note 10) Single Ended –88 –87 –93 –91 49.5 25.1 8 19.5 –85 –76 –92 –89 49 24.7 7.7 19.5 dBc dBc dBc dBc dBm dB nV/√Hz dBm dBc dBc dBc dBc dBm dB nV/√Hz dBm PARAMETER CONDITIONS MIN TYP MAX UNITS Noise/Harmonic Performance Input/Output Characteristics 10MHz Signal 6411f 3 LT6411 ELECTRICAL CHARACTERISTICS SYMBOL HD IMD330M PARAMETER Second/Third Harmonic Distortion Third-Order IMD 30MHz Signal 2VP-P Differential 2VP-P Differential, RL = 200Ω Differential 2VP-P Differential Composite, f1 = 29.5MHz, Differential, f2 = 30.5MHz 2VP-P Differential Composite, f1 = 29.5MHz, f2 = 30.5MHz, RL = 200Ω Differential OIP330M NF en30M P1dB HD IMD370M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point Second/Third Harmonic Distortion Third-Order IMD (Note 10) 2VP-P Differential 2VP-P Differential, RL = 200Ω Differential 2VP-P Differential Composite, f1 = 69.5MHz, Differential, f2 = 70.5MHz 2VP-P Differential Composite, f1 = 69.5MHz, f2 = 70.5MHz, RL = 200Ω Differential OIP370M NF en70M P1dB Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point (Note 10) Differential, f1 = 69.5MHz, f2 = 70.5MHz (Note 10) Single Ended Differential, f1 = 29.5MHz, f2 = 30.5MHz (Note 10) Single Ended –77 –64 –87 –75 46.5 24.6 7.6 19.5 –63 –52 –83 –64 44.5 24.7 7.7 19.5 dBc dBc dBc dBc dBm dB nV/√Hz dBm dBc dBc dBc dBc dBm dB nV/√Hz dBm The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = 0V, AV = 2, No RLOAD, VEN = 0.4V, VDGND = 0V, unless otherwise noted. CONDITIONS MIN TYP MAX UNITS 70MHz Signal Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It is not production tested. Note 3: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Depending on the supply voltage, a heat sink may be required. Note 4: The LT6411C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 5: The LT6411C is guaranteed to meet specified performance from 0°C to 70°C. The LT6411C is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6411I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: The two supply voltage settings for power supply rejection are shifted from the typical ±VS points for ease of testing. The first measurement is taken at VCC = 3V, VEE = –1.5V to provide the required 3V headroom for the enable circuitry to function with EN, DGND and all inputs connected to 0V. The second measurement is taken at VCC = 8V, VEE = –4V. Note 7: Full power bandwidth is calculated from the slew rate: FPBW = SR/(π • VP-P) Note 8: Differential gain and phase are measured using a Tektronix TSG120YC/NTSC signal generator and a Tektronix 1780R video measurement set. The resolution of this equipment is better than 0.05% and 0.05°. Ten identical amplifier stages were cascaded giving an effective resolution of better than 0.005% and 0.005°. Note 9: Slew rate is 100% production tested on channel 1. Slew rate of channel 2 is guaranteed through design and characterization. Note 10: Since the LT6411 is a feedback amplifier with low output impedance, a resistive load is not required when driving an ADC. Therefore, typical output power is very small. In order to compare the LT6411 with typical gm amplifiers that require 50Ω output loading, the LT6411 output voltage swing driving an ADC is converted to OIP3 and P1dB as if it were driving a 50Ω load. 6411f 4 LT6411 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifier with single-ended outputs unless otherwise noted. Supply Current per Amplifier vs Temperature 12 10 SUPPLY CURRENT (mA) 8 6 4 2 0 –55 –35 –15 VEN = 0V VEN = 0.4V VS = ±5V RL = ∞ VIN+, VIN– = 0V SUPPLY CURRENT (mA) 12 Supply Current per Ampifier vs Supply Voltage VCC = –VEE VEN, VDGND, VIN+, VIN– = 0V 10 TA = 25°C SUPPLY CURRENT (mA) 8 6 4 2 0 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 TOTAL SUPPLY VOLTAGE (V) 6411 G02 Supply Current per Amplifier vs EN Pin Voltage TA = –55°C TA = 25°C TA = 125°C VS = ±5V VDGND = 0V VIN+, VIN– = 0V 5 25 45 65 85 105 125 TEMPERATURE (°C) 6411 G01 0 0.5 1.0 1.5 2.0 2.5 3.0 EN PIN VOLTAGE (V) 3.5 4.0 6411 G03 Output Offset Voltage vs Temperature 20 15 OFFSET VOLTAGE (mV) 10 5 0 –5 –10 –15 –20 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 6411 G04 Positive Input Bias Current vs Input Voltage 20 VS = ±5V AV = 2 EN PIN CURRENT (µA) TA = 125°C –20 TA = 25°C TA = –55°C –40 0 –20 –40 –60 –80 EN Pin Current vs EN Pin Voltage VS = ±5V VDGND = 0V VS = ±5V VIN = 0V AV = 2 IN+ BIAS CURRENT (µA) 0 TA = 125°C TA = –55°C TA = 25°C –100 –120 –60 –2.5 –1.5 0.5 –0.5 INPUT VOLTAGE (V) 1.5 2.5 6411 G05 –140 0 1 3 2 EN PIN VOLTAGE (V) 4 5 6411 G06 Output Voltage vs Input Voltage 5 VS = ±5V 4 RL = 1k AV = 1 3 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2 1 0 –1 –2 TA = –55°C –3 –4 TA = 125°C –5 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 INPUT VOLTAGE (V) 6411 G07 Output Voltage Swing vs ILOAD (Output High) 5 VS = ±5V AV = 2 VIN = 2V TA = –55°C TA = 25°C 2 TA = 125°C 1 OUTPUT VOLTAGE (V) 0 Output Voltage Swing vs ILOAD (Output Low) VS = ±5V AV = 2 VIN = –2V TA = 25°C –2 TA = 125°C TA = –55°C 4 TA = 25°C –1 3 –3 –4 0 0 10 20 30 40 50 60 70 80 90 100 SOURCE CURRENT (mA) 6411 G08 –5 0 10 20 30 40 50 60 70 80 90 100 SINK CURRENT (mA) 6411 G09 6411f 5 LT6411 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifier with single-ended outputs unless otherwise noted. Input Noise Spectral Density 1000 INPUT NOISE (nV/√Hz OR pA/√Hz) VS = ±5V AV = 2 TA = 25°C INPUT IMPEDANCE (kΩ) 1000 Positive Input Impedance vs Frequency VS = ±5V VIN = 0V TA = 25°C REJECTION RATIO (dB) 70 60 50 40 30 20 10 PSRR vs Frequency ±PSRR VS = ±5V AV = 2 TA = 25°C 100 –PSRR 100 en in 10 +PSRR 10 1 1 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 6553 G10 0.1 0.01 0.1 1 10 FREQUENCY (MHz) 100 1000 6411 G11 0 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 6411 G12 Frequency Response vs Gain Configuration 9 AV = 2, VOUT = 2VP-P 6 AV = 2, VOUT = 200mVP-P GAIN (dB) 3 AV = 1, AV = –1,VOUT = 200mVP-P 0 AV = 1, VOUT = 2VP-P –3 VS = ±5V RL = 150Ω TA = 25°C 1 AV = –1, VOUT = 2VP-P NORMALIZED GAIN (dB) 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 10 100 FREQUENCY (MHz) 1000 6411 G13 Gain Flatness vs Frequency VS = ±5V AV = 2 VOUT = 200mVP-P RL = 150Ω TA = 25°C CHANNEL 1 18 Frequency Response with Capacitive Loads VS = ±5V 16 A = 2 V 14 VOUT = 2VP-P RL = 150Ω 12 TA = 25°C 10 8 6 4 2 0 –2 –4 –6 0.1 CL = 2.2pF CL = 6.8pF CL = 12pF CHANNEL 2 –6 0.1 5.5 0.1 1 10 100 FREQUENCY (MHz) 1000 6411 G14 AMPLITUDE (dB) 1 10 100 FREQUENCY (MHz) 1000 6553 G15 Harmonic Distortion vs Frequency, Differential Input 0 –10 –20 DISTORTION (dBc) –30 –40 –50 –60 –70 –80 –90 –100 1 10 FREQUENCY (MHz) 100 6411 G16 Harmonic Distortion vs Amplitude, 30MHz, Differential Input 0 AV = 2, VCC = 5V –10 VEE = 0V, VCM = 1.6V RL = ∞ –20 TA = 25°C –30 –40 –50 –60 –70 –80 HD3 HD2 0 –10 –20 DISTORTION (dBc) –30 –40 –50 –60 –70 –80 –90 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DIFFERENTIAL OUTPUT AMPLITUDE (VP-P) 6411 G17 Harmonic Distortion vs Load, 30MHz, Differential Input VOUT = 2VP-P, DIFFERENTIAL AV = 2, VCC = 5V VEE = 0V, VCM = 1.6V TA = 25°C HD3, RL = 200Ω HD3, RL = ∞ HD2, RL = 200Ω HD2, RL = ∞ DISTORTION (dBc) VOUT = 2VP-P, DIFFERENTIAL AV = 2, VCC = 5V VEE = 0V, VCM = 1.6V DIFFERENTIAL RLOAD TA = 25°C HD3 HD2 –90 –100 –100 0 100 200 300 400 500 600 700 800 900 1000 DIFFERENTIAL RLOAD (Ω) 1011 G06 6411f 6 LT6411 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifier with single-ended outputs unless otherwise noted. Third Order Intermodulation Distortion vs Frequency, Differential Input 0 –10 –20 THIRD ORDER IMD (dBc) –30 –40 –50 –60 –70 –80 –90 –100 0 10 40 30 20 50 FREQUENCY (MHz) 60 70 0 0 RL = 200Ω RL = ∞ VOUT = 2VP-P, COMPOSITE, DIFFERENTIAL 1MHz TONE SPACING AV = 2, VCC = 5V VEE = 0V, VCM = 1.6V DIFFERENTIAL RLOAD TA = 25°C 60 50 40 OIP3 (dBm) 30 20 10 VOUT = 2VP-P, COMPOSITE, DIFFERENTIAL 1MHz TONE SPACING AV = 2, VCC = 5V VEE = 0V, VCM = 1.6V DIFFERENTIAL RLOAD TA = 25°C 10 40 30 50 20 FREQUENCY (MHz) 60 70 RL = ∞ COMPUTED FOR 50Ω ENVIRONMENT OUTPUT IMPEDANCE (Ω) 100 Output Third Order Intercept vs Frequency, Differential Input 1000 Output Impedance vs Frequency DISABLED VEN = 4V RL = 200Ω 10 1 ENABLED VEN = 0.4V 0.1 0.01 VS = ±5V RL = 150Ω TA = 25°C 100 1000 6411 G21 0.1 10 1 FREQUENCY (MHz) 6411 G19 6411 G20 Small-Signal Transient Response 0.15 0.10 0.05 OUTPUT (V) OUTPUT (V) 1.0 0 –0.05 –0.10 –0.15 0 VIN = 100mVP-P AV = 2 VS = ±5V RL = 150Ω TA = 25°C 2.0 Video Amplitude Transient Response VIN = 700mVP-P AV = 2 VS = ±5V RL = 150Ω TA = 25°C OUTPUT (V) 4 3 2 1 0 –1 –2 –3 Large-Signal Transient Response VIN = 2.5VP-P AV = 2 VS = ±5V RL = 150Ω TA = 25°C 1.5 0.5 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6411 G22 –0.5 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6411 G23 –4 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6411 G24 Crosstalk vs Frequency 0 –20 AMPLITUDE (dB) –40 –60 –80 DRIVE 2 LISTEN 1 DRIVE 1 LISTEN 2 VS = ±5V VOUT = 2VP-P RL = 150Ω TA = 25°C 40 35 PERCENT OF UNITS (%) 30 25 20 15 10 5 1000 1635 G25 Gain Error Distribution VS = ±5V VOUT = ±2V RL = 150Ω TA = 25°C 35 30 PERCENT OF UNITS (%) 25 20 15 10 5 Gain Matching Distribution VS = ±5V VOUT = ±2V RL = 150Ω TA = 25°C –100 –120 1 10 100 FREQUENCY (MHz) 0 –3.0 0 3.0 –2.0 –1.0 1.0 2.0 GAIN ERROR–INDIVIDUAL CHANNEL (%) 6411 G26 0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 GAIN MATCHING–BETWEEN CHANNELS (%) 6411 G27 6411f 7 LT6411 PIN FUNCTIONS VEE (Pins 1, 2): Negative Supply Voltage. VEE pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. VEE (Pins 3, 7): Negative Supply Voltage for Output Stage. VEE pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. NC (Pin 4): This pin is not internally connected. OUT2 (Pin 5): Output of Channel 2. The gain between the input and the output of this channel is set by the connection of the channel 2 input pins. See Table 1 in Applications Information for details. VCC (Pins 6, 9): Positive Supply Voltage for Output Stage. VCC pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUT1 (Pin 8): Output of Channel 1. The gain between the input and the output of this channel is set by the connection of the channel 1 input pins. See Table 1 in Applications Information for details. VCC (Pin 10): Positive Supply Voltage. VCC pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. EN (Pin 11): Enable Control Pin. An internal pull-up resistor of 46k will turn the part off if the pin is allowed to float and defines the pin’s impedance. When the pin is pulled low, the part is enabled. DGND (Pin 12): Digital Ground Reference for Enable Pin. This pin is normally connected to ground. IN1+ (Pin 13): Channel 1 Positive Input. This pin has a nominal impedance of 400kΩ and does not have an internal termination resistor. IN1– (Pin 14): This pin connects to the internal resistor network of the channel 1 amplifier, connecting by a 370Ω resistor to the inverting input. IN2– (Pin 15): This pin connects to the internal resistor network of the channel 2 amplifier, connecting by a 370Ω resistor to the inverting input. IN2+ (Pin 16): Channel 2 Positive Input. This pin has a nominal impedance of 400kΩ and does not have an internal termination resistor. Exposed Pad (Pin 17): The pad is internally connected to VEE (Pin 1). If split supplies are used, do not tie the pad to ground. 6411f 8 LT6411 APPLICATIONS INFORMATION Power Supplies The LT6411 can be operated on as little as ±2.25V or a single 4.5V supply and as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation. Note that the Exposed Pad is internally connected to VEE and must not be grounded when using split supplies. Do not leave any supply pins disconnected or the part may not function correctly! Enable/Shutdown The LT6411 has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pull-up resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the DC output impedance will rise to approximately 740Ω through the internal feedback and gain resistors (assuming inputs at ground). Supply current into the amplifier in the disabled state will be primarily through VCC and approximately equal to (VCC – VEN)/46k. It is important that the two following constraints on the DGND pin and the EN pin are always followed: VCC – VDGND ≥ 3V –0.5V ≤ VEN – VDGND ≤ 5.5V Split supplies of ±3V to ±5.5V will satisfy these requirements with DGND connected to 0V. In dual supply cases with VCC less than 3V, DGND should be connected to a potential below ground such as VEE. +V IN+ LT6411 OUT+ AV = +1 IN+ LT6411 +V OUT+ AV = –1 IN+ LT6411 Since the EN pin is referenced to DGND, it may need to be pulled below ground in those cases. In order to protect the internal enable circuitry, the EN pin should not be forced more than 0.5V below DGND. In single supply applications above 5.5V, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to float. For example, on a 12V single supply, a 33k resistor would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to 10mA or less. The enable/disable times of the LT6411 are fast when driven with a logic input. Turn on (from 50% EN input to 50% output) typically occurs in less than 50ns. Turn off is slower, but is less than 300ns. Gain Selection The gain of the internal amplifiers of the LT6411 is configured by connecting the IN+ and IN– pins to the input signal or ground in the combinations shown in Figure 1. As shown in the Simplified Schematic, the IN– pins connect to the internal gain resistor of each amplifier, and therefore, each pin can be configured independently. Floating the IN– pins is not recommended as the parasitic capacitance causes an AC gain of 2 at high frequencies, despite a DC gain of +1. Both inputs are connected together in the gain of +1 configuration to avoid this limitation. +V + – AV = +2 + – + – OUT– IN– IN– OUT– OUT– –V –V –V Figure 1. LT6411 Configured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies 6411f + – 6411 F01 IN– OUT+ + – + – 9 LT6411 APPLICATIONS INFORMATION Input Considerations The LT6411 input voltage range is from VEE + 1V to VCC – 1V. Therefore, on split supplies the LT6411 input range is always as large as or larger than the output swing. On a single positive supply with a gain of +2 and IN– connected to ground, however, the input range limit of +1V limits the linear output low swing to 2V (1V multiplied by the internal gain of 2). The inputs can be driven beyond the point at which the output clips so long as input currents are limited to ±10mA. Continuing to drive the input beyond the output limit can result in increased current drive and slightly increased swing, but will also increase supply current and may result in delays in transient response at larger levels of overdrive. DC Biasing Differential Amplifier Applications The inputs of the LT6411 must be DC biased within the input common mode voltage range, typically VEE + 1V to VCC – 1V. If the inputs are AC coupled or DC biased beyond the input voltage range of a driven A-to-D converter, DC biasing or level shifting will be required. In the basic circuit configurations shown in Figure 1, the DC input common mode voltage and the differential input signal are both multiplied by the amplifier gain. In the gain of +2 configuration, the DC common mode voltage gain can be set to unity by adding a capacitor at the IN– pins as shown in Figure 2. If the inputs are AC coupled or the LT6411 is preceded by a highpass filter, the input common mode voltage can be set by resistor dividers as shown in Figure 3. Adding +V IN+ VDC LT6411 the blocking capacitor to the gain setting resistors sets the input and output DC common mode voltages equal. When using the LT6411 to drive an A-to-D converter, the DC common mode voltage level will affect the harmonic distortion of the combined amplifier/ADC system. Figure 4 shows the measured distortion of an LTC2249 ADC when driven by the LT6411 at different common mode voltage levels with the inputs configured as shown in Figure 3. Adjusting the DC bias voltage can optimize the design for the lowest possible distortion. If the input signals are within the input voltage range and output swing of the LT6411, but outside the input range of an ADC or other circuit the LT6411 is driving, V+ IN+ OV R2 CLARGE R1 VDC LT6411 +V + – OUT+ VDC V+ IN– OV R2 6411 F03 OUT– R1 VDC CLARGE Figure 3. Using Resistor Dividers to Set the Input Common Mode Voltage When AC Coupling –50 –55 –60 DISTORTION (dBc) –65 –70 –75 –80 –85 VCC = 5V, VEE = 0V A V= 2 TA = 25°C HD3 + – CLARGE OUT+ VDC IM3 OUT– IN– VDC HD2 –90 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 VCM (V) VDC 6411 F04 6411 F02 Figure 2. LT6411 Configured with a Differential Gain of 2 and Unity DC Common Mode Gain Figure 4. Harmonic and Intermodulation Distortion of the LT6411 Driving an LTC2249 Versus DC Common Mode Voltage. Harmonic Distortion Measured with a –1dBFS Signal at 30.2MHz. Intermodulation Distortion Measured with Two –7dBFS Tones at 30.2MHz and 29.2MHz 6411f 10 + – VDC + – LT6411 APPLICATIONS INFORMATION the output signals can be AC coupled and DC biased in a manner similar to what is shown at the inputs in Figure 3. A simpler alternative when using an ADC such as the LTC2249 is to use the ADC’s VCM pin to set the optimal common mode voltage as shown in Figure 5. If unity common mode gain and difference mode response to DC is desired, there is another configuration available. Figure 6 shows the LT6411 connected to provide a differential signal gain of +3 with unity common mode gain. For differential signal gain between unity and +3, three resistors can be added to provide attenuation and set the differential input impedance of the stage as illustrated in Figure 7. The general expression for the differential gain is: 2•k A V(DIFF ) = 1+ k+2 Scaling factor ‘k’ is the multiple between the two equalvalue series input resistors and the resistor connected between the two positive inputs. The correct value of R for the external resistors can be computed from the desired differential input impedance, ZIN, as a function of k and the 370Ω internal gain setting resistors, as described in the equation: R= ZIN • 370Ω 370Ω (k + 2) – ZIN (k + 1 ) +V IN+ VCM LT6411 + – OUT+ VCM OUT– IN– VCM Figure 6. LT6411 Configured for a Differential Gain of +3 and Unity Common Mode Gain with Response to DC +V IN+ VCM R = 13.7Ω LT6411 k • R = 27.4Ω OUT– IN– VCM R = 13.7Ω Figure 7. LT6411 Configured with a Differential Input Impedance of 50Ω, a Differential Gain of +2 and Unity Common Mode Gain In Figure 7 k = 2 and R = 13.7Ω, setting the differential gain to +2 and the differential input impedance to approximately 50Ω. +V IN+ OV LT6411 CLARGE + – 10k IN– OV CLARGE LTC2249 VCM 10k 2.2µF 6411 F05 –V Figure 5. Level Shifting the Output Common Mode Voltage of the LT6411 Using the VCM Pin of an LTC2249 + – + – 6411 F06 VCM + – OUT+ VCM VCM 6411 F07 + – 6411f 11 LT6411 APPLICATIONS INFORMATION Layout and Grounding It is imperative that care is taken in PCB layout in order to utilize the very high speed and very low crosstalk of the LT6411. Separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. If input or output traces must be run over a distance of several centimeters, they should use a controlled impedance with matching series and shunt resistances to maintain signal fidelity. Series termination resistors should be placed as close to the output pins as possible to minimize output capacitance. See the Typical Performance Characteristics section for a plot of frequency response with various output capacitors—only 12pF of parasitic output capacitance causes 6dB of peaking in the frequency response! Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 4700pF ceramic capacitor is recommended for both VCC and VEE. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional 1µF to 10µF tantalums should be added on each supply. The smallest value capacitors should be placed closest to the LT6411 package. If the undriven input pins are not connected directly to a low impedance ground plane, they must be carefully bypassed to maintain minimal impedance over frequency. Although crosstalk will be very dependent on the board layout, a recommended starting point for bypass capacitors would be 470pF as close as possible to each input pin with one 4700pF capacitor in parallel. To maintain the LT6411’s channel isolation, it is beneficial to shield parallel input and output traces using a ground plane or power supply traces. Vias between topside and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. ESD Protection The LT6411 has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may flow through these diodes. If the current is kept below 10mA, no damage to the devices will occur. TYPICAL APPLICATIONS Single-Ended to Differential Converter Because the gains of each channel of the LT6411 can be configured independently, the LT6411 can be used to provide a gain of +2 when amplifying differential signals and when converting single-ended signals to differential. With both channels connected to a single-ended input, one channel configured with a gain of +1 and the other configured with a gain of –1, the output will be a differential version of the input with twice the peak-to-peak (differential) amplitude. Figure 8 shows the proper connections and Figure 9 displays the resulting performance when driving an LTC2249. This configuration can preserve signal amplitude when converting single ended video signals to differential signals when driving double terminated cables. The 10k resistors in Figure 8 set the common mode voltage at the output. 5V VCC IN1+ 1µF INPUT 5V 10k VCM 0.1µF IN2+ VEE DGND EN 6411 F08 LT6411 + – 370Ω 370Ω 370Ω 370Ω OUT1 OUT+ IN1– IN2– – + OUT2 OUT– 10k Figure 8. Single-Ended to Differential Converter with Gain of +2 and Common Mode Control 6411f 12 LT6411 TYPICAL APPLICATIONS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 32768 POINT FFT TONE 1 AT 29.5MHz, –7dBFS TONE 2 AT 30.5MHz, –7dBFS IM3 = –90dBc 5V IN+ 13 14 15 IN– 16 + – 6,9,10 50Ω 50Ω 100Ω RECEIVER AMPLITUDE (dBFS) LT6411 AV = 2 5 1,2,3,7 –5V 6411 F10 11,12 Figure 10. Twisted-Pair Driver 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 6411 F09 of 100Ω, the cables can be terminated with a smaller series resistance or a larger shunt resistance in order to compensate for attenuation. A typical circuit for a twistedpair driver is shown in Figure 10. Single Supply Differential ADC Driver The LT6411 is well suited for driving differential analog to digital converters. The low output impedance of the LT6411 is capable of driving a variety of filters as well as interfacing with the typically high impedance inputs of ADCs. In addition, the LT6411’s excellent distortion allows the part to perform with an SFDR below the limits of many high speed ADCs. The DC1057 demo board, shown schematically in Figure 11 and physically in Figure 12, allows implementation and testing of the LT6411 with a variety of different Linear Technology high speed ADCs. Figure 9. 2-Tone Response of the LT6411 Configured with Single-Ended Inputs Driving the LTC2249 at 29.5MHz, 30.5MHz Twisted-Pair Line Driver The LT6411 is ideal when used for driving inexpensive unshielded twisted-pair wires as often found in telephone or communications infrastructure. The input can be composite video, or if three parts are used, RGB or similar and can be either single ended or differential. The LT6411 has excellent performance with all formats. Double termination of the video cable will enhance fidelity and isolate the LT6411 from capacitive loads. Although most twisted-pair cables have a characteristic impedance 6411f 13 LT6411 TYPICAL APPLICATIONS VCC CD1 0.1µF VEE CD2 4700pF JP1 R1 ENABLE 10Ω 1 0603 VCC 2 3 L2 TBD 0603 6 R5 13 14 C9 R38 OPT C8 TBD 0603 R13 C11 R14 C12 R16 0Ω VEE R17 OPT VCC R18 CD6 CD7 4700pF 1µF CD5 470pF CD8 0.1µF 0603 C31 OPT “B” CASE 6411 F11 + C1 OPT “B” CASE E1 VCC E2 GND CD3 470pF VCC J1 AIN+ R4 OPT 0603 R6 T1 TBD ETC1-1TTR 0603 5 1 2 4 J2 AIN– 3 VCC R37 OPT R7 C2 R2 OPT C3 C5 R3 CD4 0.1µF 9 10 11 12 OUT1 8 VCC VCC VCC EN DGND IN1+ IN1– IN2– IN2+ 1 2 3 7 LT6411 VEE OUT2 4 R8 10Ω 1% R9 10Ω 1% L1 TBD R12 0603 10Ω 1% L3 TBD 0603 C4 R35 12.1Ω 1% AIN+ TO ADC INPUTS AIN– R10 15 16 5 R11 10Ω 1% C6 C7 R36 12.1Ω 1% C10 VEE VEE VEE VEE NC Figure 11. DC1057 Demo Circuit Schematic Figure 12. Layout of DC1057 Demo Circuit 6411f 14 + R19 0Ω E7 VEE OPT E8 GND LT6411 SIMPLIFIED SCHEMATIC VCC TO OTHER AMPLIFIER BIAS IN– 370Ω 46k 1k EN IN+ 150Ω VCC 370Ω VEE OUT VCC DGND VEE 6411 SS VEE PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) BOTTOM VIEW—EXPOSED PAD 3.00 ± 0.10 (4 SIDES) 0.70 ± 0.05 PIN 1 TOP MARK (NOTE 6) 1.45 ± 0.10 (4-SIDES) 0.75 ± 0.05 R = 0.115 TYP 15 16 0.40 ± 0.10 1 2 PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 3.50 ± 0.05 1.45 ± 0.05 2.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.200 REF 0.00 – 0.05 (UD16) QFN 0904 0.25 ± 0.05 0.50 BSC 6411f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6411 TYPICAL APPLICATION In cases where lowering the noise floor is paramount, adding higher order lowpass or bandpass filtering can significantly increase signal-to-noise ratio. In Figure 13, the LT6411 is shown driving an LTC2249 with a 2nd order lowpass filter that has been carefully chosen to ensure optimal intermodulation distortion. The response is shown in Figure 14. The filter improves the SNR over the unfiltered case by 6dB to 69.5dB. With the filter, the SNR of the ADC and the LT6411 are comparable; better SNR can be achieved by using either a higher resolution ADC IN+ 1.9VDC IN– 1.9VDC 5V 80.6Ω 55Ω LT6411 55Ω 390nH 15pF 390nH 80.6Ω 10Ω 10Ω AIN– LTC2249 AIN+ 6411 F13 or additional filtering. Figure 15 shows the corresponding SFDR of –75.5dBc with a 30MHz tone. Figure 16 shows the 2-tone response of the LT6411 with 29.5MHz and 30.5MHz inputs. Note that 0dBFS corresponds to a 2VP-P differential signal. 9 6 3 GAIN (dB) 0 –3 –6 –9 –12 1 10 100 FREQUENCY (MHz) 1000 6411 F14 + – – + Figure 13. Optimized 30MHz LT6411 Differential ADC Driver 0 –10 8192 POINT FFT f = 30MHz, –1dBFS –20 IN SNR = 69.5dB –30 SFDR = 75.5dB –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 10 15 20 25 30 5 0 FREQUENCY (MHz) Figure 14. Frequency Response of the LT6411 and Filter 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 32768 POINT FFT TONE 1 AT 29.5MHz, –7dBFS TONE 2 AT 30.5MHz, –7dBFS IM3 = –89.7dBc AMPLITUDE (dBFS) AMPLITUDE (dBFS) 35 40 5 10 6411 F15 15 20 25 30 FREQUENCY (MHz) 35 40 6411 F16 Figure 15. SNR and SFDR of the LT6411 and Filter Driving the LTC2249 Figure 16. 2-Tone Response of the LT6411 and Filter Driving the LTC2249 at 29.5MHz, 30.5MHz RELATED PARTS PART NUMBER LT1993-2 LT1993-4 LT1993-10 LT1994 LT6402-6 LT6553 LT6554 DESCRIPTION 800MHz Low Distortion, Low Noise ADC Driver, AV = 2 900MHz Low Distortion, Low Noise ADC Driver, AV = 4 700MHz Low Distortion, Low Noise ADC Driver, AV = 10 Low Noise, Low Distortion Fully Differential Amplfier 300MHz Low Distortion, Low Noise ADC Driver, AV = 2 650MHz Gain of 2 Triple Video Amplifier 650MHz Gain of 1 Triple Video Amplifier COMMENTS 3.8nV/√Hz Total Noise, Low Distortion to 100MHz 2.4nV/√Hz Total Noise, Low Distortion to 100MHz 1.9nV/√Hz Total Noise, Low Distortion to 100MHz 70MHz Gain Bandwidth Differential In and Out 3.8nV/√Hz Input Referred Noise, Low Distortion to 30MHz Triple Amplifier with Fixed Gain Triple Amplifier with Fixed Gain 6411f LT 0606 • PRINTED IN USA 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006