LT6552

LT6552 3.3V Single Supply Video Difference Amplifier FEATURES s s s s s s s s s s s s DESCRIPTIO Differential or Single-Ended Gain Block Wide Supply Range 3V to 12.6V Output Swings Rail-to-Rail Input Common Mode Range Includes Ground 600V/µs Slew Rate –3dB Bandwidth = 75MHz, AV = ±2 CMRR at 10MHz: >60dB Specified on 3.3V, 5V and ±5V Supplies High Output Drive: ±70mA Power Shutdown to 300µA Operating Temperature Range: –40°C to 85°C Available in 8-Lead SO and Tiny 3mm x 3mm x 0.8mm DFN Packages The LT®6552 is a video difference amplifier optimized for low voltage single supply operation. This versatile amplifier features uncommitted high input impedance (+) and (–) inputs and can be used in differential or single-ended configurations. A second set of inputs gives gain adjustment and DC control to the differential amplifier. On a single 3.3V supply, the input voltage range extends from ground to 1.3V and the output swings from ground to 2.9V while driving a 150Ω load. The LT6552 features 75MHz – 3dB bandwidth, 600V/µs slew rate, and ±70mA output current making it ideal for driving cables directly. The LT6552 maintains its performance for supplies from 3V to 12.6V and is fully specified at 3.3V, 5V and ±5V supplies. The shutdown feature reduces power dissipation to less than 1mW and allows multiple amplifiers to drive the same cable. The LT6552 is available in the 8-lead SO package as well as a tiny, dual fine pitch leadless package (DFN). The device is specified over the commercial and industrial temperature ranges. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s s Differential to Single-Ended Conversion Video Line Driver Automotive Displays RGB Amplifiers Coaxial Cable Drivers Low Voltage High Speed Signal Processing TYPICAL APPLICATIO Cable Sense Amplifier for Loop Through Connections with DC Adjust COMMON MODE REJECTION RATIO (dB) Input Referred CMRR vs Frequency 100 90 80 70 60 50 40 30 20 10 100k 1 10 FREQUENCY (MHz) 100 6552 TA01b VIN 5V CABLE VDC 3 2 7 + – LT6552 4 RF 500Ω RG 500Ω CF 8pF 75Ω VOUT 75Ω VS = 5V, 0V VCM = 0V DC 1 REF 8 FB 6 6552 TA01a U 6552f U U 1 LT6552 ABSOLUTE AXI U RATI GS (Note 1) Specified Temperature Range (Note 5) ....–40°C to 85°C Maximum Junction Temperature .......................... 150°C (DD Package) ................................................... 125°C Storage Temperature Range ..................–65°C to 150°C (DD Package) ....................................–65°C to 125°C Lead Temperature (Soldering, 10 sec) ........................................... 300°C Supply Voltage (V + to V –) .................................... 12.6V Input Current (Note 2) ........................................ ±10mA Input Voltage Range ......................................... V – to V + Differential Input Voltage +Input (Pin 3) to –Input (Pin 2) ................................ ±VS Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ...–40°C to 85°C PACKAGE/ORDER I FOR ATIO TOP VIEW REF –IN +IN V– 1 2 3 4 8 7 6 5 FB V+ OUT SHDN ORDER PART NUMBER LT6552CDD LT6552IDD DD PART MARKING* LADR REF 1 –IN 2 +IN 3 V– 4 DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 160°C/W UNDERSIDE METAL CONNECTED TO V– (PCB CONNECTION OPTIONAL) *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. 3.3V ELECTRICAL CHARACTERISTICS SYMBOL VOS ∆VOS/∆T IB IOS PARAMETER Input Offset Voltage Input VOS Drift Input Bias Current Input Offset Current Any Input The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3.3V, 0V. Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) CONDITIONS Both Inputs (Note 7) q q q q Either Input Pair 2 U U W WW U W TOP VIEW 8 7 6 5 FB V+ OUT SHDN ORDER PART NUMBER LT6552CS8 LT6552IS8 S8 PART MARKING 6552 6552I S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 100°C/W MIN TYP 5 40 20 1 MAX 20 25 50 5 UNITS mV mV µV/°C µA µA 6552f LT6552 3.3V ELECTRICAL CHARACTERISTICS SYMBOL en in RIN CMRR PSRR GE VOH PARAMETER Input Noise Voltage Density Input Noise Current Density Input Resistance Common Mode Rejection Ratio Input Range Power Supply Rejection Minimum Supply (Note 8) Gain Error Swing High CONDITIONS f = 10kHz f = 10kHz The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3.3V, 0V. Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) MIN TYP 55 0.7 300 q q MAX UNITS nV/√Hz pA/√Hz kΩ dB Common Mode, VCM = 0V to 1.3V VCM = 0V to 1.3V VS = 3V to 12V VO = 0.5V to 2V, RL = 1k RL = 150Ω (VDIFF = 0.4V), VREF (Pin 1) = 0V, AV = 10 RL = 1k RL = 150Ω RL = 75Ω (VDIFF = –0.1V), VREF(Pin 1) = 0V, AV = 10 RL = 1k ISINK = 5mA ISINK = 10mA VOUT = 0.5V to 2.5V Measure from 1V to 2V, RL = 150Ω, AV = 2 VO = 2VP-P AV = 2, RL = 150Ω AV =50, VO = 0.5V to 2.5V, 20% to 80%, RL = 150Ω AV = 2, ∆VOUT = 2V, Positive Step RL = 150Ω AV = 2, RL = 150Ω, Output Black Level = 0.6V AV = 2, RL = 150Ω, Output Black Level = 0.6V VOUT = 0V, VDIFF = 1V q 58 0 48 3 83 1.3 54 1 1 3 3 V dB V % % V V V q q q q q q 3.1 2.5 2 3.2 2.9 2.5 8 65 40 350 55 65 125 20 30 0.4 0.15 175 50 120 200 VOL Swing Low q q q mV mV mV V/µs MHz MHz ns ns ns % Deg mA mA SR FPBW BW tr, tf tS Slew Rate Full-Power Bandwidth (Note 9) Small-Signal –3dB Bandwidth Rise Time, Fall Time (Note 10) Settling Time to 3% Settling Time to 1% Differential Gain Differential Phase ISC IS Short-Circuit Current Supply Current 35 25 50 12.5 13.5 15 750 0.5 q mA mA µA V V µA µA ns ns µA Supply Current, Shutdown VL VH Shutdown Pin Input Low Voltage Shutdown Pin Input High Voltage Shutdown Pin Current tON tOFF Turn On-Time Turn Off-Time Shutdown Output Leakage Current VSHDN = 0.5V q q q 300 3 40 3 250 450 VSHDN = 0.5V VSHDN = 3V VSHDN from 0.5V to 3V VSHDN from 3V to 0.5V VSHDN = 0.5V, 0V ≤ VOUT ≤ V+ q q 150 10 q 0.25 6552f 3 LT6552 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V; Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL VOS ∆VOS/∆T IB IOS en in RIN CMRR PSRR GE VOH PARAMETER Input Offset Voltage Input VOS Drift Input Bias Current Input Offset Current Input Noise Voltage Density Input Noise Current Density Input Resistance Common Mode Rejection Ratio Input Range Power Supply Rejection Minimum Supply (Note 8) Gain Error Swing High VO = 0.5V to 3.5V, RL = 1k RL = 150Ω (VDIFF = 0.6V), VREF(Pin 1) = 0V, AV = 10 RL = 1k RL = 150Ω RL = 75Ω, 0°C ≤ TA ≤ 70°C (Only) (VDIFF = – 0.1V), VREF (Pin 1) = 0V, AV = 10 RL = 1k ISINK = 5mA ISINK = 10mA VOUT = 0.5V to 3.5V Measure from 1V to 3V, RL = 150Ω, AV = 2 VO = 2VP-P AV = 2, RL = 150Ω 5V, 0V; AV = 50, VO = 0.5V to 3.5V, 20% to 80%, RL = 1k AV = 2, ∆VOUT = 2V, Positive Step RL = 150Ω AV = 2, RL = 150Ω, Output Black Level = 1V AV = 2, RL = 150Ω, Output Black Level = 1V VOUT = 0V, VDIFF = 1V 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C q q q 5V ELECTRICAL CHARACTERISTICS CONDITIONS Both Inputs (Note 7) q q MIN TYP 5 40 20 1 55 0.7 300 MAX 20 25 50 5 UNITS mV mV µV/°C uA uA nV/√Hz pA/√Hz kΩ dB Any Input Either Input Pair f = 10kHz f = 10kHz Common Mode, VCM = 0V to 3V VCM = 0V to 3V VS = 3V to 12V q q q q q q q q q q q q q q 58 0 48 3 83 3 54 1 1 3 3 V dB V % % V V V 4.8 3.6 2.75 4.875 4.3 3.4 8 65 110 450 70 70 125 20 30 0.25 0.04 175 50 120 200 VOL Swing Low mV mV mV V/µs MHz MHz ns ns ns % Deg mA mA mA SR FPBW BW tr, tf tS Slew Rate Full-Power Bandwidth (Note 9) Small-Signal –3dB Bandwidth Rise Time, Fall Time Settling Time to 3% Settling Time to 1% Differential Gain Differential Phase ISC Short-Circuit Current 50 45 35 70 IS Supply Current Supply Current Shutdown VSHDN = 0.5V q q q 13.5 400 4.7 60 4 14.5 16 900 0.5 200 10 mA mA µA V V µA µA VL VH Shutdown Pin Input Low Voltage Shutdown Pin Input High Voltage Shutdown Pin Current VSHDN = 0.5V VSHDN = 4.7V q q 6552f 4 LT6552 5V ELECTRICAL CHARACTERISTICS SYMBOL tON tOFF PARAMETER Turn-On Time Turn-Off Time Shutdown Output Leakage Current The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V. Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) CONDITIONS VSHDN from 0.5V to 4.7V VSHDN from 4.7V to 0.5V VSHDN = 0.5V, 0V ≤ VOUT ≤ V+ q MIN TYP 250 450 0.25 MAX UNITS ns ns µA ± 5V ELECTRICAL CHARACTERISTICS SYMBOL VOS ∆VOS/∆T IB IOS en in RIN CMRR PSRR GE PARAMETER Input Offset Voltage Input VOS Drift Input Bias Current Input Offset Current Input Noise Voltage Density Input Noise Current Density Input Resistance Common Mode Rejection Ratio Input Range Power Supply Rejection Gain Error Output Voltage Swing Any Input Either Input Pair f = 10kHz f = 10kHz CONDITIONS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ± 5V. Figure 2 shows the DC test circuit, VREF = VCM = 0V, VDIFF = 0V, VSHDN = V +, unless otherwise noted. RL = RF + RG = 1k. (Note 6) MIN q q q q TYP 10 50 25 1 55 0.7 300 MAX 25 30 50 5 UNITS mV mV µV/°C µA µA nV/√Hz pA/√Hz kΩ dB Both Inputs (Note 7) Common Mode, VCM = –5V to 3V VCM = – 5V to 3V VS = ±2V to ±6V, VCM = 0V VO = –3V to 3V, RL = 1k RL = 150Ω (VDIFF = ± 0.6V), VREF (Pin 1) = 0V, AV = 10 RL = 1k RL = 150Ω RL = 75Ω, 0°C ≤ TA ≤ 70°C (Only) VCM = 0V, VDIFF = –1.5V to +1.5V, VO = – 5V to 5V Measure from –2V to 2V, RL = 150Ω VO = 6VP-P (Note 9) AV = 2, RL = 150Ω AV = 50, VO = –3V to 3V, 20% to 80% AV = 2, ∆VOUT = 6V, Positive Step RL = 150Ω AV = 2, RL = 150Ω, Output Black Level = 0V AV = 2, RL = 150Ω, Output Black Level = 0V VOUT = 0V, VDIFF = ±1V 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C VSHDN = – 4.5V q q q q q q q q q q q q 58 –5 48 75 3 54 1 1 3 3 V dB % % V V V V/µs MHz MHz ±4.8 ±3.6 ±2.75 400 ±4.875 ±4.3 ±3.4 600 30 75 125 25 35 0.2 0.15 175 SR FPBW BW tr, tf tS Slew Rate Full-Power Bandwidth Small-Signal –3dB Bandwidth Rise Time, Fall Time Settling Time to 3% Settling Time to 1% Differential Gain Differential Phase ns ns ns % Deg mA mA mA ISC Short-Circuit Current 50 45 35 70 Supply Current Shutdown IS VL VH Supply Current Shutdown Pin Input Low Voltage Shutdown Pin Input High Voltage 650 14 1400 16.5 18.5 –4.5 µA mA mA V V 6552f q q 4.7 5 LT6552 ± 5V ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Shutdown Pin Current tON tOFF Turn-On Time Turn-Off Time Shutdown Output Leakage Current The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ± 5V. Figure 2 shows the DC test circuit, VREF = VCM = 0V, VDIFF = 0V, VSHDN = V +, unless otherwise noted. RL = RF + RG = 1k. (Note 6) CONDITIONS VSHDN = – 4.5V VSHDN = 4.7V VSHDN from – 4.5V to 4.7V VSHDN from 4.7V to –4.5V VSHDN = – 4.5V, V – ≤ VOUT ≤ V+ q q q MIN TYP 85 3 200 400 0.25 MAX 250 10 UNITS µA µA ns ns µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected from ESD with diodes to the supplies. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: The LT6552C/LT6552I are guaranteed functional over the temperature range of –40°C to 85°C. Note 5: The LT6552C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet specified performance from –40°C to 85°C, but is not tested or QA sampled at these temperatures. The LT6552I is guaranteed to meet specified performance from – 40°C to 85°C. RG 100Ω 0.1% Note 6: When RL = 1k is specified, the load resistor is RF + RG, but when RL = 150Ω or RL = 75Ω is specified, then an additional resistor of that value is added to the output. Note 7: VOS measured at the output (Pin 6) is the contribution from both input pairs and is input referred. Note 8: Minimum supply is guaranteed by the PSRR test. Note 9: Full power bandwidth is calculated from the slew rate. FPBW = SR/2πVp Note 10: VS = 3.3V, tr and tf limits are guaranteed by correlation to VS = 5V and ±5V tests. RG 100Ω 0.1% REF FB V+ OUT SHDN VSHDN – + VREF +IN V– + – + – VCM + – + – V+ RL 6552 F01 + – Figure 1. 3.3V, 5V DC Test Circuit 6 + – + – VDIFF –IN 1µF REF RF 900Ω 0.1% VDIFF VCM V– –IN +IN V– 1µF FB V+ OUT SHDN VSHDN 1µF RF 900Ω 0.1% + – + – V+ RL 6552 F02 Figure 2. ±5V DC Test Circuit 6552f LT6552 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 20 18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0 0 2 6 8 10 4 TOTAL SUPPLY VOLTAGE (V) 12 6552 G01 TA = 125°C INPUT BIAS CURRENT (µA) TA = –55°C TA = 25°C –14 –16 –18 –20 –22 –24 –50 –25 INPUT BIAS CURRENT (µA) Output Saturation Voltage vs Load Current (Output High) 1 OUTPUT HIGH SATURATION VOLTAGE (V) OUTPUT LOW SATURATION VOLTAGE (V) VS = 5V, 0V 1 SUPPLY CURRENT (mA) TA = 125°C 100m TA = 25°C TA = –55°C 10m 0.01 0.1 1 10 SOURCING LOAD CURRENT (mA) Shutdown Pin Current vs Shutdown Pin Voltage 0 SHUTDOWN PIN CURRENT (µA) –10 –20 –30 TA = 25°C –40 TA = –55°C –50 –60 TA = 125°C OUTPUT SHORT-CIRCUIIT CURRENT (mA) VS = 5V, 0V VCM = 1V 75 70 65 60 55 OUTPUT SHORT-CIRCUIIT CURRENT (mA) 0 1 2 3 4 SHUTDOWN PIN VOLTAGE (V) UW 6552 G04 Input Bias Current vs Temperature –10 –12 VS = 5V, 0V VCM = 1V –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 50 25 75 0 TEMPERATURE (°C) 100 125 –24 Input Bias Current vs Common Mode Voltage VS = 5V, 0V TA = 125°C TA = 25°C TA = –55°C 0 1 3 4 2 COMMON MODE VOLTAGE (V) 5 6552 G03 6552 G02 Output Saturation Voltage vs Load Current (Output Low) VS = 5V, 0V 16 14 12 10 8 6 4 2 1m 0.01 0.1 1 10 SINKING LOAD CURRENT (mA) 100 6552 G05 Supply Current vs Shutdown Pin Voltage VS = 5V, 0V VCM = 1V TA = 125°C TA = 25°C TA = –55°C 100m 10m TA = 125°C TA = –55°C TA = 25°C 100 0 2.5 3.0 3.5 4.5 4.0 SHUTDOWN PIN VOLTAGE (V) 5.0 6552 G06 Output Short-Circuit Current vs Temperature 80 VS = 5V, 0V Output Short-Circuit Current vs Temperature VS = ±5V SOURCING CURRENT 75 SINKING CURRENT 70 VS = 3.3V, 0V 50 45 40 –50 –25 65 5 6552 G07 50 25 75 0 TEMPERATURE (°C) 100 125 60 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 6552 G08 6552 G09 6552f 7 LT6552 TYPICAL PERFOR A CE CHARACTERISTICS Open-Loop Gain 500 INPUT NOISE VOLTAGE DENSITY (nV/√Hz) 400 300 200 100 0 –100 –200 –300 –400 –500 –5 –4 –3 –2 –1 0 1 2 3 OUTPUT VOLTAGE (V) 4 5 RL = 150Ω RL = 1k INPUT NOISE CURRENT DENSITY (pA/√Hz) CHANGE IN INPUT OFFSET VOLTAGE (µV) Closed-Loop Voltage Gain vs Frequency 10 6.2 CLOSED-LOOP VOLTAGE GAIN (dB) CLOSED-LOOP VOLTAGE GAIN (dB) 9 8 7 6 5 4 3 2 1 AV = 2 VOUT = 1.5V DC VS = 3.3V, 0V OPEN-LOOP GAIN 3.3V VIN VDC 3 2 7 + – LT6552 4 RF 500Ω 1 REF 8 FB 6 VOUT RL 150Ω RG 500Ω CF 8pF 0 100k 0.1M 1M 10M FREQUENCY (Hz) Gain Bandwidth Product and Phase Margin vs Temperature GAIN BANDWIDTH PRODUCT (MHz) 140 130 GAIN BANDWIDTH PRODUCT (MHz) GAIN BANDWIDTH PRODUCT 120 100 80 VS = 3.3V, OV VCM = 1V VS = ±5V –3dB BANDWIDTH (MHz) PHASE MARGIN VS = ±5V VS = 3.3V, OV VCM = 1V –50 –25 50 25 75 0 TEMPERATURE (°C) 100 8 UW VS = ±5V 6552 G10 Input Noise Voltage Density vs Frequency 225 VS = 5V, 0V 200 VCM = 1V 175 150 125 100 75 50 25 100 1k 10k FREQUENCY (Hz) 100k 6552 G11 Input Noise Current Density vs Frequency 5 VS = 5V, 0V VCM = 1V 4 3 2 1 0 100 1k 10k FREQUENCY (Hz) 100k 6552 G12 Gain Flatness vs Frequency AV = 2 VOUT = 1.5V DC VS = 3.3V, 0V 70 60 50 40 30 20 10 0 Open-Loop Gain and Phase vs Frequency 140 CL = 5pF 120 RL = 1k TA = 25°C 100 VS = 3.3V, OV 80 VCM = 1V 60 40 VS = 3.3V, OV VCM = 1V VS = ±5V GAIN 20 0 –20 –40 –60 500M 6552 G15 6.1 PHASE VS = ±5V PHASE (DEG) 6.0 VIN 3 2 3.3V 7 + – LT6552 4 RF 500Ω 5.9 VDC 1 REF 8 FB 6 VOUT RL 150Ω 5.8 RG 500Ω CF 8pF –10 –20 100M 6552 G14 100M 6552 G13 5.7 10k 100k 1M 10M FREQUENCY (Hz) –30 100k 1M 10M FREQUENCY (Hz) 100M Gain Bandwidth Product and Phase Margin vs Supply Voltage CL = 5pF RL = 1k TA = 25°C VCM =1V GAIN BANDWIDTH PRODUCT 85 80 –3dB Bandwidth vs Temperature AV = 2 RL = 150Ω VS = ±5V 75 70 65 60 55 –50 –25 VS = 3.3V, OV VOUT = 1.5V CL = 5pF RL = 1k 120 110 PHASE MARGIN (DEG) 40 PHASE MARGIN PHASE MARGIN (DEG) 40 30 20 125 30 0 2 8 6 4 10 12 TOTAL SUPPLY VOLTAGE (V) 20 14 50 25 75 0 TEMPERATURE (°C) 100 125 6552 G16 6552 G17 6552 G18 6552f LT6552 TYPICAL PERFOR A CE CHARACTERISTICS RL = 150Ω TA = 25°C VOUT = –3V TO 3V VS = ±5V Output Impedance vs Frequency 100 VS = ±5V 550 500 OUTPUT IMPEDANCE (Ω) 10 SLEW RATE (V/µs) AV = 10 AV = 2 1 450 400 350 300 250 0.01 100k SLEW RATE (V/µs) 0.1 1M 10M FREQUENCY (Hz) 6552 G19 Common Mode Rejection Ratio vs Frequency 90 COMMON MODE REJECTION RATIO (dB) 80 70 60 VS = 3.3V, 0V 50 40 30 20 10 100k 1M 10M FREQUENCY (Hz) 100M 6552 G22 POWER SUPPLY REJECTION RATIO (dB) VCM = 0V DC 40 30 OVERSHOOT (%) VS = ±5V 2nd and 3rd Harmonic Distortion vs Frequency –30 VS = 3.3V, 0V AV = 2 VO = 0.5V TO 2.5V DISTORTION (dB) RL = 150Ω, 3RD –50 RL = 150Ω, 2ND –30 –40 –50 –60 –70 –80 –70 RL = 1k, 3RD –80 10k 100k 1M FREQUENCY (Hz) 10M 6552 G25 –40 DISTORTION (dB) –60 UW Slew Rate vs Temperature AV = 2 RL = 150Ω FALLING VS = 5V, 0V VOUT = 0.5V T0 3.5V RISING 900 800 700 Slew Rate vs Closed-Loop Gain RL = 150Ω TA = 25°C VOUT = –3V TO 3V VS = ±5V FALLING 600 500 400 300 200 100 0 RISING FALLING VS = 3.3V, 0V VOUT = 0.5V T0 2.5V RISING 100M 200 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 2 4 6 GAIN (AV) 8 10 6552 G21 6552 G20 Power Supply Rejection Ratio vs Frequency 60 50 NEGATIVE SUPPLY VS = ±5V TA = 25°C 55 Series Output Resistor vs Capacitive Load VS = 5V, 0V 50 A = 2 V 45 RF = RG = 500Ω CFB = 8pF 40 35 30 25 20 15 10 5 0 RS = 20Ω, RL = ∞ RS = 10Ω, RL = ∞ POSITIVE SUPPLY 20 10 0 10k RS = RL = 50Ω 10 100 CAPACITIVE LOAD (pF) 1000 6552 G24 100k 1M 10M FREQUENCY (Hz) 100M 6552 G23 2nd and 3rd Harmonic Distortion vs Frequency VS = ±5V AV = 2 VO = 2VP-P RL = 150Ω, 2ND RL = 150Ω, 3RD RL = 1k, 2ND RL = 1k, 3RD RL = 1k, 2ND –90 –100 10k 100k 1M FREQUENCY (Hz) 10M 6552 G26 6552f 9 LT6552 TYPICAL PERFOR A CE CHARACTERISTICS Large Signal Response, VS = 5V, 0V Large Signal Response, VS = ±5V Small Signal Response, VS = 5V, 0V 500mV/DIV 0V 50mV/DIV 6552 G28 1V/DIV 0V AV = 2 CF = 5pF CL = 10pF RF = RG = 500Ω RL = 150Ω 50ns/DIV Small Signal Response, VS = 5V, 0V VSHDN 2V/DIV 50mV/DIV 2.5V VOUT 1V/DIV 0V AV = 2 CF = 5pF CL = 10pF RF = RG = 500Ω RL = 150Ω 50ns/DIV 6552 G30 10 UW 6552 G27 2.5V AV = 2 CF = 5pF CL = 10pF RF = RG = 500Ω RL = 150Ω 50ns/DIV AV = 1 CL = 10pF RL = 150Ω 50ns/DIV 6552 G29 Shutdown Response Output Overdrive Recovery VIN 1V/DIV 0V VOUT 2V/DIV 0V AV = 2 RL = 150Ω VIN = 1.25V VS = 5V, 0V 200ns/DIV 6552 G31 0V AV = 2 VS = 5V, 0V 100ns/DIV 6552 G32 6552f LT6552 APPLICATIO S I FOR ATIO The LT6552 is a video difference amplifier with two pairs of high impedance inputs. The primary purpose of the LT6552 is to convert high frequency differential signals into a single-ended output, while rejecting any common mode noise. In the simplest configuration, one pair of inputs is connected to the incoming differential signal, while the other pair of inputs is used to set amplifier gain and DC level. The device will operate on either single or dual supplies and has an input common mode range which includes the negative supply. The common mode rejection ratio is greater than 60dB at 10MHz. Feedback is SHDN 3 2 5 V+ 7 + – LT6552 4 RF VINDIFF VDC SHDN VIN 3 2 5 V+ 7 3 2 1 REF 8 FB + – LT6552 4 V– RF 6 VO RG VO = + ( R R+ R ( V F G G IN U applied to Pin 8 and the LT6552’s transient response is optimized for gains of 2 or greater. Figure 3 shows the single supply connection. The amplifier gain is set by a feedback network from the output to Pin 8 (FB). A DC signal applied to Pin 1 (REF) establishes the output quiescent voltage and the differential signal is applied to Pins 2 and 3. Figure 4 shows several other connections using dual supplies. In each case, the amplifier gain is set by a feedback network from the output to Pin 8 (FB). 1 REF 8 FB 6 VO RG R + RG VO = (VINDIFF + VDC) F RG 6552 F01 W U U Figure 3 SHDN 5 SHDN V+ 7 VINDIFF VO VIN RG 3 2 5 V+ 7 + – LT6552 4 V– RF VIN 1 REF 8 FB + – LT6552 4 V– RF 6 1 REF 8 FB 6 VO RG VO = – ( R R+ R ( V F G G IN VO = ( R R+ R ( V F G G INDIFF – R ( R (V F G IN 6552 F01 Figure 4 6552f 11 LT6552 APPLICATIO S I FOR ATIO Amplifier Characteristics Figure 5 shows a simplified schematic of the LT6552. There are two input stages; the first one consists of transistors Q1 to Q8 for the (+) and (–) inputs while the second input stage consists of transistors Q9 to Q16 for the reference and feedback inputs. This topology provides high slew rates at low supply voltages. The input common mode range extends from ground to typically 1.75V from VCC, and is limited by 2VBE’s plus a saturation voltage of current sources I1-I4. Each input stage drives the degeneration resistors of PNP and NPN current mirrors, Q17 to Q20, that convert the differential signals into a singleended output. The complementary drive generator supplies current to the output transistors that swing from railto-rail. I1 I2 I3 Q2 Q3 Q5 R1 Q7 Q10 Q1 Q4 Q6 Q8 Q9 V+ RIN1 DESD1 DESD2 3 +IN V– DESD3 DESD4 V+ RIN2 RIN3 V+ DESD5 DESD6 DESD7 DESD8 V– 2 –IN 1 REF V– Figure 5. Simplified Schematic 12 U The current generated through R1 or R2, divided by the capacitor CM, determines the slew rate. Note that this current, and hence the slew rate, are proportional to the magnitude of the input step. The input step equals the output step divided by the closed-loop gain. The highest slew rates are therefore obtained in the lowest gain configurations. The Typical Performance Characteristic Curve of Slew Rate vs Closed-Loop Gain shows the details. ESD The LT6552 has reverse-biased ESD protection diodes on all inputs and outputs, as shown in Figure 5. If these pins are forced beyond either supply, unlimited current will flow through these diodes. If the current is transient in nature and limited to 100mA or less, no damage to the device will occur. 7 V+ I4 I5 R3 R4 Q21 Q17 Q11 Q13 R2 Q15 Q18 CM V+ DESD9 Q12 Q14 Q16 COMPLEMENTARY DRIVE GENERATOR Q19 Q20 Q22 I6 V+ RIN4 BIAS V– 8 FB R5 R6 V+ V+ DESD11 5 SHDN DESD12 V– 6552 FO5 W UU 6 OUT DESD10 V– 4 V– 6552f LT6552 APPLICATIO S I FOR ATIO Layout and Passive Components With a bandwidth of 75MHz and a slew rate of 600V/µs, the LT6552 requires special attention to board layout and supply bypassing. Use a ground plane, short lead lengths and RF quality low ESR supply bypass capacitors. The positive supply pin should be bypassed with a small capacitor (typically 0.1µF) within 1 inch of the pin. When driving loads greater than 10mA, an additional 4.7µF electrolytic capacitor should be used. When using split supplies, the same is true for the negative supply pin. The parallel combination of the feedback resistor and gain setting resistor on Pin 8 (FB) can combine with the input capacitance to form a pole which can degrade stability. In general, use feedback resistors of 1k or less. 10 AV = 2 9 RF = RG = 500Ω RL = 150Ω 8 T = 25°C A 7 VOUT = 1.5V DC VS = 3.3V, 0V 6 5 4 3 2 1 0 0.1 CLOSED-LOOP VOLTAGE GAIN (dB) Figure 6. Closed-Loop Gain vs Frequency 50mV/DIV 50mV/DIV 1.5V AV = 2 RF = RG = 500Ω RL = 150Ω 50ns/DIV 6552 F07a Figure 7A. Small Signal Transient Response, VS = 3.3V, 0V U Operating with Low Closed-Loop Gains The LT6552 has been optimized for closed-loop gains of 2 or greater. For a closed-loop gain of 2 the response peaks about 3dB. Peaking can be reduced by using low value feedback resistors, and can be eliminated by placing a capacitor across the feedback resistor (feedback zero). Figure 6 shows the closed-loop gain of 2 frequency response with various values of the feedback capacitor. This peaking shows up as a time domain overshoot of 40%; with an 8pF feedback capacitor the overshoot is eliminated. Figures 7A and 7B show the Small Signal Response of the LT6552 with and without an 8pF feedback capacitor. CF = 0pF CF = 3pF CF = 5pF CF = 8pF CF = 10pF 1 10 FREQUENCY (MHz) 100 6552 F06 W UU 1.5V AV = 2 CF = 8pF RF = RG = 500Ω RL = 150Ω 50ns/DIV 6552 F07b Figure 7B. Small Signal Transient Response, VS = 3.3V, 0V with 8pF Feedback Capacitor 6552f 13 LT6552 APPLICATIO S I FOR ATIO SHDN Pin The LT6552 includes a shutdown feature that disables the part, reducing quiescent current and making the output high impedance. The part can be shutdown by bringing the SHDN pin within 0.5V of V–. When shutdown the supply current is typically 400µA and the output leakage current PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 3.5 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 0.38 ± 0.10 8 PIN 1 TOP MARK (NOTE 6) (DD8) DFN 1203 0.200 REF NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 14 U is 0.25µA (V– ≤ VOUT ≤ V+). In normal operation the SHDN can be tied to V+ or left floating; if the pin is left unconnected, an internal FET pull-up will keep the LT6552 fully operational. 0.675 ± 0.05 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) 0.75 ± 0.05 4 0.25 ± 0.05 2.38 ± 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD 1 0.50 BSC 0.00 – 0.05 6552f U W UU LT6552 PACKAGE DESCRIPTIO U S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 8 7 6 5 .045 ±.005 .050 BSC .160 ±.005 .228 – .244 (5.791 – 6.197) .150 – .157 (3.810 – 3.988) NOTE 3 1 2 3 4 .053 – .069 (1.346 – 1.752) 0°– 8° TYP .004 – .010 (0.101 – 0.254) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0303 .245 MIN .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 6552f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6552 TYPICAL APPLICATIO U YPBPR to RGB Video Converter +3V +3V 499Ω 499Ω 8.2pF 8 8 1 2 3 FB REF 7 LT6552 5 4 SD –3V –3V +3V Y 499Ω 909Ω 2.2pF 8 PR 21.5Ω 53.6Ω 21.5Ω 11.3Ω 1 2 3 FB REF 7 LT6552 5 4 SD 6 75Ω R 75Ω 6 1 2 3 FB REF 7 LT6552 5 4 SD 6 75Ω G 75Ω 499Ω 499Ω 5.6pF – + – + – + –3V 42.2Ω +3V 499Ω 1.3k 1pF 8 FB REF 7 LT6552 5 4 SD BW (± 0.5dB) > 25MHz BW (–3dB) > 36MHz IS ≈ 70mA 6 75Ω B 75Ω PB 49.9Ω 25.5Ω 1 2 3 – + –3V R = Y + 1.4 • PR G = Y – 0.34 • PB – 0.71 • PR B = Y + 1.8 • PB 6552 TA02 RELATED PARTS PART NUMBER LT1193 LT1675 LT6205/LT6206/LT6207 LT6550/LT6551 DESCRIPTION AV = 2 Video Difference Amp RGB Multiplexer with Current Feedback Amplifiers Single/Dual/Quad Single Supply 3V, 100MHz Video Op Amps 3.3V Triple and Quad Video Amplifiers COMMENTS 80MHz BW, 500V/µs Slew Rate, Shutdown –3dB Bandwidth = 250MHz, 100MHz Pixel Switching 450V/µs Slew Rate, Rail-to-Rail Output, Input Common Modes to Ground Internal Gain of 2, 110MHz –3dB Bandwidth, Input Common Modes to Ground 6552f 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q LT/TP 0304 1K • PRINTED IN USA FAX: (408) 434-0507 q www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003