LT6555IUF

LT6555 650MHz Gain of 2 Triple 2:1Video Multiplexer FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 650MHz –3dB Small Signal Bandwidth 450MHz –3dB 2VP-P Large-Signal Bandwidth 120MHz ±0.1dB Bandwidth High Slew Rate: 2200V/µs Fixed Gain of 2; No External Resistors Required 72dB Channel Separation at 10MHz 50dB Channel Separation at 100MHz –80dBc 2nd Harmonic Distortion at 10MHz, 2VP-P –70dBc 3rd Harmonic Distortion at 10MHz, 2VP-P Low Supply Current: 9mA per Amplifier 6.5ns 0.1% Settling Time for 2V Step ISS ≤ 500µA per Amplifier when Disabled Differential Gain of 0.033%, Differential Phase of 0.022° Wide Supply Range: ±2.25V (4.5V) to ±6V (12V) Available in 24-Lead SSOP and 24-Lead QFN Packages The LT®6555 is a high speed triple 2:1 video multiplexer with an internally fixed gain of 2. The individual amplifiers are optimized for performance with a double terminated 75Ω video load and feature a –3dB 2VP-P bandwidth of 450MHz, making them ideal for driving very high resolution video signals. Separate power supply pins for each amplifier boost channel separation to 72dB, allowing the LT6555 to excel in many high speed applications. While the performance of the LT6555 is optimized for dual supply operation, it can also be operated with a single supply as low as 4.5V. Using dual 5V supplies, each amplifier draws only 9mA. When disabled, the amplifiers draw less than 500µA and the outputs become high impedance. The LT6555 is manufactured on Linear Technology’s proprietary low voltage complementary bipolar process and is available in 24-lead SSOP and ultra-compact 24-lead QFN packages. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ RGB Amplifiers UXGA Video Multiplexing LCD Projectors TYPICAL APPLICATIO RINA GINA BINA LT6555 75Ω ×2 75Ω RGB Multiplexer and Line Driver V+ 75Ω 75Ω ROUT Video Amplitude Transient Response 1.8 1.6 1.4 1.2 75Ω AGND ×2 RINB GINB BINB 75Ω 75Ω 75Ω 75Ω SELECT A/B 75Ω ENABLE DGND V– 6555 TA01a GOUT OUTPUT (V) 75Ω 1.0 0.8 0.6 0.4 0.2 0 VIN = 0V TO 700mV VS = ± 5V RL = 150Ω TA = 25°C 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6555 G21 75Ω ×2 BOUT –0.2 –0.4 U 6555f U U 1 LT6555 ABSOLUTE AXI U RATI GS Total Supply Voltage (V+ to V–) ............................ 12.6V Input Current (Note 2) ........................................ ±10mA Output Current (Continuous) ............................. ±70mA EN to DGND Voltage (Note 2) ................................. 5.5V SEL to DGND Voltage (Note 2) .................................. 8V Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C PACKAGE/ORDER I FOR ATIO TOP VIEW IN1A DGND IN2A VREF IN3A AGND1 IN1B AGND2 IN2B 1 2 3 4 5 6 7 8 9 G = +2 G = +2 G = +2 23 EN 22 SEL A/B 21 V+ 20 OUT1 19 V– 18 OUT2 17 V+ LT6555CGN LT6555IGN EN V+ 24 V+ SEL A/B DGND IN2A IN1A ORDER PART NUMBER VREF 1 IN3A 2 AGND1 3 V– 4 IN1B 5 AGND2 6 16 OUT3 15 V– 14 V+ 13 V+ V+ IN2B AGND3 IN3B V– V AGND3 10 IN3B 11 V– 12 GN PACKAGE 24-LEAD PLASTIC SSOP + TJMAX = 150°C, θJA = 90°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND, VVREF = 0V. SYMBOL VOS IIN RIN CIN PSRR IPSRR AV ERR AV MATCH VOUT PARAMETER Input Referred Offset Voltage Input Current Input Resistance Input Capacitance Power Supply Rejection Ratio Input Current Power Supply Rejection Gain Error Gain Matching Output Voltage Swing VIN = ±1V f = 100kHz VS = ±2.25V to ±6V (Note 6) VS = ±2.25V to ±6V (Note 6) VOUT = ±2V, Nominal Gain 2V/V Any One Channel to Another (Note 7) ● ● ● ● ELECTRICAL CHARACTERISTICS CONDITIONS VIN = 0V, VOS = VOUT/2 ● ● ● 2 U U W WW U W (Note 1) Junction Temperature SSOP ................................................................ 150°C QFN .................................................................. 125°C Storage Temperature Range SSOP ................................................. –65°C to 150°C QFN ................................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C TOP VIEW ORDER PART NUMBER 18 V+ 17 OUT1 16 V– 15 OUT2 14 V+ 13 OUT3 24 23 22 21 20 19 LT6555CUF LT6555IUF 25 7 8 9 10 11 12 UF PART* MARKING 6555 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W EXPOSED PAD (PIN 25) IS V – MUST BE SOLDERED TO PCB MIN TYP 5 –17 MAX ±16 ± 24 ± 45 UNITS mV mV µA kΩ pF dB 100 56 400 1 62 1 ±0.33 ±4 ±2.5 µA/V % % V V 6555f ±3.15 ±3.0 ±3.4 LT6555 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND, VVREF = 0V. SYMBOL IS PARAMETER Supply Current, Per Amplifier Supply Current, Disabled, Per Amplifier IEN ISEL ISC SR –3dB BW 0.1dB BW FPBW Enable Pin Current Select Pin Current Output Short-Circuit Current Slew Rate Small-Signal –3dB Bandwidth Gain Flatness ±0.1dB Bandwidth Full Power Bandwidth 2V Full Power Bandwidth 4V All-Hostile Crosstalk Selected Channel to Unselected Channel Crosstalk Channel Select Output Transient Channel-to-Channel Select Time tS tR, tF dG dP HD2 HD3 Settling Time Small-Signal Rise and Fall Time Differential Gain Differential Phase 2nd Harmonic Distortion 3rd Harmonic Distortion CONDITIONS RL = ∞ ● ELECTRICAL CHARACTERISTICS MIN TYP 9 MAX 12 14 500 500 UNITS mA mA µA µA µA µA µA µA mA V/µs MHz MHz MHz MHz dB dB dB dB mVP-P ns ns ps % Deg dBc dBc VEN = 4V, RL = ∞ VEN = Open, RL = ∞ VEN = 0.4V VEN = 4V VSEL = 0.4V VSEL = 4V RL = 0Ω, VIN = ±1V ±1V on ±2.5V Output Step (Note 8) VOUT = 200mVP-P VOUT = 200mVP-P VOUT = 2VP-P (Note 9) VOUT = 4VP-P (Note 9) f = 10MHz, VIN = 1VP-P f = 100MHz, VIN = 1VP-P f = 10MHz, VIN = 1VP-P f = 100MHz, VIN = 1VP-P INA = INB = 0V INA = –1V, INB = 1V from 50% SEL to VOUT = 0V 0.1% of VFINAL, VSTEP = 2V 10% to 90%, VOUT = 400mVP-P (Note 10) (Note 10) f = 10MHz, VOUT = 2VP-P f = 10MHz, VOUT = 2VP-P ● ● ● ● ● ● ● 47 42 –200 –75 –50 –50 ±50 1600 –95 –21 –5 –1 ±105 2200 650 120 250 350 175 –72 –50 –80 –55 200 8 6.5 520 0.033 0.022 –80 –70 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It is not production tested. Note 3: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Depending on the supply voltage, a heat sink may be required. Note 4: The LT6555C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 5: The LT6555C is guaranteed to meet specified performance from 0°C to 70°C. The LT6555C is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6555I is guaranteed to meet specified performance from –40°C to 85°C. Note 6: In order to follow the constraints for 4.5V operation for PSRR and IPSRR testing at ± 2.25V, the DGND pin is set to V–, the EN pin is set to V– + 0.4V, and the SEL pin is set to either V– + 0.4V or V– + 4V. At ±6V and all other cases, DGND is set to ground and the EN and SEL pins are referenced from it. Note 7: The VREF pin is set to 1V when testing positive swing and –1V when testing negative swing to ensure that the internal input clamps do not limit the output swing. Note 8: Slew rate is 100% production tested using both inputs of channel 2. Slew rates of channels 1 and 3 are guaranteed through design and characterization. Note 9: Full power bandwidth is calculated from the slew rate: FPBW = SR/(π • VP-P) Note 10: Differential gain and phase are measured using a Tektronix TSG120YC/NTSC signal generator and a Tektronix 1780R video measurement set. The resolution of this equipment is better than 0.05% and 0.05°. Nine identical amplifier stages were cascaded giving an effective resolution of better than 0.0056% and 0.0056%. 6555f 3 LT6555 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current per Amplifier vs Temperature 12 10 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VEN = 0V VEN = 0.4V 8 6 4 2 VEN = 4V 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 6555 G01 Input Referred Offset Voltage vs Temperature 15 10 VS = ± 5V VIN = 0V INPUT BIAS CURRENT (µA) OFFSET VOLTAGE (mV) EN PIN CURRENT (µA) 5 0 –5 –10 –15 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 6555 G04 Maximum Output Voltage Swing vs VREF Pin Voltage 4 3 TA = – 55°C HIGH SWING OUTPUT VOLTAGE (V) TA = 25°C TA = 125°C 4 5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2 1 0 –1 –2 –3 LOW SWING –4 VS = ± 5V RL = 150Ω TA = 125°C TA = 25°C TA = – 55°C –2 –1.5 –1 –0.5 0 0.5 1 VREF PIN VOLTAGE (V) 1.5 2 0 0 10 20 30 40 50 60 70 80 90 100 SOURCE CURRENT (mA) 6555 G08 4 UW VS = ±5V RL = ∞ VIN = 0V 6555 G07 Supply Current per Amplifier vs Supply Voltage 12 10 8 6 4 2 0 VEN, VIN, VDGND, VSEL = 0V TA = 25°C 12 10 Supply Current per Amplifier vs EN Pin Voltage VS = ±5V RL = ∞ VIN = 0V TA = –55°C 8 TA = 25°C 6 4 2 0 TA = 125°C 0 1 2 3 4 5 6 7 8 9 10 11 12 TOTAL SUPPLY VOLTAGE (V) 6555 G02 0 0.5 1.0 1.5 2.0 2.5 3.0 EN PIN VOLTAGE (V) 3.5 4.0 6555 G03 Input Bias Current vs Temperature 0 –5 –10 –15 –20 VIN = –1.5V –25 –30 –35 –40 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 6555 G05 EN Pin Current vs EN Pin Voltage 0 –20 VS = ±5V VDGND = 0V VS = ± 5V VIN = 0V VIN = 1.5V –40 –60 –80 TA = 25°C –100 –120 –140 0 1 3 2 EN PIN VOLTAGE (V) 4 5 6555 G06 TA = 125°C TA = –55°C Output Voltage Swing vs ILOAD (Output High) VREF INPUT CLAMPING VS = ± 5V VIN = 2V VVREF = 0V Output Voltage Swing vs ILOAD (Output Low) 0 VS = ± 5V VIN = –2V VVREF = 0V TA = 125°C TA = 25°C TA = – 55°C –2 –1 3 2 TA = 125°C TA = 25°C TA = – 55°C –3 1 –4 VREF INPUT CLAMPING –5 0 10 20 30 40 50 60 70 80 90 100 SINK CURRENT (mA) 6555 G09 6555f LT6555 TYPICAL PERFOR A CE CHARACTERISTICS Input Noise Spectral Density INPUT NOISE VOLTAGE (nV/√Hz OR pA/√Hz) 1000 VS = ± 5V TA = 25°C 1000 POWER SUPPLY REJECTION RATIO (dB) INPUT IMPEDANCE (kΩ) 100 in 10 en 1 0.001 0.01 0.1 1 FREQUENCY (kHz) Frequency Response vs Output Amplitude 9 8 7 6 VS = ±5V RL = 150Ω TA = 25°C NORMALIZED GAIN (dB) GAIN (dB) GAIN (dB) 5 4 3 2 1 0 0.1 1 10 100 FREQUENCY (MHz) 1000 6555 G13 VOUT = 200mVP-P VOUT = 2VP-P VOUT = 4VP-P Crosstalk vs Frequency VS = ± 5V VOUT = 2VP-P –20 RL = 150Ω TA = 25°C AMPLITUDE (dB) AMPLITUDE (dB) –40 –60 –80 0 0 –40 –60 –80 DRIVE IN A, SELECT IN B DRIVE IN B, SELECT IN A DISTORTION (dBc) WORST ADJACENT ALL CHANNELS DRIVEN –100 –120 0.1 1 10 100 FREQUENCY (MHz) UW 10 6555 G10 6555 G16 Input Impedance vs Frequency VS = ±5V VIN = 0V TA = 25°C 70 60 Input Referred PSRR vs Frequency ± PSRR +PSRR 50 40 30 20 10 0 0.001 –PSRR VS = ±5V TA = 25°C 100 10 1 100 0.1 0.01 0.1 1 10 FREQUENCY (MHz) 100 1000 6555 G11 0.01 0.1 1 FREQUENCY (MHz) 10 100 6555 G12 Gain Flatness vs Frequency 6.20 6.15 IN1A 6.10 IN3A 6.05 IN1B 6.00 5.95 IN2B VS = ± 5V VOUT = 200mVP-P RL = 150Ω TA = 25°C 1 10 100 FREQUENCY (MHz) 1000 6555 G14 Frequency Response with Capacitive Loads 18 16 14 12 10 8 6 4 2 0 –2 –4 –6 0.1 1 10 100 FREQUENCY (MHz) 1000 6555 G15 VS = ± 5V VOUT = 2VP-P RL = 150Ω TA = 25°C CL = 10pF CL = 4.7pF CL = 0pF IN3B IN2A 5.90 0.1 Crosstalk vs Frequency VS = ± 5V VIN = 1VP-P –20 RL = 150Ω TA = 25°C Harmonic Distortion vs Frequency 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0.01 HD3 HD2 VS = ± 5V VOUT = 2VP-P RL = 150Ω TA = 25°C –100 –120 0.1 1000 1 10 100 FREQUENCY (MHz) 1000 6555 G17 0.1 1 10 FREQUENCY (MHz) 100 6555 G18 6555f 5 LT6555 TYPICAL PERFOR A CE CHARACTERISTICS Output Impedance vs Frequency 1000 DISABLED VEN = 4V 0.4 0.3 0.2 OUTPUT IMPEDANCE (Ω) 100 OUTPUT (V) OUTPUT (V) 10 1 ENABLED VEN = O.4V 0.1 0.01 VS = ± 5V RL = 150Ω TA = 25°C 100 1000 6555 G19 0.1 1 10 FREQUENCY (MHz) Large-Signal Transient Response 1.5 1.0 0.5 VIN = 1VP-P VS = ± 5V RL = 150Ω TA = 25°C OUTPUT (V) 0 –0.5 –1.0 –1.5 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6555 G22 OUTPUT (V) 1 0 –1 –2 –3 –4 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6555 G23 PERCENT OF UNITS (%) Gain Matching Distribution 40 35 VS = ± 5V VOUT = ± 2V RL = 150Ω TA = 25°C PERCENT OF UNITS (%) 30 25 20 15 SEL A/B (V) 10 5 0 0 –1.5 –1.0 –0.5 1.5 0.5 1.0 GAIN MATCHING–BETWEEN CHANNELS (%) 6555 G25 SEL A/B (V) 6 UW Small-Signal Transient Response 1.8 VIN = 200mVP-P VS = ± 5V RL = 150Ω TA = 25°C 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.3 –0.4 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6555 G20 Video Amplitude Transient Response 0.1 0 –0.1 –0.2 –0.2 –0.4 0 2 VIN = 0V TO 700mV VS = ± 5V RL = 150Ω TA = 25°C 4 6 8 10 12 14 16 18 20 TIME (ns) 6555 G21 Large-Signal Transient Response 4 3 2 VIN = 2.5VP-P VS = ± 5V RL = 150Ω TA = 25°C 40 35 30 25 20 15 10 5 Gain Error Distribution VS = ± 5V VOUT = ± 2V RL = 150Ω TA = 25°C 0 –1.5 0 1.5 –1.0 –0.5 0.5 1.0 GAIN ERROR—INDIVIDUAL CHANNEL (%) 6555 G24 Channel Switching Transient VS = ±5V RL = 150Ω INA = 0V TA = 25°C INB = 0V 0.2 0.1 0 Channel Switching Transient 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 OUT (V) –0.1 5 4 2 0 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 6555 G26 OUT (V) 5 4 3 2 1 0 0 INB = 300MHz, 1VP-P SINE VS = ±5V RL = 150Ω TA = 25°C INA = 0V 6555 G27 10 20 30 40 50 60 70 80 90 100 TIME (ns) 6555f LT6555 PI FU CTIO S (GN24 Package) IN1A (Pin 1): Channel 1 Input A. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. DGND (Pin 2): Digital Ground Reference for Enable Pin. This pin is normally connected to ground. IN2A (Pin 3): Channel 2 Input A. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. VREF (Pin 4): Voltage Reference for Input Clamping. This is the tap to an internal voltage divider that defines midsupply. It is normally connected to ground in dual supply, DC coupled applications. IN3A (Pin 5): Channel 3 Input A. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND1 (Pin 6): Analog Ground for the 360Ω Gain Resistor of Channel 1. IN1B (Pin 7): Channel 1 Input B. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND2 (Pin 8): Analog Ground for the 360Ω Gain Resistor of Channel 2. IN2B (Pin 9): Channel 2 Input B. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND3 (Pin 10): Analog Ground for the 360Ω Gain Resistor of Channel 3. IN3B (Pin 11): Channel 3 Input B. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. V – (Pin 12): Negative Supply Voltage. V – pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. V + (Pins 13, 14, 24): Positive Supply Voltage. V+ pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. V – (Pin 15): Negative Supply Voltage for Channel 3 Output Stage. V – pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUT3 (Pin 16): Channel 3 Output. It is twice the selected channel 3 input and performs optimally with a 150Ω load (a double terminated 75Ω cable). V + (Pin 17): Positive Supply Voltage for Channels 2 and 3 Output Stages. V+ pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUT2 (Pin 18): Channel 2 Output. It is twice the selected channel 2 input and performs optimally with a 150Ω load (a double terminated 75Ω cable). V – (Pin 19): Negative Supply Voltage for Channels 1 and 2 Output Stages. V – pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUT1 (Pin 20): Channel 1 Output. It is twice the selected channel 1 input and performs optimally with a 150Ω load (a double terminated 75Ω cable). V + (Pin 21): Positive Supply Voltage for Channel 1 Output Stage. V+ pins are not internally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. SEL (Pin 22): Select Pin. This high impedance pin selects which set of inputs are sent to the output pins. When the pin is pulled low, the A inputs are selected. When the pin is pulled high, the B inputs are selected. EN (Pin 23): Enable Control Pin. An internal pull-up resistor of 46k defines the pin’s impedance and will turn the part off if the pin is unconnected. When the pin is pulled low, the amplifiers are enabled. Exposed Pad (Pin 25, QFN Only): The Exposed Pad is V– and must be soldered to the PCB. It is internally connected to the QFN Pin 4, V–. 6555f U U U 7 LT6555 APPLICATIO S I FOR ATIO Power Supplies The LT6555 is optimized for ±5V supplies but can be operated on as little as ±2.25V or a single 4.5V supply and as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation. Do not leave any supply pins disconnected or the part may not function correctly! Enable/Shutdown The LT6555 has a shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pullup resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the DC output impedance will rise to approximately 360Ω through the internal feedback and gain resistors. Supply current into the amplifier in the disabled state will be: V + – VEN V + – V – IS = + 46k 80k It is important that the following constraints on the DGND, EN and SEL pins are always followed: V+ – VDGND ≥ 4.5V VEN – VDGND ≤ 5.5V VSEL – VDGND ≤ 8V In dual supply cases where V+ is less than 4.5V, DGND should be connected to a potential below ground, such as V–. Since the EN and SEL pins are referenced to DGND, they may need to be pulled below ground in those cases. In single supply applications above 5.5V, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to float. For example, on a 12V single supply, a 33k resistor would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. On dual ±2.25V supplies, connecting the DGND pin to V– is the only way of ensuring that V+ – VDGND ≥ 4.5V. 8 U The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to 10mA or less. The enable/disable times of the LT6555 are fast when driven with a logic input. Turn on (from 50% EN input to 50% output) typically occurs in less than 50ns. Turn off is slower, but is typically below 500ns. Channel Select The SEL pin uses the same internal threshold as the EN pin and is also referenced to DGND. When the pin is logic low, the channel A inputs are passed to the output. When the pin is logic high, the channel B inputs are passed to the output. The pin should not be floated but can be tied to DGND to force the outputs to always be channel A or to V+ (when less than 8V) to force the outputs to always be channel B. Truth Table SEL A/B 0 1 X EN 0 0 1 OUT 2 × IN A 2 × IN B OFF W U U Input Considerations The LT6555 uses input clamps referenced to the VREF pin to prevent damage to the input stage on the unselected channel. Three transistors in series limit the input voltage to within three diode drops (±) from VREF. VREF is nominally set to half of the sum of the supplies by the 40k resistors. A simplified schematic is shown in Figure 1. To improve clamping, the pin’s DC impedance should be minimized by connecting the VREF pin directly to ground in the symmetric dual supply case with a common mode voltage of 0V. While loaded output swing limits the useful input voltage range in that case, if the common mode voltage is not centered at ground or the input voltage exceeds plus or minus three diodes from ground, an external resistor to either supply can be added to shift the 6555f LT6555 APPLICATIO S I FOR ATIO V+ IN V– Figure 1. Simplified Schematic of VREF Pin and Input Clamping VREF voltage to the desired level. The only way to cover the full common mode voltage range of V– + 1V to V+ – 1V is to shift VREF up or down. Note that on a single supply, the unclamped input range limits the output low swing to 2V (1V multiplied by the internal gain of 2). The VREF pin can also be directly driven with a DC source. Bypassing the VREF pin is not necessary. The inputs can be driven beyond the point at which the output clips so long as input currents are limited to less than ±10mA. Continuing to drive the input beyond the output limit can result in increased current drive and slightly increased swing, but will also increase supply current and may result in delays in transient response at larger levels of overdrive. Layout and Grounding It is imperative that care is taken in PCB layout in order to benefit from the very high speed and very low crosstalk of the LT6555. Separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. If input or output traces must be run over a distance of several centimeters, they should use a controlled impedance with matching series and shunt resistances (nominally 75Ω) to maintain signal fidelity. U 40k VREF 40k 6555 F01 W UU Series termination resistors should be placed as close to the output pins as possible to minimize output capacitance. See the Typical Performance Characteristics section for a plot of frequency response with various output capacitors—only 10pF of parasitic output capacitance before the series termination resistor causes 6dB of peaking in the frequency response! Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 4700pF ceramic capacitor is recommended for both V+ and V– supply busses. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional 1µF to 10µF tantalums should be added on each supply. The smallest value capacitors should be placed closest to the package. If the AGND pins are not connected to ground, they must be carefully bypassed to maintain minimal impedance over frequency. Although crosstalk will vary depending upon board layout, a recommended starting point for bypass capacitors would be 470pF as close as possible to each AGND pin with a single 4700pF capacitor in parallel. 6555f 9 LT6555 APPLICATIO S I FOR ATIO To maintain the LT6555’s channel isolation, it is beneficial to shield parallel input and parallel output traces using a ground plane or power supply traces. Vias between topside and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. See Figures 6 and 7 for photos of an optimized layout. Input Expansion In applications with more than two inputs per channel, multiple LT6555s can be connected by several different methods. The simplest method is to connect the outputs after the 75Ω series termination, as shown in Figure 2. The compromise of this approach is that the internal gain setting resistors cause a 435Ω shunt across the 75Ω cable termination, resulting in increased gain error. IN1A AV = 2 75Ω IN1B EN LT6555 #1 IN1C AV = +2 75Ω OUT 75Ω EN LT6555 #2 IN1D CHIP SELECT 74HC04 6555 F02 Figure 2. Two LT6555s Build a 4-Input Router 10 U Figure 3 illustrates the loading effect of expanding the number of inputs. The resultant gain error can be calculated by the following formula using n as the number of LT6555s: ⎞ ⎛ 435Ω 75Ω ⎟ ⎜ Gain Error (dB) = 6dB + 20log ⎜ n – 1 ⎟ dB 435Ω ⎜ 75 + 75Ω ⎟ ⎠ ⎝ n–1 For example, two LT6555s would result in a gain error of –0.74dB per channel. Three LT6555s (i.e., six red inputs, six green inputs and six blue inputs), would have a gain error of –1.4dB. 1/3 LT6555 #1 IN1A 360Ω 75Ω OFF 360Ω IN1B W UU ⇒ 75Ω 435 n–1 R2 75Ω 360Ω OFF 360Ω n = NUMBER OF LT6555s IN PARALLEL 1/3 LT6555 #2 IN1C 360Ω 75Ω OFF 360Ω IN1D 75Ω CABLE 360Ω ON 360Ω . . . n 6555 F03 Figure 3. Disabled Amplifiers Load the Cable Termination with 435Ω Each 6555f LT6555 APPLICATIO S I FOR ATIO MULTIPLEXED OUTPUT (V) This systematic gain error can be significantly reduced by lowering the value of the 75Ω series termination resistors. The compromise of this approach is an increased dependence on the accuracy of the 75Ω shunt termination at the receiving end of the line. A table of values for 1% series termination resistors from n = 2 to n = 4 is shown below. NUMBER OF DEVICES (n) 2 3 4 SERIES RT 63.9 56.2 49.9 Another approach that does not compromise gain accuracy is to connect the outputs directly together before the series termination. In this case, there will be slightly increased output glitching and supply current spiking during the EN pin switching, but the additional output loading will not increase the gain error, and the series termination resistors remain at their ideal value for AC response. See Figure 4 for a scope photo showing the result of the outputs connected both before and after the series terminations, and Figure 8 for a full schematic of a 4:1 RGB multiplexer with the output pins directly connected together. It is imperative that the output traces be as short as possible before the series termination in order to reduce capacitance and minimize AC peaking. TYPICAL APPLICATIO RGB Multiplexer Demo Board The DC858A Demo Board illustrates optimal routing, bypassing and termination using the LT6555 as an RGB video multiplexer. The schematic is shown in Figure 5. All inputs and outputs are routed to have a characteristic impedance of 75Ω and 75Ω input shunt and output series terminations are connected as close to the part as U 1.5 1.0 0.5 0 –0.5 –1.0 OUTPUTS DIRECTLY CONNECTED IS– IS+ 150 100 50 0 0 0.5 1 1.5 2 2.5 TIME (µs) 3 3.5 4 SERIES 63.9Ω AT EACH OUTPUT VS = ±5V VIN(AMP1) = – 0.5V VIN(AMP2) = 0.5V RL = 150Ω W U UU SUPPLY CURRENT (mA) 6555 F04 Figure 4. 4-Input Router Switching with Outputs Directly Connected and with Outputs Connected After 63.9Ω Series Termination ESD Protection The LT6555 has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may flow through these diodes. If the current is kept below 10mA, no damage to the devices will occur. possible. The board is fabricated with four layers with internal ground and power planes. For ideal operation, a 75Ω load termination should be connected at the output. The LT6555’s gain of 2 will compensate for the resulting divider between the series and load termination resistors. Figures 6 and 7 show the topside and bottom side board layout and placement. 6555f 11 LT6555 TYPICAL APPLICATIO E1 EN J1 50Ω BNC 1 EN JP1 3 CONTROL 1 2 EXT ENABLE JP2 3 DGND 1 2 FLOAT AGND JP5 VREF E5 VREF E2 DGND 5 4 3 2 DGND 3 BNC × 6 5 JP12 1 L1 Z = 75 4 3 2 5 JP13 1 L1 Z = 75 4 3 2 5 JP14 1 L1 Z = 75 4 3 2 5 JP5 1 L1 Z = 75 4 3 2 5 JP6 1 L1 Z = 75 4 3 2 5 JP7 1 L1 Z = 75 4 3 2 1 C1 4700pF U1 LT6555CGN 1 24 V+ IN1A DGND 2 3 VREF 4 5 6 7 8 9 10 11 DGND IN2A VREF IN3A AGND1 IN1B AGND2 IN2B AGND3 IN3B V– EN SEL V + 2 EXT GND IN1A IN2A IN3A IN1B IN2B IN3B R10 75Ω R11 75Ω R12 75Ω R4 75Ω E3 AGND J3 BANANA JACK AGND Figure 6. Demo Board Topside (IC Removed for Clarity) 12 U E4 SEL A/B Z = 50 R8 50Ω OPT Z = 50 R9 50Ω OPT 2 3A R7 B 1 20k J8 50Ω BNC 1 SEL A/B VCC DGND 5432 JP4 SEL C2 470pF C3 470pF C10 4700pF C4 10µF 16V 1206 C11 0.33µF 16V V J2 BANANA JACK VCC 3.3V TO 5V CC 23 EN 22 21 20 19 18 17 16 15 14 13 J4 BANANA JACK VEE –3.3V TO –5V 6555 F05 SEL R1 75Ω R2 75Ω R3 75Ω BNC × 3 5 J9 4 3 2 J10 5 1 4 3 2 J11 5 1 4 3 2 1 OUT1 V– OUT2 V + Z = 75 L2 OUT1 Z = 75 L2 OUT2 OUT3 V– V+ V+ Z = 75 L2 OUT3 R5 75Ω R6 75Ω 12 C5 4700pF SINGLE DUAL 2 1 JP3 3 SUPPLY NOTE: 470pF BYPASS CAPACITORS LOCATED AS CLOSE TO PINS AS POSSIBLE C6 470pF C7 470pF C9 10µF 16V 1206 C8 0.33µF VEE Figure 5. Demo Board Schematic Figure 7. Demo Board Bottom Side 6555f SI PLIFIED SCHE ATIC W V+ OUT V+ 40k V REF 40k V– VREF 770Ω INA 100Ω 100Ω INB V+ V+ SEL 360Ω 360Ω BIAS TO OTHER OUTPUT STAGES V+ (One channel shown) EN 1k 46k V– V– DGND VREF SELECT TO OTHER INPUT STAGES V– 6555 SS 360Ω VREF 360Ω AGND V– W LT6555 13 6555f LT6555 PACKAGE DESCRIPTIO .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 14 U GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .045 ± .005 .033 (0.838) REF .229 – .244 (5.817 – 6.198) .150 – .165 .150 – .157** (3.810 – 3.988) 1 .0250 BSC 23 4 56 7 8 9 10 11 12 .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN24 (SSOP) 0204 6555f LT6555 PACKAGE DESCRIPTIO U UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ± 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 0.40 ± 0.10 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) 4.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 6555f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6555 TYPICAL APPLICATIO RED 1 GREEN 1 BLUE 1 RED 2 GREEN 2 BLUE 2 RED 3 GREEN 3 BLUE 3 RED 4 GREEN 4 BLUE 4 SEL0 NC75Z14 SEL1 RELATED PARTS PART NUMBER LT1203 LT1399 LT1675 LT6550/LT6551 LT6553 LT6554 DESCRIPTION 150MHz Single 2:1 Multiplexer 300MHz Triple Current Feedback Amplifier 250MHz Triple RGB Multiplexer 3.3V Triple and Quad Video Buffers 650MHz Gain of 2 Triple Video Amplifier 650MHz Gain of 1 Triple Video Amplifier COMMENTS Single SPDT Video Switch 0.1dB Gain Flatness to 150MHz, Shutdown 100MHz Pixel Switching, 1100V/µs Slew Rate, 16-Lead SSOP 110MHz Gain of 2 Buffers in MS Package Performance Similar to the LT6555 with One Set of Inputs, 16-Lead SSOP Same Pinout as the LT6553 but Optimized for High Impedance Loads 6555f 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U 75Ω LT6555 #1 IN1A IN1B 75Ω ×2 V+ 5V OUT1 75Ω IN2A IN2B 75Ω ×2 OUT2 75Ω IN3A IN3B 75Ω SEL EN ×2 OUT3 AGND DGND VREF V– –2V 5V 75Ω LT6555 #2 IN1A IN1B 75Ω ×2 OUT1 V+ 75Ω 75Ω BOUT 75Ω 75Ω GOUT 75Ω 75Ω ROUT 75Ω IN2A IN2B 75Ω ×2 OUT2 75Ω IN3A IN3B 75Ω SEL EN ×2 OUT3 AGND DGND VREF V– 6555 F08 SEL1 SEL0 OUTPUT 0 0 1 0 1 2 1 0 3 1 1 4 –2V Figure 8. 4:1 RGB Multiplexer LT/TP 0405 500 • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005