LT685CJ

LT685 High Speed Comparator FEATURES ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Ultrafast (5.5ns typ) Complementary ECL Output 50Ω Line Driving Capability Low Offset Voltage Output Latch Capability External Hysteresis Control Pin Compatible with Am685 The LT®685 is an ultrafast comparator with differential inputs and complementary outputs fully compatible with ECL logic levels. The output current capability is adequate for driving transmission lines terminated in 50Ω. The low input offset and high resolution make this comparator ideally suited for analog-to-digital signal processing applications. A latch function is provided to allow the comparator to be used in a sample-hold mode. When the latch enable input is ECL high, the comparator functions normally. When the latch enable is driven low, the comparator outputs are locked in their existing logical states. If the latch function is not used, the latch enable must be connected to ground or ECL high. The device is pin-compatible with the Am685. Hysteresis has been added to improve switching time with slow input signals as well as to minimize oscillation. A single resistor between the hysteresis pin and V – adds input hysteresis voltage as more current is drawn. If hysteresis is not required, the pin can be left unconnected. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S ■ ■ ■ High Speed A-to-D Converters High Speed Sampling Circuits Oscillators TYPICAL APPLICATIO Comparator with Hysteresis 100 6V GND1 V+ GND2 VIN + LT685 Q Q V– HYSTERESIS R LATCH ENABLE –5.2V VT LT685 • TA01 HYSTERESIS (mV) 10 – RL RL 1 100 200 U Hysteresis HYSTERESIS IS ZERO IF PIN LEFT OPEN 1k 2k 500 RESISTANCE (Ω) 5k 10k LT685 • TA02 U U 685fa 1 LT685 ABSOLUTE (Note 1) AXI U RATI GS Output Current ...................................................... 30mA Power Dissipation (Note 2) ................................ 500mW Operating Temperature LT685C ......................................... –30°C ≤ TA ≤ 85°C LT685M (OBSOLETE) ................. –55°C ≤ TA ≤ 125°C Positive Supply Voltage ............................................. 7V Negative Supply Voltage .......................................... –7V Input Voltage ........................................................... ±4V Differential Input Voltage ......................................... ±6V Latch Pin Voltage .............................................. 2V to V – Hysteresis Pin Voltage ...................................... 0V to V – PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW GND #1 + GND #2 V 10 1 9 NONINVERTING 2 INPUT INVERTING 3 INPUT 4 LATCH ENABLE LT685CH LT685MH + – 5 V– 6 8 Q OUTPUT 7 Q OUTPUT HYSTERESIS H PACKAGE TO-5 METAL CAN OBSOLETE PACKAGE Consider the N16 Package as an Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. 2 U U W WW U W TOP VIEW GND #1 1 V+ 2 NON-INVERTING INPUT 3 INVERTING INPUT 4 NC 5 LATCH ENABLE 6 NC 7 V– 8 N16 PACKAGE 16-LEAD CERDIP J16 PACKAGE (HERMETIC) 16-LEAD PDIP 16 GND #2 15 NC 14 NC 13 NC 12 Q OUTPUT 11 Q OUTPUT 10 NC 9 HYSTERESIS ORDER PART NUMBER LT685CN ORDER PART NUMBER LT685CJ LT685MJ LT685 • POI01 OBSOLETE PACKAGE Consider the N16 Package as an Alternate Source 685fa LT685 ELECTRICAL CHARACTERISTICS erature ranges, unless otherwise noted. SYMBOL VOS dVOS/dT lOS IB RIN CIN VCM CMRR SVRR VOH PARAMETER Input Offset Voltage Input Offset Voltage Drift Input Offset Current Input Bias Current Input Resistance Input Capacitance lnput Voltage Range Common Mode Rejection Supply Voltage Rejection Output High Voltage TA = 25°C TA = TMIN TA = TMAX TA = 25°C TA = TMIN TA = TMAX CONDITIONS TA = 25°C (Note 3) TA = 25°C TA= 25°C TA = 25°C (Note 3) TA = 25°C (Note 3) V+ = 6.0V, V– = – 5.2V, VT = –2V, RL = 50Ω, R = ∞ over the operating tempLT685C TYP 1.0 LT685M TYP 1.0 MIN MAX ±2.0 ±2.5 ±10 MIN MAX ±2.0 ±3.0 ±10 UNITS mV mV µV/°C µA µA µA µA kΩ 0.3 5 6.0 ±1.0 ±1.3 10 13 6.0 3.0 ±3.3 0.3 5 ±1.0 ±1.6 10 16 3.0 ±3.3 80 70 pF V dB dB 80 70 – 0.960 –1.060 – 0.890 –1.850 –1.890 –1.825 –0.810 –0.890 –0.700 –1.650 –1.675 –1.625 22 26 300 –0.960 –1.100 –0.850 –1.850 –1.910 –1.810 –0.810 –0.920 –0.620 –1.650 –1.690 –1.575 22 26 300 V V V V V V mA mA mW VOL Output Low Voltage I+ I– PDISS Positive Supply Current Negative Supply Current Power Dissipation 685fa 3 LT685 SWITCHI G CHARACTERISTICS SYMBOL tPD PARAMETER Propagation Delay (Note 4) Latch Enable to Output Delay (Note 3) Minimum Set-Up Time (Note 3) Minimum Hold Time (Note 3) Minimum Latch Enable Pulse Width (Note 3) CONDITIONS TA = 25°C TA = TMAX TA = TMIN TA = 25°C TA = TMAX TA = TMIN TMIN ≤ TA ≤ 25°C TA = TMAX TMIN ≤ TA ≤ TMAX TMIN ≤ TA ≤ 25°C TA = TMAX tPD(E) tS tH tPW(E) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: For the metal can package, derate at 6.8mW/°C for operation at ambient temperatures above 100°C; for the hermetic dual-in-line package, derate at 9mW/°C for operation at ambient temperatures above 105°C. Note 3: Guaranteed by design, but not tested. Note 4: Sample tested at 25°C only. 4 U (VIN = 100mV step, 5mV overdrive) MIN 4.5 5.0 4.0 4.5 5.0 4.0 LT685C TYP 5.5 MAX 6.5 9.5 6.5 6.5 9.5 6.5 3.0 4.0 1.0 3.0 4.0 MIN 4.5 5.5 3.5 4.5 5.5 3.5 LT685M TYP 5.5 MAX 6.5 12 6.5 6.5 12 6.5 3.0 6.0 1.0 3.0 5.0 UNITS ns ns ns ns ns ns ns ns ns ns ns 5.5 5.5 Definitions: tPD: The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of the output transition. tPD(E): The propagation delay measured from the 50% point of the latch enable signal positive transition to the 50% point of the output transition. tS: The minimum time before the negative transition of the latch enable signal that an input signal change must be present in order to be acquired and held at the outputs. tH: The minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. tPW (E): The minimum time that the latch enable signal must be HIGH in order to acquire and hold an input signal change. 685fa LT685 SCHE ATIC DIAGRA R2 300Ω D2 Q13 D1 Q33 R22 2.9k Q3 Q31 Q18 Q30 NONINVERTING INPUT INVERTING INPUT Q7 Q1 Q5 Q2 R3 1.4k R4 2.4k R21 846Ω Q29 LATCH ENABLE Q9 Q10 Q28 Q11 R11 430Ω Q12 R12 200Ω HYSTERESIS R19 2.4k Q27 R10 880Ω R14 3k Q26 R18 150Ω R13 3.0k R15 2.1k R16 2.1k Q25 R17 150Ω V– LT685 • S01 Q4 Q8 Q6 D5 D6 Q23 Q21 Q16 Q15 Q22 Q24 D7 D8 R7 275Ω R8 275Ω W V+ R1 300Ω R23 1.7k Q14 R6 525Ω D4 D3 Q32 Q20 Q17 GND #2 GND #1 R5 525Ω Q19 R20 3.8k Q Q OUTPUT OUTPUT 685fa W 5 LT685 TYPICAL PERFOR A CE CHARACTERISTICS Propagation Delays as a Function of Temperature 12 10 PROPAGATION (ns) HYSTERESIS (mV) 8 VOD = 5mV 6 VOD = 2.5mV 4 V = 20mV OD 2 –50 –25 50 25 0 75 TEMPERATURE (°C) PACKAGE DESCRIPTIO SEATING PLANE 0.010 – 0.045* (0.254 – 1.143) 0.016 – 0.021** (0.406 – 0.533) 36°BSC 0.028 – 0.034 (0.711 – 0.864) 0.110 – 0.160 (2.794 – 4.064) INSULATING STANDOFF 6 U UW Hysteresis as a Function of Temperature 100 90 80 70 60 50 40 30 20 10 R = 1000Ω 50 25 0 75 TEMPERATURE (°C) 100 125 R = 500Ω R = 200Ω VOD = 10mV 100 125 0 –50 –25 LTC685 • TPC01 LTC685 • TPC02 H Package 10-Lead TO-5 Metal Can (Reference LTC DWG # 05-08-1322) 0.335 – 0.370 (8.509 – 9.398) DIA 0.305 – 0.335 (7.747 – 8.509) 0.040 (1.016) MAX 0.050 (1.270) MAX GAUGE PLANE 0.165 – 0.185 (4.191 – 4.699) REFERENCE PLANE 0.500 – 0.750 (12.700 – 19.050) 0.027 – 0.045 (0.686 – 1.143) PIN 1 0.230 ( 5.842) TYP *LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND 0.045" BELOW THE REFERENCE PLANE 0.016 – 0.024 **FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS (0.406 – 0.610) H10(TO-5) 1197 OBSOLETE PACKAGE 685fa LT685 PACKAGE DESCRIPTIO CORNER LEADS OPTION (4 PLCS) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.300 BSC (0.762 BSC) 0.008 – 0.018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U J Package 16-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 0.840 (21.336) MAX 16 15 14 13 12 11 10 9 0.005 (0.127) MIN 0.025 (0.635) RAD TYP 1 2 3 4 5 6 7 8 0.200 (5.080) MAX 0.015 – 0.060 (0.380 – 1.520) 0.220 – 0.310 (5.588 – 7.874) 0.125 (3.175) MIN 0.045 – 0.065 (1.143 – 1.651) 0.014 – 0.026 (0.360 – 0.660) 0.100 (2.54) BSC J16 1298 OBSOLETE PACKAGE 685fa 7 LT685 PACKAGE DESCRIPTIO U N Package 16-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 5 6 7 8 0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.100 (2.54) BSC N16 1098 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) +0.035 0.325 –0.015 ( 8.255 +0.889 –0.381 ) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 685fa 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LW/TP 0902 1K REV A • PRINTED IN USA www.linear.com  LINEAR TECHNOLOGY CORPORATION 1988