LTBGP

LTC1403-1/LTC1403A-1 Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown FEATURES s s s s s s s s s s DESCRIPTIO 2.8Msps Conversion Rate Low Power Dissipation: 14mW 3V Single Supply Operation 2.5V Internal Bandgap Reference can be Overdriven 3-Wire Serial Interface Sleep (10µW) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection ±1.25V Bipolar Input Range Tiny 10-Lead MSE Package The LTC®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps serial ADCs with differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MSE package. A Sleep shutdown feature lowers power consumption to 10µW. The combination of speed, low power and tiny package makes the LTC1403-1/LTC1403A-1 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for +AIN and –AIN extends from ground to the supply voltage. The serial interface sends out the conversion results during the 16 clock cycles following CONV↑ for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition BLOCK DIAGRA 10µF 3V LTC1403A-1 AIN+ AIN– 1 7 VDD 14-BIT LATCH THREESTATE SERIAL OUTPUT PORT 14 + S&H 14-BIT ADC THD, 2nd, 3rd (dB) 8 SDO 2 – VREF 2.5V REFERENCE 3 10µF 4 10 TIMING LOGIC 9 6 11 EXPOSED PAD CONV GND 5 SCK 14031 BD U THD, 2nd and 3rd vs Input Frequency for Differential Input Signals –44 –50 –56 –62 –68 –74 –80 –86 –92 –98 –104 0.1 1 10 FREQUENCY (MHz) 100 14031 G19 W U THD 3rd 2nd 14031f 1 LTC1403-1/LTC1403A-1 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW AIN+ AIN– VREF GND GND 1 2 3 4 5 10 9 8 7 6 CONV SCK SDO VDD GND Supply Voltage (VDD) ................................................. 4V Analog Input Voltage (Note 3) ....................................–0.3V to (VDD + 0.3V) Digital Input Voltage ................... – 0.3V to (VDD + 0.3V) Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 100mW Operation Temperature Range LTC1403C-1/LTC1403AC-1 ..................... 0°C to 70°C LTC1403I-1/LTC1403AI-1 .................. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C 11 LTC1403CMSE-1 LTC1403IMSE-1 LTC1403ACMSE-1 LTC1403AIMSE-1 MSE PART MARKING LTBGP LTBGQ LTBGR LTBGS MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 150°C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Gain Error Gain Tempco (Notes 4, 5, 18) (Notes 4, 18) (Note 4, 18) CONDITIONS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3V MIN q q q q LTC1403-1 TYP MAX ±0.25 ±1 ±5 ±15 ±1 2 10 30 LTC1403A-1 MIN TYP MAX 14 –4 –20 –60 ± 0.5 ±2 ± 10 ± 15 ±1 4 20 60 UNITS Bits LSB LSB LSB ppm/°C ppm/°C 12 –2 –10 –30 Internal Reference (Note 4) External Reference A ALOG I PUT SYMBOL PARAMETER VIN VCM IIN CIN tACQ tAP tJITTER CMRR The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V CONDITIONS 2.7V ≤ VDD ≤ 3.3V q MIN TYP –1.25 to 1.25 0 to VDD MAX UNITS V V Analog Differential Input Range (Notes 3, 8, 9) Analog Common Mode + Differential Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio q 1 13 39 1 0.3 (Note 6) q fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V –60 –15 2 U µA pF ns ns ps dB dB 14031f W U U WW W U U U LTC1403-1/LTC1403A-1 DY A IC ACCURACY SYMBOL SINAD PARAMETER Signal-to-Noise Plus Distortion Ratio The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V. Single-ended AIN+ signal drive with AIN– = 1.5V DC. Differential signal drive with VCM = 1.5V at AIN+ and AIN– CONDITIONS 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V (Note 19) 750kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V (Note 19) 100kHz First 5 Harmonics (Note 19) 1.4MHz First 5 Harmonics (Note 19) 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 0.625VP-P 1.4MHz Summed with 0.625VP-P 1.56MHz into AIN+ and Inverted into AIN– VREF = 2.5V (Note 18) VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) S/(N + D) ≥ 68dB q THD SFDR IMD I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time CONDITIONS IOUT = 0 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V MIN TYP 2.5 15 VDD = 2.7V to 3.6V, VREF = 2.5V Load Current = 0.5mA 600 0.2 2 MAX UNITS V ppm/°C µV/V Ω ms DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT = 0V, VDD = 3V VOUT = VDD = 3V CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD (Note 20) The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V MIN q q q U U U WU U MIN 68 LTC1403-1 TYP MAX 70.5 70.5 72 72 –87 –83 –87 –83 –82 0.25 50 5 LTC1403A-1 MIN TYP MAX 70 73.5 73.5 76.3 76.3 –90 –86 –90 –86 –82 1 50 5 UNITS dB dB dB dB dB dB dB dB dB LSBRMS MHz MHz Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth q –76 –78 U TYP MAX 0.6 ± 10 UNITS V V µA pF V V V µA pF mA mA 14031f 2.4 5 q q q VDD = 3V, IOUT = – 200µA VDD = 2.7V, IOUT = 160µA VDD = 2.7V, IOUT = 1.6mA VOUT = 0V to VDD 2.5 2.9 0.05 0.10 1 20 15 0.4 ± 10 3 LTC1403-1/LTC1403A-1 POWER REQUIRE E TS SYMBOL VDD IDD PARAMETER Supply Voltage Positive Supply Voltage The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 17) CONDITIONS Active Mode Nap Mode Sleep Mode (LTC1403) Sleep Mode (LTC1403A) Active Mode with SCK in Fixed State (Hi or Lo) q q PD Power Dissipation The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 PARAMETER Maximum Sampling Frequency per Channel (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Clock Period Conversion Time Minimum Positive or Negative SCLK Pulse Width CONV to SCK Setup Time Nearest SCK Edge Before CONV Minimum Positive or Negative CONV Pulse Width SCK to Sample Mode CONV to Hold Mode 16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) Minimum Delay from SCK to Valid Data SCK to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition CONDITIONS q q TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-scale specifications are measured for a singleended AIN+ input with AIN– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between AIN+ and AIN–. Performance is specified with AIN– = 1.5V DC while driving AIN+. Note 9: The absolute voltage at AIN+ and AIN– must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 4 UW MIN 2.7 TYP 4.7 1.1 2 2 12 MAX 3.6 7 1.5 15 10 UNITS V mA mA µA µA mW UW MIN 2.8 TYP MAX UNITS MHz ns ns SCLK cycles ns ns ns ns ns ns ns ns ns ns ms (Note 16) (Note 6) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Notes 6, 14) q 19.8 16 2 3 0 4 4 1.2 45 8 6 2 357 10000 18 2 Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read without an arbitrarily long clock. Note 17: VDD = 3V, fSAMPLE = 2.8Msps. Note 18: The LTC1403A-1 is measured and specified with 14-bit Resolution (1LSB = 152µV) and the LTC1403-1 is measured and specified with 12-bit Resolution (1LSB = 610µV). Note 19: Full-scale sinewaves are fed into the noninverting input while the inverting input is kept at 1.5V DC. Note 20: The sampling capacitor at each input accounts for 4.1pF of the input capacitance. 14031f LTC1403-1/LTC1403A-1 TA = 25°C, VDD = 3V. Single ended AIN+ signal drive with AIN– = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1) ENOBs and SINAD vs Input Frequency 12.0 11.5 11.0 74 71 68 65 62 59 56 53 1 10 FREQUENCY (MHz) 50 100 14031 G01 TYPICAL PERFOR A CE CHARACTERISTICS 10.0 9.5 9.0 8.5 8.0 0.1 –74 –80 –86 –92 –98 –104 0.1 THD 3rd 2nd SFDR (dB) 100 14031 G02 10.5 THD, 2nd, 3rd (dB) ENOBs (BITS) SNR vs Input Frequency 74 71 68 12.0 11.5 11.0 SNR (dB) 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100 14031 G04 10.5 10.0 9.5 9.0 8.5 8.0 0.1 1 10 FREQUENCY (MHz) 65 62 59 56 53 50 100 14031 G18 THD, 2nd, 3rd (dB) ENOBs (BITS) SFDR vs Input Frequency for Differential Input Signals 104 98 92 MAGNITUDE (dB) MAGNITUDE (dB) 86 SFDR (dB) 80 74 68 62 56 50 44 0.1 1 10 FREQUENCY (MHz) 100 14031 G20 UW THD, 2nd and 3rd vs Input Frequency –44 –50 –56 –62 –68 SFDR vs Input Frequency 104 98 92 86 80 74 68 62 56 50 SINAD (dB) 1 10 FREQUENCY (MHz) 44 0.1 1 10 FREQUENCY (MHz) 100 14031 G03 ENOBs and SINAD vs Input Frequency for Differential Input Signals 74 71 68 THD, 2nd and 3rd vs Input Frequency for Differential Input Signals –44 –50 –56 –62 –68 –74 –80 –86 –92 –98 –104 0.1 1 10 FREQUENCY (MHz) 100 14031 G19 SINAD (dB) THD 3rd 2nd 98kHz Sine Wave 4096 Point FFT Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 350 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G05 1.3MHz Sine Wave 4096 Point FFT Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 350k 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G06 14031f 5 LTC1403-1/LTC1403A-1 TA = 25°C, VDD = 3V. Single ended AIN+ signal drive with AIN– = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1) 1.4MHz Input Summed with 1.56MHz Input IMD 4096 Point FFT Plot for Differential Input Signals 0 –10 –20 –30 0 –10 –20 MAGNITUDE (dB) TYPICAL PERFOR A CE CHARACTERISTICS MAGNITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 200k 400k 600k 800k 1M FREQUENCY (Hz) 1.2M 1.4M 14031 G07 MAGNITUDE (dB) Differential Linearity vs Output Code 1.0 0.8 4 3 DIFFERENTIAL LINEARITY (LSB) INTEGRAL LINEARITY (LSB) 2 1 0 –1 –2 –3 –4 INTEGRAL LINEARITY (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 12288 8192 OUTPUT CODE 16384 14031 G08 Differential and Integral Linearity vs Conversion Rate 8 7 6 5 LINEARITY (LSB) 4 3 2 1 0 –1 –2 –3 –4 2 2.25 2.5 2.75 3 3.25 3.5 3.75 CONVERSION RATE (Msps) 4 MIN INL MAX DNL MIN DNL S/(N+D) (dB) 18 CLOCKS PER CONVERSION 6 UW 1.3MHz Sine Wave 4096 Point FFT Plot for Differential Input Signals 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 350 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G21 10.7MHz Sine Wave 4096 Point FFT Plot for Differential Input Signals –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 350 700k 1.05M FREQUENCY (Hz) 1.4M 14031 G22 Integral Linearity vs Output Code 4 3 2 1 0 –1 –2 –3 0 4096 12288 8192 OUTPUT CODE –4 16384 14071 G09 Integral Linearity vs Output Code for Differential Input Signals 0 4096 12288 8192 OUTPUT CODE 16384 14071 G23 SINAD vs Conversion Rate 78 77 76 MAX INL 75 74 73 72 71 70 69 68 2 EXTERNAL VREF = 3.3V fIN ~ fS/3 EXTERNAL VREF = 3.3V fIN ~ fS/40 INTERNAL VREF = 2.5V fIN ~ fS/3 INTERNAL VREF = 2.5V fIN ~ fS/40 2.25 2.5 2.75 3 3.25 3.5 3.75 CONVERSION RATE (Msps) 4 14031 G10 14031 G11 14031f LTC1403-1/LTC1403A-1 TYPICAL PERFOR A CE CHARACTERISTICS 2.5VP-P Power Bandwidth 12 6 0 AMPLITUDE (dB) CMRR (dB) PSRR (dB) –6 –12 –18 –24 –30 –36 1M 10M 100M FREQUENCY (Hz) 1G 14031 G12 Reference Voltage vs Load Current 2.4902 2.4900 2.4898 VREF (V) VDD SUPPLY CURRENT (mA) VREF (V) 2.4896 2.4894 2.4892 2.4890 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 14031 G15 UW TA = 25°C, VDD = 3V (LTC1403-1 and LTC1403A-1) PSRR vs Frequency –25 –30 CMRR vs Frequency 0 –20 –35 –40 –60 –80 –100 –40 –45 –50 –55 –60 –65 –120 100 –70 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 14031 G13 14031 G14 Reference Voltage vs VDD 2.4902 2.4900 2.4898 2.4896 2.4894 2.4892 2.4890 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 14031 G16 VDD Supply Current vs Conversion Rate 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 CONVERSION RATE (Msps) 14031 G17 14031f 7 LTC1403-1/LTC1403A-1 PI FU CTIO S AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN– with a –1.25V to 1.25V differential swing with respect to AIN– and a 0V to VDD common mode swing. AIN– (Pin 2): Inverting Analog Input. AIN– operates fully differentially with respect to AIN+ with a 1.25V to –1.25V differential swing with respect to AIN+ and a 0V to VDD common mode swing. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference between 2.55V and VDD. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. VDD (Pin 7): 3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-State Serial Data Output. Each of output data words represents the difference between AIN+ and AIN– analog inputs at the start of the previous conversion. The output format is 2’s complement. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. Responds to TTL (≤ 3V) and 3V CMOS levels. One or more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (≤ 3V) and 3V CMOS levels. Two pulses with SCK in fixed high or fixed low state start Nap mode. Four or more pulses with SCK in fixed high or fixed low state start Sleep mode. BLOCK DIAGRA 1 + S&H 14-BIT ADC 14-BIT LATCH AIN+ AIN– 10µF 4 GND 5 6 8 W U U U 10µF 3V LTC1403A-1 7 VDD THREESTATE SERIAL OUTPUT PORT 14 8 SDO 2 – VREF 2.5V REFERENCE 3 10 TIMING LOGIC 9 11 EXPOSED PAD CONV SCK 14031 BD 14031f LTC1403-1/LTC1403A-1 TI I G DIAGRA 17 SCK t4 CONV t6 INTERNAL S/H STATUS SAMPLE t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* Hi-Z 14031 TD01 18 *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED. 17 SCK t4 CONV t6 INTERNAL S/H STATUS 18 SAMPLE t8 SDO SLK t1 CONV t1 NAP SLEEP t12 VREF 14031 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS W LTC1403 Timing Diagram t2 t3 1 2 3 4 5 6 7 t1 8 9 10 11 12 13 14 15 16 t7 17 18 1 t5 tACQ HOLD t8 SAMPLE t9 HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT UW LTC1403A Timing Diagram t2 t3 1 2 3 4 5 6 7 t1 8 9 10 11 12 13 14 15 16 t7 17 18 1 t5 tACQ HOLD t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z 14031 TD01b SAMPLE t9 HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT Nap Mode and Sleep Mode Waveforms SCK to SDO Delay SCK t8 t10 SDO VOH VOL 14031 TD03 VIH SCK VIH t9 90% SDO 10% 14031f 9 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1403-1/LTC1403A-1 are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the AIN– input is set to VCM). Both differential analog inputs, AIN+ with AIN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1403-1/ LTC1403A-1 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier, the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance ( 1403 bipolar Sine wave collection with Serial Port interface bvectors.asm buffered mode. s2k14ini.asm 2k buffer size. first element at 1024, last element at 1023, two middles at 2047 and 0000 bipolar mode Works 16 or 64 clock frames. negative edge BCLKR negative BFSR pulse -0 data shifted 1' cable from counter to CONV at DUT 2' cable from counter to CLK at DUT *************************************************************************** .width 160 .length 110 .title “sineb0 BSP in auto buffer mode” .mmregs .setsect “.text”, 0x500,0 ;Set address .setsect “vectors”, 0x180,0 ;Set address .setsect “buffer”, 0x800,0 ;Set address .setsect “result”, 0x1800,0 ;Set address .text ;.text marks start: ;this label seems necessary ;Make sure /PWRDWN is low at J1-9 ;to turn off AC01 adc tim=#0fh prd=#0fh tcr = #10h tspc = #0h pmst = #01a0h sp = #0700h dp = #0 ar2 = #1800h ar3 = #0800h ar4 = #0h call sineinit sinepeek: call sineinit wait ; goto wait ; stop timer ; stop TDM serial port to AC01 ; set up iptr. Processor Mode STatus register ; init stack pointer. ; data page ; pointer to computed receive buffer. ; pointer to Buffered Serial Port receive buffer ; reset record counter ; Double clutch the initialization to insure a proper ; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. ————————Buffered Receive Interrupt Routine ————————— breceive: ifr = #10h ; clear interrupt flags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable ; ———————mask and shift input data —————————————— bufull: b = *ar3+ Vector Table for the ‘C54x DSKplus 10.Jul.96 BSP vectors and Debugger vectors TDM vectors just return *************************************************************************** The vectors in this table can be configured for processing external and internal software interrupts. The DSKplus debugger uses four interrupt vectors. These are RESET, TRAP2, INT2, and HPIINT. * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * All other vector locations are free to use. When programming always be sure the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally. ;Set address of BSP buffer for clearing ;Set address of result for clearing .title “Vector Table” .mmregs reset nmi goto #80h nop nop return_enable nop nop nop goto #88h nop nop .space 52*16 return_enable nop nop nop return_enable nop nop nop ;00; RESET * DO NOT MODIFY IF USING DEBUGGER * ;04; non-maskable external interrupt trap2 ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER * int0 ;0C-3F: vectors for software interrupts 18-30 ;40; external interrupt int0 int1 ;44; external interrupt int1 U 14031f W U U 17 LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO int2 return_enable nop nop nop return_enable nop nop nop goto breceive nop nop nop goto bsend nop nop nop return_enable nop nop nop return_enable nop nop return_enable nop nop nop dgoto #0e4h nop nop .space 24*16 ;48; external interrupt int2 tint ;4C; internal timer interrupt brint ;50; BSP receive interrupt bxint ;54; BSP transmit interrupt trint ;58; TDM receive interrupt txint int3 ;5C; TDM transmit interrupt ;60; external interrupt int3 hpiint ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER * ;68-7F; reserved area ********************************************************************** * (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 * ********************************************************************** * * * File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus * * for use with 1403 in buffered mode * * BSPC and SPC are the same in the ‘C542 * * BSPCE and SPCE seem the same in the ‘C542 * ********************************************************************** .title “Buffered Serial Port Initialization Routine” ON .set 1 OFF .set !ON YES .set 1 NO .set !YES BIT_8 .set 2 BIT_10 .set 1 BIT_12 .set 3 BIT_16 .set 0 GO .set 0x80 ********************************************************************** * This is an example of how to initialize the Buffered Serial Port (BSP). * The BSP is initialized to require an external CLK and FSX for * operation. The data format is 16-bits, burst mode, with autobuffering * enabled. * 18 U 14031f W U U LTC1403-1/LTC1403A-1 APPLICATIO S I FOR ATIO ***************************************************************************************************** *LTC1403 timing from board with 10MHz crystal. * *10MHz, divided from 40MHz, forced to CLKIN by 1403 board. * *Horizontal scale is 25ns/chr or 100ns period at BCLKR * *Timing measured at DSP pins. Jxx pin labels for jumper cable. * *BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~* *BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~* *BDR Pin J1-26 _—_—_——_—> 1)|((Format & 2)