LTBGX

LTC1407-1/LTC1407A-1 Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown FEATURES s s s s s s DESCRIPTIO s s s s s s 3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation ±1.25V Differential Input Range Pin Compatible 0V to 2.5V Input Range Version (LTC1407/LTC1407A) 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10µW) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection at 100kHz Tiny 10-Lead MS Package The LTC®1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps ADCs with two 1.5Msps simultaneously sampled differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MS package. A Sleep shutdown feature lowers power consumption to 10µW. The combination of speed, low power and tiny package makes the LTC1407-1/LTC1407A-1 suitable for high speed, portable applications. The LTC1407-1/LTC1407A-1 contain two separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal. These two sampled inputs are then converted at a rate of 1.5Msps per channel. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for CH0+, CH0–, CH1+ and CH1– extends from ground to the supply voltage. The serial interface sends out the two conversion results in 32 clocks for compatibility with standard serial interfaces. , LTC and LT are registered trademarks of Linear Technology Corporation. U.S. patent numbers 6084440, 6522187 APPLICATIO S s s s s s s Telecommunications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control I & Q Demodulation Industrial Radio BLOCK DIAGRA CH0+ 1 10µF 3V 7 VDD LTC1407A-1 14-BIT LATCH + S&H CH0– 2 – MUX 3Msps 14-BIT ADC 8 SDO THD, 2nd, 3rd (dB) CH1+ 4 + S&H 14-BIT LATCH THREESTATE SERIAL OUTPUT PORT CH1– 5 – VREF GND 2.5V REFERENCE 10 TIMING LOGIC 9 CONV 3 10µF 6 11 SCK EXPOSED PAD 1407A1 BD U THD, 2nd and 3rd vs Input Frequency for Differential Input Signals –44 –50 –56 –62 –68 –74 –80 –86 –92 –98 –104 0.1 1 FREQUENCY (MHz) 10 2nd THD 3rd 20 14071 G22 W U 14071f 1 LTC1407-1/LTC1407A-1 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW CH0 + CH0 – VREF CH1+ CH1– 1 2 3 4 5 10 9 8 7 6 CONV SCK SDO VDD GND 11 Supply Voltage (VDD) ................................................. 4V Analog Input Voltage (Note 3) ................................... – 0.3V to (VDD + 0.3V) Digital Input Voltage .................... – 0.3V to (VDD + 0.3V) Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 100mW Operation Temperature Range LTC1407C-1/LTC1407AC-1 ..................... 0°C to 70°C LTC1407I-1/LTC1407AI-1 .................. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 150°C/ W EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO PCB LTC1407CMSE-1 LTC1407IMSE-1 LTC1407ACMSE-1 LTC1407AIMSE-1 MSE PART MARKING LTBGT LTBGV LTBGW LTBGX Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Offset Match from CH0 to CH1 Gain Error Gain Match from CH0 to CH1 Gain Tempco The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V. CONDITIONS q LTC1407-1 MIN TYP MAX 12 –2 –10 –5 q q q LTC1407A-1 MIN TYP MAX 14 –4 –20 –10 –60 –10 ±0.5 ±2 ±1 ± 10 ±2 ± 15 ±1 4 20 10 60 10 UNITS Bits LSB LSB LSB LSB LSB ppm/°C ppm/°C (Notes 5, 17) (Notes 4, 17) (Note 17) (Notes 4, 17) (Note 17) Internal Reference (Note 4) External Reference ± 0.25 ±1 ±0.5 ±5 ±1 ± 15 ±1 2 10 5 30 5 –30 –5 A ALOG I PUT SYMBOL PARAMETER VIN VCM IIN CIN tACQ tAP tJITTER tSK CMRR The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V. CONDITIONS 2.7V ≤ VDD ≤ 3.3V MIN TYP –1.25 to 1.25 0 to VDD q MAX UNITS V V Analog Differential Input Range (Notes 3, 8, 9) Analog Common Mode + Differential Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Sample-and-Hold Aperture Skew from CH0 to CH1 Analog Input Common Mode Rejection Ratio 1 13 39 1 0.3 200 (Note 18) (Note 6) q fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V –60 –15 2 U µA pF ns ns ps ps dB dB 14071f W U U WW W U U U LTC1407-1/LTC1407A-1 DY A IC ACCURACY SYMBOL SINAD PARAMETER Signal-to-Noise Plus Distortion Ratio The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V. Single ended signal drive CH0+/CH1+ with CHO–/CH1– = 1.5V DC. Differential signals drive both inputs of each channel with VCM = 1.5V DC. CONDITIONS 100kHz Input Signal (Note 19) 750kHz Input Signal (Note 19) 100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V (Note 19) 750kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V (Note 19) 100kHz First 5 Harmonics (Note 19) 750kHz First 5 Harmonics (Note 19) 100kHz Input Signal (Note 19) 750kHz Input Signal (Note 19) 0.625VP-P 1.4MHz Summed with 0.625VP-P, 1.56MHz into CH0+ and Inverted into CHO–. Also Applicable to CH1+ and CH1– VREF = 2.5V (Note 17) VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15) S/(N + D) ≥ 68dB q THD SFDR IMD I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT = 0V, VDD = 3V VOUT = VDD = 3V CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V. MIN q q q U U U WU U LTC1407-1 MIN TYP MAX 68 70.5 70.5 72.0 72.0 –87 –83 –87 –83 –82 LTC1407A-1 MIN TYP MAX 70 73.5 73.5 76.3 76.3 –90 –86 –90 –86 –82 UNITS dB dB dB dB dB dB dB dB dB Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth q –77 –80 0.25 50 5 1 50 5 LSBRMS MHz MHz U TA = 25°C. VDD = 3V. MIN TYP 2.5 15 600 0.2 2 MAX UNITS V ppm/°C µV/V Ω ms VDD = 2.7V to 3.6V, VREF = 2.5V Load Current = 0.5mA TYP MAX 0.6 ± 10 UNITS V V µA pF V V V µA pF mA mA 14071f 2.4 5 VDD = 3V, IOUT = – 200µA VDD = 2.7V, IOUT = 160µA VDD = 2.7V, IOUT = 1.6mA VOUT = 0V to VDD q q q 2.5 2.9 0.05 0.10 1 20 15 0.4 ± 10 3 LTC1407-1/LTC1407A-1 POWER REQUIRE E TS SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V. CONDITIONS Active Mode, fSAMPLE = 1.5Msps Nap Mode Sleep Mode (LTC1407) Sleep Mode (LTC1407A) Active Mode with SCK in Fixed State (Hi or Lo) q q PD Power Dissipation The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V. SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 PARAMETER Maximum Sampling Frequency per Channel (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Clock Period Conversion Time Minimum Positive or Negative SCLK Pulse Width CONV to SCK Setup Time SCK Before CONV Minimum Positive or Negative CONV Pulse Width SCK to Sample Mode CONV to Hold Mode 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) Minimum Delay from SCK to Valid Bits 0 Through 11 SCK to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition CONDITIONS q q TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and range specifications apply for a single-ended CH0+ or CH1+ input with CH0 – or CH1– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between CH0+ and CH0 – or CH1+ and CH1–. Performance is specified with CHO– = 1.5V DC while driving CHO+ and with CH1– = 1.5V DC while driving CH1+. Note 9: The absolute voltage at CH0+, CH0 –, CH1+ and CH1– must be within this range. 4 UW MIN 2.7 TYP 4.7 1.1 2.0 2.0 12 MAX 3.6 7.0 1.5 15 10 UNITS V mA mA µA µA mW UW MIN 1.5 TYP MAX UNITS MHz ns ns SCLK cycles ns ns ns ns ns ns ns ns ns ns ms (Note 16) (Note 6) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Notes 6, 14) q 19.6 32 2 3 0 4 4 1.2 45 8 6 2 667 10000 34 2 Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 11: Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 32nd rising clock and it is ended by the rising edge of CONV. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops by 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock period. Note 17: The LTC1407A-1 is measured and specified with 14-bit Resolution (1LSB = 152µV) and the LTC1407-1 is measured and specified with 12-bit Resolution (1LSB = 610µV). Note 18: The sampling capacitor at each input accounts for 4.1pF of the input capacitance. Note 19: Full-scale sinewaves are fed into the noninverting inputs while the inverting inputs are kept at 1.5V DC. 14071f LTC1407-1/LTC1407A-1 TYPICAL PERFOR A CE CHARACTERISTICS ENOBs and SINAD vs Input Sinewave Frequency 12.0 11.5 11.0 ENOBs (BITS) VDD = 3V, TA = 25°C. Single ended signals drive +CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1) THD, 2nd and 3rd vs Input Frequency 74 71 68 65 62 59 56 53 1 10 FREQUENCY (MHz) 50 100 14071 G01 10.0 9.5 9.0 8.5 8.0 0.1 –74 –80 –86 –92 –98 –104 0.1 THD 3rd 2nd SFDR (dB) 100 14071 G02 10.5 THD, 2nd, 3rd (dB) SNR vs Input Frequency 74 71 68 12.0 11.5 11.0 ENOBs (BITS) SNR (dB) 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100 14071 G04 10.5 10.0 9.5 9.0 8.5 8.0 0.1 1 10 FREQUENCY (MHz) 65 62 59 56 53 50 100 14071 G21 THD, 2nd, 3rd (dB) SFDR vs Input Frequency for Differential Input Signals 104 98 92 MAGNITUDE (dB) MAGNITUDE (dB) 86 SFDR (dB) 80 74 68 62 56 50 44 0.1 1 10 FREQUENCY (MHz) 100 14071 G23 UW SFDR vs Input Frequency 104 98 92 86 80 74 68 62 56 50 –44 –50 –56 –62 –68 SINAD (dB) 1 10 FREQUENCY (MHz) 44 0.1 1 10 FREQUENCY (MHz) 100 14071 G03 ENOBs and SINAD vs Input Sinewave Frequency for Differential Input Signals 74 71 68 THD, 2nd and 3rd vs Input Frequency for Differential Input Signals –44 –50 –56 –62 –68 –74 –80 –86 –92 –98 –104 0.1 1 FREQUENCY (MHz) 10 2nd THD 3rd SINAD (dB) 20 14071 G22 98kHz Sine Wave 4096 Point FFT Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 100 200 300 400 500 FREQUENCY (kHz) 600 700 14071 G05 748kHz Sine Wave 4096 Point FFT Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 100 200 300 400 500 FREQUENCY (kHz) 600 700 14071 G06 14071f 5 LTC1407-1/LTC1407A-1 TYPICAL PERFOR A CE CHARACTERISTICS 1403kHz Input Summed with 1563kHz Input IMD 4096 Point FFT Plot for Differential Input Signals 0 –10 –20 –30 VDD = 3V, TA = 25°C. Single ended signals drive +CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1) 748kHz Sine Wave 4096 Point FFT Plot for Differential Input Signals 0 –10 –20 MAGNITUDE (dB) MAGNITUDE (dB) MAGNITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 100 200 300 400 500 FREQUENCY (kHz) 600 700 14071 G07 Differential Linearity for CH0 with Internal 2.5V Reference 1.0 0.8 4.0 3.2 DIFFERENTIAL LINEARITY (LSB) INTEGRAL LINEARITY (LSB) INTEGRAL LINEARITY (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 12288 8192 OUTPUT CODE 16384 14071 G08 Differential Linearity for CH1 with Internal 2.5V Reference 1.0 0.8 4.0 3.2 DIFFERENTIAL LINEARITY (LSB) INTEGRAL LINEARITY (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 12288 8192 OUTPUT CODE 16384 14071 G10 1.6 0.8 0 –0.8 –1.6 –2.4 –3.2 –4.0 0 4096 12288 8192 OUTPUT CODE 16384 14071 G11 INTEGRAL LINEARITY (LSB) 0.6 6 UW 10.7MHz Sine Wave 4096 Point FFT Plot for Differential Input Signals 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 185k 371k 556k FREQUENCY (Hz) 741k 14071 G24 0 185k 371k 556k FREQUENCY (Hz) 741k 14071 G25 Integral Linearity End Point Fit for CH0 with Internal 2.5V Reference 4.0 3.2 2.4 1.6 0.8 0 –0.8 –1.6 –2.4 –3.2 –4.0 0 4096 12288 8192 OUTPUT CODE 16384 14071 G09 Integral Linearity End Point Fit for CH0 with Internal 2.5V Reference for Differential Input Signals 2.4 1.6 0.8 0 –0.8 –1.6 –2.4 –3.2 –4.0 0 4096 12288 8192 OUTPUT CODE 16384 14071 G26 Integral Linearity End Point Fit for CH1 with Internal 2.5V Reference 4.0 3.2 2.4 1.6 0.8 0 –0.8 –1.6 –2.4 –3.2 –4.0 Integral Linearity End Point Fit for CH1 with Internal 2.5V Reference for Differential Input Signals 2.4 0 4096 12288 8192 OUTPUT CODE 16384 14071 G27 14071f LTC1407-1/LTC1407A-1 TYPICAL PERFOR A CE CHARACTERISTICS Differential and Integral Linearity vs Conversion Rate 8 7 6 5 4 3 2 1 0 –1 –2 –3 –4 2 2.25 2.5 2.75 3 3.25 3.5 3.75 CONVERSION RATE (MSPS) 4 MIN DNL MIN INL MAX DNL VDD = 3V, TA = 25°C. Single ended signals drive +CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1) SINAD vs Conversion Rate 78 77 76 MAX INL LINEARITY (LSB) S/(N+D) (dB) VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1) Full-Scale Signal Frequency Response 12 6 0 CMRR (dB) –6 –12 –18 –24 –30 –36 1M 10M 100M FREQUENCY (Hz) 1G 14071 G14 CROSSTALK (dB) AMPLITUDE (dB) Output Match with Simultaneous Input Steps at CH0 and CH1 from 25Ω 16384 14336 12288 OUTPUT CODE PSRR (dB) 10240 8192 6144 4096 2048 0 –5 0 5 CH0 AND CH1 FALLING 15 10 TIME (ns) 20 25 14071 G17 UW 75 74 73 72 71 70 69 68 2 EXTERNAL VREF = 3.3V, fIN ~ fS/3 EXTERNAL VREF = 3.3V, fIN ~ fS/40 INTERNAL VREF = 2.5V, fIN ~ fS/3 INTERNAL VREF = 2.5V, fIN ~ fS/40 2.5 3 3.5 CONVERSION RATE (Msps) 4 14071 G13 14071 G12 CMRR vs Frequency 0 –20 –40 –60 CH0 –80 –100 –120 100 CH1 –20 –30 –40 –50 –60 Crosstalk vs Frequency CH1 TO CH0 –70 CH0 TO CH1 –80 –90 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1k 10k 100k FREQUENCY (Hz) 1M 10M 14071 G16 14071 G15 PSSR vs Frequency –25 –30 –35 –40 CH0 AND CH1 RISING CH0 CH1 –45 –50 –55 –60 –65 –70 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 14071 G18 14071f 7 LTC1407-1/LTC1407A-1 TYPICAL PERFOR A CE CHARACTERISTICS Reference Voltage vs VDD 2.4902 2.4900 2.4898 2.4902 2.4900 2.4898 VREF (V) 2.4896 2.4894 2.4892 2.4890 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 14071 G19 VREF (V) PI FU CTIO S CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates fully differentially with respect to CH0–, with a –1.25V to 1.25V differential swing with respect to CH0– and a 0 to VDD absolute input range. CH0– (Pin 2): Inverting Channel 0. CH0– operates fully differentially with respect to CH0+, with a 1.25V to –1.25V differential swing with respect to CH0+ and a 0 to VDD absolute input range. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference voltage ≥ 2.55V and ≤ VDD. CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates fully differentially with respect to CH1–, with a –1.25V to 1.25V differential swing with respect to CH1– and a 0 to VDD absolute input range. CH1– (Pin 5): Inverting Channel 1. CH1– operates fully differentially with respect to CH1+, with a 1.25V to –1.25V differential swing with respect to CH1+ and a 0 to VDD absolute input range. GND (Pins 6, 11): Ground and Exposed Pad. This single ground pin and the Exposed Pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these connections. VDD (Pin 7): 3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND pin and solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum) in parallel with 0.1µF ceramic. Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-state Serial Data Output. Each pair of output data words represent the two analog input channels at the start of the previous conversion. The output format is 2’s complement. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. One or more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds the two analog input signals and starts the conversion on the rising edge. Two pulses with SCK in fixed high or fixed low state starts Nap mode. Four or more pulses with SCK in fixed high or fixed low state starts Sleep mode. 14071f 8 UW VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1) Reference Voltage vs Load Current 2.4896 2.4894 2.4892 2.4890 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 14071 G20 U U U LTC1407-1/LTC1407A-1 BLOCK DIAGRA S&H CH0– 2 – MUX 3Msps 14-BIT ADC 14-BIT LATCH CH0+ CH1+ 4 + S&H CH1– 5 – VREF GND 2.5V REFERENCE 14-BIT LATCH 10µF 6 11 W 10µF 3V 7 1 VDD LTC1407A-1 + THREESTATE SERIAL OUTPUT PORT 8 SDO 10 TIMING LOGIC 9 CONV 3 SCK EXPOSED PAD 1407A1 BD 14071f 9 LTC1407 Timing Diagram t7 9 14 31 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 1 t2 t1 5 6 7 8 t3 33 34 1 2 3 4 TI I G DIAGRA S t4 t5 CONV tACQ HOLD t9 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1 X* D11 12-BIT DATA WORD tCONV tTHROUGHPUT D10 D9 D8 D7 D6 D5 D4 X* Hi-Z D3 D2 D1 D0 X* X* Hi-Z 1407A1 TD01 t6 HOLD t8 INTERNAL S/H STATUS SAMPLE SAMPLE t9 HOLD LTC1407-1/LTC1407A-1 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 D9 12-BIT DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO Hi-Z D11 D10 *BITS MARKED “X” AFTER D0 SHOULD BE IGNORED LTC1407A Timing Diagram t1 5 14 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 t7 33 34 1 t2 t3 33 34 1 2 3 4 SCK t5 t4 CONV tACQ HOLD t9 Hi-Z D2 D1 D0 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1 D13 D12 D11 D10 D9 D8 D7 D6 14-BIT DATA WORD tCONV tTHROUGHPUT D5 D4 D3 D2 D1 D0 Hi-Z 1407A1 TD01 t6 HOLD t8 INTERNAL S/H STATUS SAMPLE SAMPLE t9 HOLD t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 D11 14-BIT DATA WORD D10 D9 D8 D7 D6 D5 D4 D3 SDO Hi-Z D13 D12 W SCK UW 10 14071f LTC1407-1/LTC1407A-1 TI I G DIAGRA S Nap Mode and Sleep Mode Waveforms SCK t1 CONV t1 NAP SLEEP t12 VREF 14071 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK t8 t10 SDO W UW SCK to SDO Delay SCK VIH VIH t9 VOH VOL 90% SDO 10% 14071 TD03 14071f 11 LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1407-1/ LTC1407A-1 are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the CH0– input is AC grounded at VCC/2). All four analog inputs of both differential analog input pairs, CH0+ with CH0– and CH1+ with CH1–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1407-1/LTC1407A-1 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind, while choosing an input amplifier, the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by 12 U increasing the time between conversions. The best choice for an op amp to drive the LTC1407-1/LTC1407A-1 depends on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1407-1/LTC1407A-1. (More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM.) LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter. LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies. Very high AVOL, 500µV offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ± 15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are – 93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/amplifier, 8.5nV/√Hz. LT1806/LT1807: 325MHz GBWP, –80dBc distortion at 5MHz, unity gain stable, rail-to-rail in and out, 10mA/amplifier, 3.5nV/√Hz. LT1810: 180MHz GBWP, –90dBc distortion at 5MHz, unity gain stable, rail-to-rail in and out, 15mA/amplifier, 16nV/√Hz. LinearView is a trademark of Linear Technology Corporation. 14071f W UU LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, –85dBc distortion at 1MHz, unity gain stable, rail-to-rail in and out, 15mA/amplifier, 0.95nV/√Hz. LT6203: 100MHz GBWP, –80dBc distortion at 1MHz, unity gain stable, rail-to-rail in and out, 3mA/amplifier, 1.9nV/√Hz. LT6600: Amplifier/Filter Differential In/Out with 10MHz Cutoff. INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1407-1/LTC1407A-1 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows a 47pF capacitor from CHO+ to ground and a 51Ω source resistor to limit the net input bandwidth to 30MHz. The 47pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components ANALOG INPUT VCM 1.5V DC 51Ω* 1 47pF* 2 CH0– LTC1407-1/ LTC1407A-1 VREF GND CH1+ CH0+ 3 10µF 11 ANALOG INPUT VCM 1.5V DC 51Ω* 4 47pF* 5 14071 F01 *TIGHT TOLERANCE REQUIRED TO AVOID APERTURE SKEW DEGRADATION C1, C2: FILM TYPE C3: COG TYPE C4: CERAMIC BYPASS Figure 1. RC Input Filter Figure 2. AC Coupling of AC Signals with 1kHz Low Cut 14071f + CH1– U can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency a multiple pole filter is required. High external source resistance, combined with 13pF of input capacitance, will reduce the rated 50MHz input bandwidth and increase acquisition time beyond 39ns. INPUT RANGE The analog inputs of the LTC1407-1/LTC1407A-1 may be driven fully differentially with a single supply. Either input may swing up to 3V, provided the differential swing is no greater than 1.25V. In the valid input range, each input of each channel is always up to ±1.25V away from the other input of each channel. The –1.25V to 1.25V range is also ideally suited for AC-coupled signals in single supply applications. Figure 2 shows how to AC couple signals in a single supply system without needing a mid-supply 1.5V DC external reference. The DC common mode level is supplied by the previous stage that is already bounded by single supply voltage of the system. The common mode range of the inputs extends from ground to the supply voltage VDD. If the difference between the CH0+ and CH0– inputs or the CH1+ and CH1– inputs exceeds 1.25V, the output code will stay fixed at zero and all ones, and if this difference goes below –1.25V, the ouput code will stay fixed at one and all zeros. C2 1µF LTC1407-1/ LTC1407A-1 CHO+ 2 CHO– 4.09V 3 VREF C4 C1 1µF 10µF 14071 F02 1 R3 51Ω VIN C3 56pF R2 1.6k R1 1.6k W UU 13 LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO INTERNAL REFERENCE The LTC1407-1/LTC1407A-1 have an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5V to obtain a precise ±1.25V input span. The reference amplifier output VREF, (Pin 3) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or a 10µF tantalum in parallel with a 0.1µF ceramic is recommended. The VREF pin can be overdriven with an external reference as shown in Figure 3. The voltage of the external reference must be higher than the 2.5V of the open-drain P-channel output of the internal reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will see a DC quiescent load of 0.75mA and as much as 3mA during conversion. 10µF 11 CMRR (dB) 3V REF 3 VREF LTC1407-1/ LTC1407A-1 GND 14071 F02 Figure 3 INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF (Pin 3) and the voltage at the Exposed Pad ground. The differential input range of ADC is –1.25V to 1.25V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference. DIFFERENTIAL INPUTS The ADC will always convert the bipolar difference of CH0+ minus CH0– or the bipolar difference of CH1+ minus CH1–, independent of the common mode voltage at either set of inputs. The common mode rejection holds up at high frequencies (see Figure 4). The only requirement is that both inputs not go below ground or exceed VDD. Integral nonlinearity errors (INL) and differential 2’s COMPLEMENT OUTPUT CODE 14 U nonlinearity errors (DNL) are largely independent of the common mode voltage. However, the offset error will vary. CMRR is typically better than 60dB. Figure 5 shows the ideal input/output characteristics for the LTC1407-1/LTC1407A-1. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is 2’s complement with 1LSB = 2.5V/16384 = 153µV for the LTC1407A-1 and 1LSB = 2.5V/4096 = 610µV for the LTC1407-1. The LTC1407A-1 has 1LSB RMS of Gaussian white noise. Figure 6a shows the LTC1819 converting a single ended input signal to differential input signals for optimum THD and SFDR performance as shown in the FFT plot (Figure 6b). 0 –20 –40 –60 CH0 –80 –100 –120 100 CH1 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 14071 G15 W UU Figure 4. CMRR vs Frequency 011...111 011...110 011...101 100...010 100...001 100...000 –FS INPUT VOLTAGE (V) 14071 F05 FS – 1LSB Figure 5. LTC1407-1/LTC1407A-1 Transfer Characteristic 14071f LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO 5V C5 0.1µF MAGNITUDE (dB) C3 1µF R4 499Ω R3 499Ω –5V C4 1µF U2 1/2 LT1819 Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially Board Layout and Bypassing Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1407-1/LTC1407A-1, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. If optimum phase match between the inputs is desired, the length of the four input wires of the two input channels should be kept matched. But each pair of input wires to the two input channels should be kept separated by a ground trace to avoid high frequency crosstalk between channels. High quality tantalum and ceramic bypass capacitors should be used at the VDD and VREF pins as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 10µF surface mount tantalum capacitor with a 0.1µF ceramic is recommended for the VDD and VREF pins. Alternatively, 10µF ceramic chip capacitors such as X5R or X7R may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. The VDD bypass capacitor returns to GND (Pin 6) and the VREF bypass capacitor returns to the Exposed Pad ground (Pin 11). Care should + VIN 1.25VP-P MAX U1 1/2 LT1819 C6 0.1µF R1 51Ω C1 47pF R5 1k 1.5VCM R6 1k R2 51Ω C2 47pF U 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 LTC1407A-1 +CH0 OR +CH1 W UU + – – –120 0 185k 371k 556k FREQUENCY (Hz) 741k 14031 F06b –CH0 OR –CH1 1407A F06a Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot with the LT1819 Driving the Inputs Differentially 1407-1 F07 Figure 7. Recommended Layout be taken to place the 0.1µF VDD bypass capacitor as close to Pins 6 and 7 as possible. Figure 7 shows the recommended system ground connections. All analog circuitry grounds should be terminated at 14071f 15 LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO the LTC1407-1/LTC1407A-1 Exposed Pad. The ground return from the LTC1407-1/LTC1407A-1 Pin 6 to the power supply should be low impedance for noise-free operation. The Exposed Pad of the 10-lead MSE package is also tied to Pin 6 and the LTC1407-1/LTC1407A-1 GND. The Exposed Pad should be soldered on the PC board to reduce ground connection inductance. Digital circuitry grounds must be connected to the digital supply common. POWER-DOWN MODES Upon power-up, the LTC1407-1/LTC1407A-1 are initialized to the active state and is ready for conversion. The Nap and Sleep mode waveforms show the power down modes for the LTC1407-1/LTC1407A-1. The SCK and CONV inputs control the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1407-1/LTC1407A-1 in Nap mode and the power drain drops from 14mW to 6mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1407-1/ LTC1407A-1 for service very quickly and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1407-1/LTC1407A-1 in Sleep mode and the power drain drops from 14mW to 10µW. One or more rising edges at SCK wake up the LTC1407-1/LTC1407A-1 for operation. The internal reference (VREF ) takes 2ms to slew and settle with a 10µF load. Using sleep mode more frequently compromises the settled accuracy of the internal reference. Note that for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. DIGITAL INTERFACE The LTC1407-1/LTC1407A-1 have a 3-wire SPI (Serial Protocol Interface) interface. The SCK and CONV inputs and SDO output implement this interface. The SCK and CONV inputs accept swings from 3V logic and are TTL compatible, if the logic swing does not exceed VDD. A detailed description of the three serial port signals follows: 16 U Conversion Start Input (CONV) The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC1407-1/ LTC1407A-1 until the following 32 SCK rising edges have occurred. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC1407-1/ LTC1407A-1 and then buffer this signal to drive the frame sync input of the processor serial port. It is good practice to drive the LTC1407-1/LTC1407A-1 CONV input first to avoid digital noise interference during the sample-to-hold transition triggered by CONV at the start of conversion. It is also good practice to keep the width of the low portion of the CONV signal greater than 15ns to avoid introducing glitches in the front end of the ADC just before the sampleand-hold goes into Hold mode at the rising edge of CONV. Minimizing Jitter on the CONV Input In high speed applications where high amplitude sinewaves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement easily. The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. As shown in the interface circuit examples, the SCK and CONV inputs should be driven first, with digital buffers used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter, even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10MHz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40MHz). The jitter in these PLL-generated high speed clocks can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP’s master clock. 14071f W UU LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK sends out two sets of 12/14 data bits, with the MSB sent first. A simple approach is to generate SCK to drive the LTC1407-1/ LTC1407A-1 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the Serial Data Output (SDO) into your processor serial port. The 14-bit Serial Data will be received right justified, in two 16-bit words with 32 or more clocks per frame sync. It is good practice to drive the LTC1407-1/LTC1407A-1 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. Serial Data Output (SDO) Upon power-up, the SDO output is automatically reset to the high impedance state. The SDO output remains in high impedance until a new conversion is started. SDO sends out two sets of 12/14 bits in 2’s complement format in the output data stream after the third rising edge of SCK after the start of conversion with the rising edge of CONV. The two 12-/14-bit words are separated by two clock cycles in high impedance mode. Please note the delay specification from SCK to a valid SDO. SDO is always guaranteed to be 3V VDD 7 10 CONV LTC1407-1/ LTC1407A-1 9 SCK SDO GND 8 6 CONV CLK 3-WIRE SERIAL INTERFACELINK B13 B12 0V TO 3V LOGIC SWING Figure 8. DSP Serial Interface to TMS320C54x U valid by the next rising edge of SCK. The 32-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. HARDWARE INTERFACE TO TMS320C54x The LTC1407-1/LTC1407A-1 are serial output ADCs whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 8 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC’s serial data can be collected in two alternating 1kB segments, in real time, at the full 3Msps conversion rate of the LTC1407-1/ LTC1407A-1. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1407-1/ LTC1407A-1 may be added to drive long tracks to the DSP to prevent corruption of the signal to LTC1407-1/ LTC1407A-1. This configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the DSP, may be needed to match the characteristic impedance of very long transmission lines. If you need to terminate the SDO transmission line, buffer it first with one or two 74ACxx gates. The TTL threshold inputs of the DSP port respond properly to the 3V swing used with the LTC1407-1/ LTC1407A-1. 5V VCC BFSR TMS320C54x BCLKR BDR 14071 F08 W UU 14071f 17 LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO ; ; ; ; ; ; ; ; ; ; ; 12-03-03 ****************************************************************** Files: 014SIAB.ASM -> 1407A Sine wave collection with Serial Port interface bvectors.asm both channels collected in sequence in the same 2k record. s2k14ini.asm Buffered mode 2k buffer size. First element at 1024, last element at 1023, two middles at 2047 and 0000 bipolar mode Works 16 or 64 clock frames. negative edge BCLKR negative BFSR pulse -0 data shifted *************************************************************************** .width 160 .length 110 .title “sineb0 BSP in auto buffer mode” .mmregs .setsect “.text”, 0x500,0 ;Set address .setsect “vectors”, 0x180,0 ;Set address .setsect “buffer”, 0x800,0 ;Set address .setsect “result”, 0x1800,0 ;Set address .text ;.text marks start: ;this label seems necessary ;Make sure /PWRDWN is low at J1-9 ;to turn off AC01 adc tim=#0fh prd=#0fh tcr = #10h tspc = #0h pmst = #01a0h sp = #0700h dp = #0 ar2 = #1800h ar3 = #0800h ar4 = #0h call sineinit sinepeek: call sineinit wait goto wait ; stop timer ; stop TDM serial port to AC01 ; set up iptr. Processor Mode STatus register ; init stack pointer. ; data page ; pointer to computed receive buffer. ; pointer to Buffered Serial Port receive buffer ; reset record counter ; Double clutch the initialization to insure a proper ; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. ; ————————Buffered Receive Interrupt Routine ————————— breceive: ifr = #10h ; clear interrupt flags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable 14071f 18 U of executable of incoming 1403 data of BSP buffer for clearing of result for clearing start of code W UU LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO ; bufull: b = *ar3+ Vector Table for the ‘C54x DSKplus 10.Jul.96 BSP vectors and Debugger vectors TDM vectors just return *************************************************************************** The vectors in this table can be configured for processing external and internal software interrupts. The DSKplus debugger uses four interrupt vectors. These are RESET, TRAP2, INT2, and HPIINT. * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * All other vector locations are free to use. When programming always be sure the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally. ;Set address of BSP buffer for clearing ;Set address of result for clearing U 14071f W UU 19 LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO .title “Vector Table” .mmregs reset goto #80h nop nop return_enable nop nop nop goto #88h nop nop .space 52*16 return_enable nop nop nop return_enable nop nop nop return_enable nop nop nop return_enable nop nop nop goto breceive nop nop nop goto bsend nop nop nop return_enable nop nop nop return_enable nop nop return_enable nop nop nop dgoto #0e4h nop nop ;00; RESET nmi ;04; non-maskable external interrupt trap2 ;08; trap2 int0 ;0C-3F: vectors for software interrupts 18-30 ;40; external interrupt int0 int1 ;44; external interrupt int1 int2 ;48; external interrupt int2 tint ;4C; internal timer interrupt brint ;50; BSP receive interrupt bxint ;54; BSP transmit interrupt trint ;58; TDM receive interrupt txint ;5C; TDM transmit interrupt int3 ;60; external interrupt int3 hpiint ;64; HPIint 20 U * DO NOT MODIFY IF USING DEBUGGER * * DO NOT MODIFY IF USING DEBUGGER * * DO NOT MODIFY IF USING DEBUGGER * 14071f W UU LTC1407-1/LTC1407A-1 APPLICATIO S I FOR ATIO .space 24*16 ;68-7F; reserved area ********************************************************************** * (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 * ********************************************************************** * * * File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus * * for use with 1407 in buffered mode * * BSPC and SPC are the same in the ‘C542 * * BSPCE and SPCE seem the same in the ‘C542 * ********************************************************************** .title “Buffered Serial Port Initialization Routine” ON .set 1 OFF .set !ON YES .set 1 NO .set !YES BIT_8 .set 2 BIT_10 .set 1 BIT_12 .set 3 BIT_16 .set 0 GO .set 0x80 ********************************************************************** * This is an example of how to initialize the Buffered Serial Port (BSP). * The BSP is initialized to require an external CLK and FSX for * operation. The data format is 16-bits, burst mode, with autobuffering * enabled. * ***************************************************************************************************** *LTC1407 timing from board with 10MHz crystal. * *10MHz, divided from 40MHz, forced to CLKIN by 1407 board. * *Horizontal scale is 25ns/chr or 100ns period at BCLKR * *Timing measured at DSP pins. Jxx pin labels for jumper cable. * *BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/ ~~~~~~~~~~~* *BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/ ~\_/~\_/~* *BDR Pin J1-26 _—_—_——_—> 1)|((Format & 2)