LTC1064-7CJ

LTC1064-7 Linear Phase, 8th Order Lowpass Filter FEATURES s s s s s DESCRIPTIO s s s Steeper Roll-Off Than 8th Order Bessel Filters fCUTOFF up to 100kHz Phase Equalized Filter in 14-Pin Package Phase and Group Delay Response Fully Tested Transient Response Exhibits 5% Overshoot and No Ringing Wide Dynamic Range 72dB THD or Better Throughout a 50kHz Passband No External Components Needed The LTC1064-7 is a clock-tunable monolithic 8th order lowpass filter with linear passband phase and flat group delay. The amplitude response approximates a maximally flat passband whilte it exhibits steeper roll-off than an equivalent 8th order Bessel filter. For instance, at twice the cutoff frequency the filter attains 34dB attenuation (vs 12dB for Bessel), while at three times the cutoff frequency the filter attains 68dB attenuation (vs 30dB for Bessel). The cutoff frequency of the LTC1064-7 is tuned via an external TTL or CMOS clock. The LTC1064-7 features wide dynamic range. With single 5V supply, the S/N + THD is 76dB. Optimum 92dB S/N is obtained with ±7.5V supplies. The clock-to-cutoff frequency ratio of the LTC1064-7 can be set to 50:1 (pin 10 to V +) or 100:1 (pin 10 to V –). When the filter operates at clock-to-cutoff frequency ratio of 50:1, the input is double-sampled to lower the risk of aliasing. The LTC1064-7 is pin-compatible with the LTC1064-X series, LTC1164-7 and LTC1264-7. APPLICATI s s s S Data Communication Filters Time Delay Networks Phase-Matched Filters TYPICAL APPLICATI 1 VIN 2 3 7.5V 4 5 6 7 LTC1064-7 80kHz Linear Phase Lowpass Filter 14 13 12 11 10 9 8 1064-7 TA01 –7.5V CLK = 4MHz VOUT NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A 0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT PIN AND THE fCLK LINE. 1V/DIV 7.5V VS = ± 7.5V fCLK = 4MHz RATIO = 50:1 U Eye Diagram 1µs/DIV 1064-7 TA02 UO UO 1 LTC1064-7 ABSOLUTE AXI U RATI GS Operating Temperature Range LTC1064-7C ....................................... – 40°C to 85°C LTC1064-7M .................................... – 55°C to 125°C Lead Temperature (Soldering, 10 sec)................. 300°C Total Supply Voltage (V + to V –) .......................... 16.5V Power Dissipation............................................. 400mW Burn-In Voltage ................................................... 16.5V Voltage at Any Input ..... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V) Storage Temperature Range ................ – 65°C to 150°C PACKAGE/ORDER I FOR ATIO TOP VIEW NC VIN GND V+ GND LP (A) INV (A) 1 2 3 4 5 6 7 14 RIN (A) 13 NC 12 V– ORDER PART NUMBER LTC1064-7CN LTC1064-7CJ LTC1064-7MJ 11 fCLK 10 50/100 9 8 VOUT NC J PACKAGE 14-LEAD CERAMIC DIP N PACKAGE 14-LEAD PLASTIC DIP TJMAX = 150°C, θJA = 65°C/W (J) TJMAX = 110°C, θJA = 65°C/W (N) ELECTRICAL CHARACTERISTICS PARAMETER Passband Gain Gain at 0.5 fCUTOFF (Note 4) Gain at 0.75 fCUTOFF (Note 1) Gain at fCUTOFF Gain at 2 fCUTOFF Gain with fCLK = 20kHz Gain with fCLK = 400kHz, VS = ± 2.375V Phase Factor (F ) Phase = 180° – F (f/fC) (Note 1) VS = ± 7.5V, RL = 10k, TA = 25°C, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz, TTL or CMOS level (maximum clock rise and fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified. CONDITIONS 0.1Hz ≤ f ≤ 0.25 fCUTOFF fTEST = 5kHz, (fCLK /fC) = 50:1 fTEST = 10kHz, (fCLK /fC) = 50:1 fTEST = 5kHz, (fCLK /f C) = 100:1 fTEST = 15kHz, (fCLK /fC) = 50:1 fTEST = 20kHz, (fCLK /fC) = 50:1 fTEST = 10kHz, (fCLK /fC) = 100:1 fTEST = 40kHz, (fCLK /fC) = 50:1 fTEST = 20kHz, (fCLK /fC) = 100:1 fTEST = 200Hz, (fCLK /fC) = 100:1 fTEST = 4kHz, (fCLK /fC) = 50:1 fTEST = 8kHz, (fCLK /fC) = 50:1 0.1Hz ≤ f ≤ fCUTOFF (fCLK /fC) = 50:1 (fCLK /fC) = 100:1 (fCLK /fC) = 50:1 (fCLK /fC) = 100:1 (fCLK /fC) = 50:1 (fCLK /fC) = 100:1 (fCLK /fC) = 50:1 (fCLK /fC) = 100:1 MIN q q q q q q q q Phase Nonlinearity (Notes 1, 3) 2 U U W WW U W TOP VIEW NC 1 VIN 2 GND 3 V+ 4 16 RIN (A) 15 NC 14 V – 13 NC 12 fCLK 11 50/100 10 NC 9 S PACKAGE 16-LEAD PLASTIC SOL TJMAX = 110°C, θJA = 85°C/W ORDER PART NUMBER LTC1064-7CS GND 5 NC 6 LP (A) 7 INV (A) 8 VOUT TYP 0.10 – 0.35 – 0.35 –1.0 – 3.4 – 4.5 – 34.0 – 34.5 – 4.3 – 0.3 – 3.3 430 ± 2.0 421 ± 2.5 430 421 ± 1.0 ± 1.0 MAX 0.65 0.15 1.25 – 0.35 – 2.50 – 3.75 – 31.75 – 31.75 – 3.5 0.25 – 2.00 UNITS dB dB dB dB dB dB dB dB dB dB dB Deg Deg Deg Deg % % % % – 0.60 – 0.90 – 1.30 – 2.0 – 4.50 – 5.75 – 36.5 – 37.0 – 6.5 – 0.9 – 4.5 q q 422 414 437 429 q q ± 2.0 ± 2.0 LTC1064-7 ELECTRICAL CHARACTERISTICS VS = ± 7.5V, RL = 10k, TA = 25°C, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz, TTL or CMOS level (maximum clock rise and fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified. PARAMETER Group Delay (t d) td = (F /360)(1/ fC) (Note 2) Group Delay Deviation (Notes 2, 3) CONDITIONS (fCLK /fC) = 50:1, f ≤ fCUTOFF (fCLK /fC) = 100:1, f ≤ fCUTOFF (fCLK /fC) = 50:1, f ≤ fCUTOFF (fCLK /fC) = 100:1, f ≤ fCUTOFF (fCLK /fC) = 50:1, f ≤ fCUTOFF (fCLK /fC) = 100:1, f ≤ fCUTOFF (fCLK /fC) = 50:1, f ≤ fCUTOFF (fCLK /fC) = 100:1, f ≤ fCUTOFF (fCLK /fC) = 50:1 (fCLK /fC) = 100:1 VS = 5V (AGND = 2V) VS = ± 5V VS = ± 7.5V 50:1 VS = ± 2.5V VS = ± 5V VS = ± 7.5V VS = ± 2.375V VS = ± 5V VS = ± 7.5V 50:1, VS = ± 5V 100:1, VS = ± 5V 50:1, VS = ± 5V 100:1, VS = ± 5V VS = ± 2.375V, TA = 25°C VS = ± 5V, TA = 25°C q MIN q q 58.6 115.0 TYP 59.7 ± 0.5 117.0 ± 1.0 59.7 117.0 ± 1.0 ± 1.0 MAX 60.7 119.0 q q ± 2.0 ± 2.0 Input Frequency Range (Table 9) Maximum fCLK Clock Feedthrough (f ≥ fCLK) Wideband Noise (1Hz ≤ f ≤ fCLK) Input Impedance Output DC Voltage Swing (Note 5) Output DC Offset Output DC Offset TempCo Power Supply Current q q 25 ± 1.0 ± 2.1 ± 3.0 80kHz) 2.7VRMS (fIN > 80kHz) 1.4VRMS (fIN > 500kHz) 1.6VRMS (fIN > 80kHz) 0.7VRMS (fIN > 400kHz) 0.5VRMS (fIN > 250kHz) ± 5V Single 5V Table 10. Transient Response of LTC Lowpass Filters DELAY RISE SETTLING TIME* TIME** TIME*** LOWPASS FILTER (SEC) (SEC) (SEC) LTC1064-3 Bessel 0.50/fC 0.34/fC 0.80/fC LTC1164-5 Bessel 0.43/fC 0.34/fC 0.85/fC LTC1164-6 Bessel 0.43/fC 0.34/fC 1.15/fC LTC1264-7 Linear Phase 1.15/fC 0.36/fC 2.05/fC LTC1164-7 Linear Phase 1.20/fC 0.39/fC 2.2/fC LTC1064-7 Linear Phase 1.20/fC 0.39/fC 2.2/fC LTC1164-5 Butterworth 0.80/fC 0.48/fC 2.4/fC LTC1164-6 Elliptic 0.85/fC 0.54/fC 4.3/fC LTC1064-4 Elliptic 0.90/fC 0.54/fC 4.5/fC LTC1064-1 Elliptic 0.85/fC 0.54/fC 6.5/fC * To 50% ± 5%, ** 10% to 90% ± 5%, *** To 1% ± 0.5% OVERSHOOT (%) 0.5 0 1 5 5 5 11 18 20 20 ts INPUT 90% OUTPUT Table 11. Aliasing (fCLK = 100kHz) INPUT FREQUENCY (VIN = 1VRMS, fIN = fCLK ± fOUT) (kHz) 50:1, fCUTOFF = 2kHz 190 (or 210) 195 (or 205) 196 (or 204) 197 (or 203) 198 (or 202) 199.5 (or 200.5) 100:1, fCUTOFF = 1kHz 97 (or 103) 97.5 (or 102.5) 98 (or 102) 98.5 (or 101.5) 99 (or 101) 99.5 (or 100.5) OUTPUT LEVEL (Relative to Input, 0dB = 1VRMS) (dB) –76.1 – 51.9 – 36.3 – 18.4 – 3.0 – 0.2 –74.2 – 53.2 – 36.9 – 19.6 – 5.2 – 0.7 OUTPUT FREQUENCY (Aliased Frequency fOUT = ABS [fCLK ± fIN]) (kHz) 10.0 5.0 4.0 3.0 2.0 0.5 3.0 2.5 2.0 1.5 1.0 0.5 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Transient Response 50µs/DIV VS = ± 7.5V, fIN = 2kHz ± 3V fCLK = 1MHz, RATIO = 50:1 1064-7 F05 W U UO Figure 5. 50% td 10% tr RISE TIME (tr) = 0.39 ±5% fCUTOFF 2.2 SETTLING TIME (ts) = ±5% f (TO 1% of OUTPUT) CUTOFF 1.2 DELAY TIME (td) = GROUP DELAY ≈ fCUTOFF (TO 50% OF OUTPUT) 1064-7 F06 Figure 6. Aliasing Aliasing is an inherent phenomenon of sampled data systems and it occurs when input frequencies close to the sampling frequency are applied. For the LTC1064-7 case at 100:1, an input signal whose frequency is in the range of fCLK ± 3%, will be aliased back into the filter’s passband. If, for instance, an LTC1064-7 operating with a 100kHz clock and 1kHz cutoff frequency receives a 98kHz, 10mV input signal, a 2kHz, 143µVRMS alias signal will appear at its output. When the LTC1064-7 operates with a clock-tocutoff frequency of 50:1, aliasing occurs at twice the clock frequency. Table 11 shows details. 11 LTC1064-7 PACKAGE DESCRIPTIO 0.290 – 0.320 (7.366 – 8.128) 0.008 – 0.018 (0.203 – 0.460) 0.385 ± 0.025 (9.779 ± 0.635) 0° – 15° 0.038 – 0.068 (0.965 – 1.727) 0.014 – 0.026 (0.360 – 0.660) 0.300 – 0.325 (7.620 – 8.255) 0.015 (0.380) MIN 0.130 ± 0.005 (3.302 ± 0.127) 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 +0.635 8.255 –0.381 ( ) 0.075 ± 0.015 (1.905 ± 0.381) 0.291 – 0.299 (7.391 – 7.595) 0.005 (0.127) RAD MIN 0.010 – 0.029 × 45° (0.254 – 0.737) 0° – 8° TYP SEE NOTE 0.009 – 0.013 (0.229 – 0.330) 0.050 (1.270) TYP 0.004 – 0.012 (0.102 – 0.305) 0.394 – 0.419 (10.007 – 10.643) SEE NOTE 0.016 – 0.050 (0.406 – 1.270) NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 U Dimensions in inches (millimeters) unless otherwise noted. J Package 14-Lead Ceramic DIP 0.785 (19.939) MAX 14 13 12 11 10 9 8 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0.005 (0.127) MIN 0.025 (0.635) RAD TYP 0.220 – 0.310 (5.588 – 7.874) 1 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN 0.098 (2.489) MAX 2 3 4 5 6 7 J14 0392 N Package 14-Lead Plastic DIP 0.065 (1.651) TYP 14 13 12 0.770 (19.558) MAX 11 10 9 8 0.045 – 0.065 (1.143 – 1.651) 0.260 ± 0.010 (6.604 ± 0.254) 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 1 0.125 (3.175) MIN 2 3 4 5 6 7 N14 0392 S Package 16-Lead Plastic SOL 0.398 – 0.413 (10.109 – 10.490) 16 0.093 – 0.104 (2.362 – 2.642) 0.037 – 0.045 (0.940 – 1.143) 15 14 13 12 11 10 9 0.014 – 0.019 (0.356 – 0.482) TYP 1 2 3 4 5 6 7 8 SOL16 0392 LT/GP 1292 10K REV 0 © LINEAR TECHNOLOGY CORPORATION 1992