LTC1067IGN

LTC1067/LTC1067-50 Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block FEATURES s s s s s DESCRIPTION The LTC ®1067/LTC1067-50 consist of two identical railto-rail, high accuracy and very wide dynamic range 2nd order switched-capacitor building blocks. Each building block, together with three to five resistors, provides 2nd order filter functions such as bandpass, highpass, lowpass, notch and allpass. High precision 4th order filters are easily designed. The center frequency of each 2nd order section is tuned by the external clock frequency. The internal clock-to-center frequency ratio (100:1 for the LTC1067 and 50:1 for the LTC1067-50) can be modified by the external resistors. These devices have a double sampled architecture which places aliasing and imaging components at twice the clock frequency. The LTC1067-50 is a low power device consuming about one half the current of the LTC1067. The LTC1067-50’s typical supply current is about 1mA from a 3.3V supply. The LTC1067 and LTC1067-50 are available in 16-pin narrow SSOP and SO packages. Mask programmable versions of the LTC1067 and LTC1067-50, with thin film resistors on-chip and custom clock-to-cutoff frequency ratios, can be designed in an SO-8 package to realize application specific monolithic filters. Please contact LTC Marketing for more details. s s s s Rail-to-Rail Input and Output Operation Operates from a Single 3V to ± 5V Supply Dual 2nd Order Filter in a 16-Lead SSOP Package > 80dB Dynamic Range on Single 3.3V Supply Clock-to-Center Frequency Ratio of 100:1 for the LTC1067 and 50:1 for the LTC1067-50 Internal Sampling-to-Center Frequency Ratio of 200:1 for the LTC1067 and 100:1 for the LTC1067-50 Center Frequency Error < ± 0.2% Typ Low Noise: < 40µVRMS, Q ≤ 5 Customizable with Internal Resistors APPLICATIONS s s s s Notch Filters Narrowband Bandpass Filters Tone Detection Noise Reduction Systems , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION Single 3.3V Supply Rail-to-Rail, 4th Order, 10kHz Bandpass Filter 1 2 3.3V 0.1µF 3 4 5 R31, 200k R21, 10k R11 200k IN 6 7 8 V+ NC V+ SA CLK AGND 16 15 1µF fCLK = 500kHz 0 –10 GAIN (dB) 14 V– 13 SB –20 LTC1067-50 12 LPA LPB BPA HPA/NA INV A BPB HPB/NB INV B 11 10 9 R32, 200k OUT –30 R22, 10k –40 TOTAL OUTPUT NOISE: 90µVRMS S/N RATIO: 80dB 1067 TA01 RB1, 200k 8 U U U Frequency Response 9 10 FREQUENCY (kHz) 11 12 1067 • TA02 1 LTC1067/LTC1067-50 ABSOLUTE MAXIMUM RATINGS Total Voltage Supply (V + to .............................. 12V Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V) Output Short-Circuit Duration .......................... Indefinite Power Dissipation............................................... 500mV Operating Temperature Range LTC1067C................................................ 0°C to 70°C LTC1067I............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C V –) PACKAGE/ORDER INFORMATION TOP VIEW V+ 1 16 CLK 15 AGND 14 V – 13 SB 12 LPB 11 BPB 10 HPB/NB 9 INV B ORDER PART NUMBER LTC1067CGN LTC1067-50CGN LTC1067IGN LTC1067-50IGN LTC1067CS LTC1067-50CS LTC1067IS LTC1067-50IS NC 2 V+ 3 SA 4 LPA 5 BPA 6 HPA/NA 7 INV A 8 GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO TJMAX = 110°C, θJA = 135°C/ W (GN) TJMAX = 110°C, θJA = 115°C/ W (S) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS PARAMETER Operating Supply Range Positive Output Voltage Swing CONDITIONS VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = ± 5V, RL = 10k VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = ± 5V, RL = 10k VS = 3V VS = 4.75V VS = ± 5V RL = 10k RL = 10k RL = 10k LTC1067 (internal op amps) VS = 4.75V, TA = 25°C, unless otherwise noted. MIN 3 2.65 4.25 4.15 TYP 2.80 4.50 4.50 0.020 0.025 – 4.96 16/1.0 33/2.2 70/7.2 90 2.8 2.25 MAX 11 UNITS V V V V V V V mA mA mA dB MHz V/µs q q q q q q Negative Output Voltage Swing 0.200 0.225 – 4.80 Output Short-Circuit Current (Source/Sink) DC Open-Loop Gain GBW Product Slew Rate LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25°C, unless otherwise noted. PARAMETER Center Frequency Range, fO (Note 1) Input Frequency Range Clock-to-Center Frequency, fCLK/fO CONDITIONS MIN TYP 0.001 to 20 0 to 1 100:1 ± 0.2 100:1 ± 0.2 q MAX Clock-to-Center Frequency Ratio, Side-to-Side Matching VS = 3V, fCLK = 250kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 4.75V, fCLK = 250kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = ± 5V, fCLK = 500kHz, Mode 1, fO = 5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 3V, fCLK = 250kHz, Q = 5 VS = 4.75V, fCLK = 250kHz, Q = 5 VS = ± 5V, fCLK = 500kHz, Q = 5 q ± 0.70 ± 0.70 ± 0.70 ± 0.35 ± 0.35 ± 0.35 100:1 ± 0.2 q q q q ± 0.1 ± 0.1 ± 0.1 UNITS kHz MHz % % % % % % % % % 2 U W U U WW W LTC1067/LTC1067-50 LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25°C, unless otherwise noted. PARAMETER Q Accuracy CONDITIONS VS = 3V, fCLK = 250kHz, Q = 5 VS = 4.75V, fCLK = 250kHz, Q = 5 VS = ± 5V, fCLK = 500kHz, Q = 5 MIN q q q ELECTRICAL CHARACTERISTICS fO Temperature Coefficient Q Temperature Coefficient DC Offset Voltage (See Table 2) VOS1 (DC Offset of Input Inverter) VOS2 (DC Offset of First Integrator) VOS3 (DC Offset of Second Integrator) Q < 2.5, VS = ± 5V VS = 3V, fCLK = 250kHz VS = 4.75V, fCLK = 250kHz VS = ± 5V, fCLK = 500kHz q q q Clock Feedthrough Maximum Clock Frequency Power Supply Current q q q TYP ± 0.5 ± 0.5 ± 0.5 ±1 ±5 ±3 ±4 ±4 150 2.0 2.50 3.00 4.35 MAX ±2 ±2 ±2 ± 12.5 ± 15.0 ± 15.0 4.5 5.5 7.5 UNITS % % % ppm/°C ppm/°C mV mV mV µVRMS MHz mA mA mA LTC1067-50 (internal op amps) VS = 4.75V, TA = 25°C, unless otherwise noted. PARAMETER Operating Supply Range Positive Output Voltage Swing CONDITIONS VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = ± 5V, RL = 10k VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = ± 5V, RL = 10k VS = 3V VS = 4.75V VS = ± 5V RL = 10k RL = 10k RL = 10k q q q q q q MIN 2.7 2.65 4.25 4.15 TYP 2.80 4.50 4.50 0.020 0.025 – 4.96 16/0.6 33/1.2 70/5.7 90 1.9 0.8 MAX 11 Negative Output Voltage Swing 0.200 0.225 – 4.80 Output Short-Circuit Current (Source/Sink) DC Open-Loop Gain GBW Product Slew Rate UNITS V V V V V V V mA mA mA dB MHz V/µs LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25°C, unless otherwise noted. PARAMETER Center Frequency Range, fO (Note 1) Input Frequency Range Clock-to-Center Frequency, fCLK/fO CONDITIONS MIN TYP 0.001 to 40 0 to 1 50:1 ± 0.2 50:1 ± 0.2 q MAX Clock-to-Center Frequency Ratio, Side-to-Side Matching Q Accuracy VS = 3V, fCLK = 125kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 4.75V, fCLK = 125kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = ± 5V, fCLK = 250kHz, Mode 1, fO = 5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 3V, fCLK = 125kHz, Q = 5 VS = 4.75V, fCLK = 125kHz, Q = 5 VS = ± 5V, fCLK = 250kHz, Q = 5 VS = 3V, fCLK = 125kHz, Q = 5 VS = 4.75V, fCLK = 125kHz, Q = 5 VS = ± 5V, fCLK = 250kHz, Q = 5 q ± 0.75 ± 0.75 ± 0.75 ± 0.55 ± 0.55 ± 0.55 ±2 ±2 ±2 50:1 ± 0.3 q q q q q q q ± 0.2 ± 0.2 ± 0.2 ± 0.5 ± 0.5 ± 0.5 UNITS kHz MHz % % % % % % % % % % % % 3 LTC1067/LTC1067-50 LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25°C, unless otherwise noted. PARAMETER fO Temperature Coefficient Q Temperature Coefficient DC Offset Voltage (See Table 2) CONDITIONS MIN TYP ±1 ±5 ±3 ±4 ±4 150 2.0 1.00 1.45 2.35 MAX UNITS ppm/°C ppm/°C mV mV mV µVRMS MHz mA mA mA ELECTRICAL CHARACTERISTICS VOS1 (DC Offset of Input Inverter) VOS2 (DC Offset of First Integrator) VOS3 (DC Offset of Second Integrator) Q < 2.5, VS = ± 5V VS = 3V, fCLK = 125kHz VS = 4.75V, fCLK = 125kHz VS = ± 5V, fCLK = 250kHz q q q ± 12.5 ± 15.0 ± 15.0 Clock Feedthrough Maximum Clock Frequency Power Supply Current q q q 2.5 3.0 4.0 The q denotes the specifications which apply over the full operating temperature range. Note 1: See Typical Performance Characteristics. TYPICAL PERFORMANCE CHARACTERISTICS LTC1067 Maximum Q vs Center Frequency (Modes 1, 1B, 2 where R4 ≥ 10R2) 50 VS = ± 5V fCLK(MAX) = 2MHz VS = 5V fCLK(MAX) = 1.5MHz 30 VS = 3.3V fCLK(MAX) = 1MHz 20 (NOISE + THD)/SIGNAL (dB) 40 MAXIMUM Q MAXIMUM Q 10 0 0 10 5 15 CENTER FREQUENCY, fO (kHz) LTC1067 Noise + THD vs Input Voltage –20 –30 (NOISE + THD)/SIGNAL (dB) (NOISE + THD)/SIGNAL (dB) –40 –50 –60 –70 –80 –90 –100 0.1 –40 –50 –60 –70 –80 –90 (NOISE + THD)/SIGNAL (dB) 4TH ORDER BUTTERWORTH LPF VS = SINGLE 5V, fIN = 1kHz fCLK = 500kHz, f–3dB = 5kHz RL = 20k MODE 1 MODE 3 1 INPUT VOLTAGE (VRMS) 4 UW 1067 G01 LTC1067 Maximum Q vs Center Frequency (Modes 2 where R4 < 10R2, 3) 50 VS = ± 5V fCLK(MAX) = 2MHz VS = 5V fCLK(MAX) = 1.5MHz VS = 3.3V fCLK(MAX) = 1MHz LTC1067 Noise + THD vs Input Voltage –20 –30 –40 –50 –60 –70 –80 –90 MODE 1 MODE 3 4TH ORDER BUTTERWORTH LPF VS = SINGLE 3.3V, fIN = 1kHz fCLK = 400kHz, f–3dB = 4kHz RL = 20k 40 30 20 10 0 20 0 10 5 15 CENTER FREQUENCY, fO (kHz) 20 1067 G02 –100 0.1 1 INPUT VOLTAGE (VRMS) 2 1067 G03 LTC1067 Noise + THD vs Input Voltage –20 –30 4TH ORDER BUTTERWORTH LPF VS = ± 5V, fIN = 1kHz fCLK = 500kHz, f–3dB = 5kHz RL = 20k LTC1067 Noise + THD vs Input Frequency –60 –65 –70 –75 –80 –85 –90 MODE 1 MODE 2 MODE 1 MODE 3 1 INPUT VOLTAGE (VRMS) 5 1067 G05 MODE 3 4TH ORDER BUTTERWORTH LPF VS = SINGLE 3.3V fCLK = 400kHz, VIN = 0.36VRMS f–3dB = 4kHz, RL = 20k 2 3 INPUT FREQUENCY (kHz) 4 5 2 1067 G04 –100 0.1 1 1067 G06 LTC1067/LTC1067-50 TYPICAL PERFORMANCE CHARACTERISTICS LTC1067 Noise + THD vs Input Frequency –75 –75 4TH ORDER LOWPASS BUTTERWORTH VS = ± 5V, VIN = 1VRMS fCLK = 1MHz, f–3dB = 10kHz RL = 20k (NOISE + THD)/SIGNAL (dB) MODE 1 –80 (NOISE + THD)/SIGNAL (dB) NOISE (µVRMS) MODE 3 –85 4TH ORDER BUTTERWORTH LPF VS = SINGLE 5V, fCLK = 500kHz VIN = 0.5VRMS, f–3dB = 5kHz, RL = 20k –90 1 3 2 INPUT FREQUENCY (kHz) 4 5 LTC1067 Output Voltage Swing vs Load Resistance, ± 5V Supply Voltage 10.0 9.8 VS = ± 5V OUTPUT VOLTAGE SWING (VP-P) OUTPUT VOLTAGE SWING (VP-P) 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 0 2 4 6 8 10 12 14 16 18 20 LOAD RESISTANCE (kΩ TO GND) 1067 G10 POWER SUPPLY CURRENT (mA) LTC1067-50 Maximum Q vs Center Frequency (Modes 2 Where R4 < 10R2, 3) 50 VS = ± 5V fCLK(MAX) = 2MHz MAXIMUM Q (NOISE + THD)/SIGNAL (dB) 40 MAXIMUM Q VS = 5V fCLK(MAX) = 1.5MHz 30 VS = 3.3V fCLK(MAX) = 800kHz VS = 3V fCLK(MAX) = 600kHz 20 10 0 0 20 10 30 CENTER FREQUENCY, fO (kHz) UW 1067 G07 LTC1067 Noise + THD vs Input Frequency 220 200 180 160 140 120 100 80 60 40 20 –90 1 3 2 4 5 6 7 8 9 10 INPUT FREQUENCY (MHz) 1067 G08 LTC1067 Noise vs Q ± 5V –80 5V 3V MODE 1 –85 MODE 3 0 0 10 20 Q 30 40 50 1067 G09 LTC1067 Output Voltage Swing vs Load Resistance, Single Supply Voltage 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 2 4 6 8 10 12 14 16 18 20 1067 G11 LTC1067 Power Supply Current vs Power Supply 4.5 4.0 3.5 3.0 –20°C 2.5 2.0 1.5 0 3 4 25°C 70°C VS = 5V VS = 3.3V LOAD RESISTANCE (kΩ TO V –) 7 9 6 8 5 TOTAL POWER SUPPLY (V) 10 1067 G12 LTC1067-50 Maximum Q vs Center Frequency (Modes 1, 1B, 2 Where R4 ≥ 10R2) 50 VS = ± 5V fCLK(MAX) = 2MHz VS = 5V fCLK(MAX) = 1.5MHz VS = 3.3V fCLK(MAX) = 800kHz 20 VS = 3V fCLK(MAX) = 600kHz LTC1067-50 Noise + THD vs Input Voltage –20 –30 –40 –50 –60 –70 –80 –90 MODE 1 MODE 3 4TH ORDER BUTTERWORTH LPF VS = SINGLE 3V, fIN = 1kHz fCLK = 200kHz, f–3dB = 4kHz 40 30 10 0 40 1067 G13 0 20 10 30 CENTER FREQUENCY, fO (kHz) 40 1067 G14 –100 0.1 1 INPUT VOLTAGE (VRMS) 2 1067 G15 5 LTC1067/LTC1067-50 TYPICAL PERFORMANCE CHARACTERISTICS LTC1067-50 Noise + THD vs Input Voltage –20 –30 4TH ORDER BUTTERWORTH LPF VS = SINGLE 5V, fIN = 1kHz fCLK = 250kHz, f–3dB = 5kHz RL = 20k –20 –30 (NOISE + THD)/SIGNAL (dB) (NOISE + THD)/SIGNAL (dB) –40 –50 –60 –70 –40 –50 –60 –70 –80 (NOISE + THD)/SIGNAL (dB) MODE 1 –80 –90 –100 0.1 MODE 3 1 INPUT VOLTAGE (VRMS) 2 1067 G16 LTC1067-50 Noise + THD vs Input Frequency –60 –65 4TH ORDER BUTTERWORTH LPF VS = SINGLE 5V, fCLK = 250kHz VIN = 0.5VRMS, f–3dB = 5kHz, RL = 20k –60 –65 (NOISE + THD)/SIGNAL (dB) (NOISE + THD)/SIGNAL (dB) NOISE (µVRMS) –70 –75 –80 –85 –90 MODE 1 MODE 3 1 3 2 INPUT FREQUENCY (kHz) LTC1067-50 Output Voltage Swing vs Load Resistance, ±5V Supply Voltage 10.0 9.8 VS = ± 5V OUTPUT VOLTAGE SWING (VP-P) OUTPUT VOLTAGE SWING (VP-P) 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 0 2 4 6 8 10 12 14 16 18 20 LOAD RESISTANCE (kΩ TO GND) 1067 G22 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 2 4 6 8 10 12 14 16 18 20 1067 G23 POWER SUPPLY CURRENT (mA) 6 UW 4 5 1067 G19 LTC1067-50 Noise + THD vs Input Voltage –60 LTC1067-50 Noise + THD vs Input Frequency MODE 1 –65 –70 –75 –80 –85 –90 4TH ORDER BUTTERWORTH LPF VS = SINGLE 3V, fCLK = 200kHz VIN = 0.34VRMS, f–3dB = 4kHz, RL = 20k 1 3 2 INPUT FREQUENCY (kHz) 4 5 4TH ORDER BUTTERWORTH LPF VS = ± 5V, fIN = 1kHz fCLK = 250kHz (225kHz FOR MODE 2) f–3dB = 10kHz, RL = 20k MODE 3 MODE 3 MODE 2 MODE 1 –90 –100 0.1 1 INPUT VOLTAGE (VRMS) 5 1067 G17 1067 G18 LTC1067-50 Noise + THD vs Input Frequency 400 LTC1067-50 Noise vs Q 350 ± 5V 300 250 200 150 100 3V 5V 4TH ORDER BUTTERWORTH LPF VS = ± 5V, fCLK = 250kHz VIN = 1VRMS, f–3dB = 5kHz RL = 20k –70 MODE 1 –75 MODE 3 –80 –85 –90 50 0 1 3 2 INPUT FREQUENCY (kHz) 4 5 0 5 10 15 20 25 30 35 40 45 50 Q 1067 G21 1067 G20 LTC1067-50 Output Voltage Swing vs Load Resistance, Single Supply Voltage 5.0 4.5 VS = 5V 2.2 2.0 1.8 LTC1067-50 Power Supply Current vs Power Supply 70°C 1.6 1.4 1.2 1.0 0.8 3 4 VS = 3V 20°C 25°C LOAD RESISTANCE (kΩ TO V –) 7 9 6 8 5 TOTAL POWER SUPPLY (V) 10 1067 G24 LTC1067/LTC1067-50 TYPICAL PERFORMANCE CHARACTERISTICS LTC1067/LTC1067-50 Mode 1B Noise Increase vs R5/R6 Ratio 2.0 RELATIVE NOISE INCREASE (REFERENCE NOISE WHEN R5/R6 = 0.02) RELATIVE NOISE INCREASE (REFERENCE NOISE WHEN R2/R4 = 1) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 0.5 1.0 1.5 2.0 2.5 R5/R6 RATIO 3.0 3.5 PIN FUNCTIONS V +, V – (Pins 1, 3,14): The V + (Pins 1, 3) and the V – (Pin 14) should each be bypassed with a 0.1µF capacitor to an adequate analog ground. The filter’s power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-tonoise ratio of the filter. The supply’s power-up slew rate should be less than 1V/µs. When V + is applied before V –, and V – is allowed to go above ground, a diode should clamp V – to prevent latch-up. Figures 1 and 2 show typical connections for dual and single supply operation. 1 2 V+ 0.1µF 3 4 5 6 7 8 V+ NC V+ SA LPA BPA HPA/NA INV A LTC1067 LTC1067-50 STAR SYSTEM GROUND Figure 1. Dual Supply Ground Plane Connections UW CLK AGND V– SB LPB BPB HPB/NB INV B 9 DIGITAL GROUND PLANE LTC1067/LTC1067-50 Mode 3 Noise Increase vs R2/R4 Ratio 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.2 0.3 0.4 0.5 0.6 0.7 R2/R4 RATIO 0.8 0.9 1.0 1067 G25 1067 G26 U U U 16 15 14 13 12 11 10 V– 0.1µF 1 2 V+ 0.1µF 3 4 5 6 7 8 V+ NC V+ SA LPA BPA HPA/NA INV A LTC1067 LTC1067-50 CLK AGND V– SB LPB BPB HPB/NB INV B 16 15 14 13 12 11 10 9 1µF 200Ω CLOCK SOURCE 1067 F01 STAR SYSTEM GROUND DIGITAL GROUND PLANE 200Ω CLOCK SOURCE 1067 F02 FOR MODE 3, THE SA AND SB SUMMING NODE PINS ARE TIED TO THE AGND PIN Figure 2. Single Supply Ground Plane Connections 7 LTC1067/LTC1067-50 PIN FUNCTIONS SA, SB (Pins 4, 13): Summing Inputs. The summing pins’ connection, along with the other resistor connections, determine the circuit topology (mode) of each 2nd order section. These pins should never be left floating. LPA, BPA, HPA/NA, HPB/NB, BPB, LPB (Pins 5, 6, 7, 10, 11, 12): Output Pins. Each 2nd order section of the LTC1067 has three outputs which typically source 33mA and sink 2mA. Driving coaxial cable, capacitive loads or resistive loads less than 10k will degrade the total harmonic distortion performance of any filter design. Refer to Output Loading in the Applications Information section for more details. When evaluating the distortion or noise performance of a filter, the output should be buffered with a wideband amplifier. INV A, INV B (Pins 8, 9): Inverting Input. These pins are the high impedance inverting inputs of internal op amps. They are susceptible to stray capacitance coupling to low impedance nodes such as signal outputs and power supply lines. Resistors that are connected from a signal output to the inverting input pin should be located as close to the inverting input as possible. AGND (Pin 15): Analog Ground. The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation Pin 15 is connected to the analog ground plane. For single supply operation Pin 15 should be bypassed to the analog ground plane with at least a 1µF capacitor. An on-chip resistive voltage divider sets the bias at one-half of the supply. CLK (Pin 16): Clock Input. Any CMOS logic clock source with a square-wave output and a 50% duty cycle (± 10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be connected to the clock’s ground at a single point only. Table 1 shows the clock’s low and high level threshold values for dual supply or single supply operation. Logic low level signals must be greater than the negative supply voltage. With a ± 5V power supply, the clock levels may be either ± 5V or 0V to 5V. Logic high level signals should be less than the positive supply voltage. However, when the positive supply voltage is either 3V or 3.3V, the clock signal can be as high as 5.5V. Table 1. Clock Source High and Low Threshold Levels POWER SUPPLY ± 5V Single 5V Single 3V, 3.3V HIGH LEVEL ≥ 2.2V ≥ 2.2V ≥ 2V LOW LEVEL ≤ 0.50V ≤ 0.50V ≤ 0.40V BLOCK DIAGRA 8 W U U U Sine waves are not recommended for the clock input. The clock signal should be routed from the right side of the IC package to avoid coupling to any power supply lines or input or output signal paths. A 200Ω resistor between the clock source and Pin 16 will slow down the rise and fall times of the clock to reduce charge coupling of the clock. This will result in less clock feedthrough noise on the output signal. V+ 1 INV A 8 V+ 3 15k HPA/NA BPA 6 LPA 5 – + 7 + ∑ 4 – AGND 15 HPB/NB SA BPB 11 LPB 12 15k INV B V – 14 CLK 9 16 + – 10 + ∑ 13 – 1067 BD SB LTC1067/LTC1067-50 ODES OF OPERATIO Linear Technology’s universal switched-capacitor filters are designed with a fixed internal, nominal fCLK/fO ratio. The LTC1067 has a 100:1 f CLK /f O r atio and the LTC1067-50 has a 50:1 fCLK/fO ratio. Filter designs often require the fCLK /fO ratio of each section to be different from the nominal ratio and in most cases different from each other. Ratios other than the nominal value are possible with external resistors. Operating modes use external resistors, connected in different arrangements to realize different fCLK /fO ratios. By choosing the proper mode, the fCLK /fO ratio can be increased or decreased from the part’s nominal ratio. The choice of operating mode also effects the transfer function at the HP/N pins. The LP and BP pins always give the lowpass and bandpass transfer functions respectively, regardless of the mode utilized. The HP/N pins have a different transfer function depending on the mode used. Mode 1 yields a notch transfer function. Mode 3 yields a highpass transfer function. Mode 2 yields a highpassnotch transfer function (i.e., a highpass with a stopband notch). More complex transfer functions, such as lowpass-notch, allpass or complex zeros, are achieved by summing two or more of the LP, BP or HP/N outputs. This is illustrated in sections Mode 2n and Mode 3a. Choosing the proper mode(s) for a particular application is not trivial and involves much more than just adjusting the fCLK/fO ratio. Listed here are six of the nearly twenty modes available. To make the design process simpler and quicker, Linear Technology has developed the FilterCADTM for Windows® design software. FilterCAD is an easy-touse, powerful and interactive filter design program. The designer can enter a few filter specifications and the program produces a full schematic. FilterCAD allows the designer to concentrate on the filter’s transfer function and not get bogged down in the details of the design. Alternatively, those who have experience with the Linear Technology family of parts can control all of the details themselves. For a complete listing of all the operating modes, consult the appendices of the FilterCAD manual or the Help files in FilterCAD. FilterCAD can be obtained free of charge on the Linear Technology web site (http:// www.linear-tech.com) or you can order the FilterCAD CD-ROM by contacting Linear Technology’s marketing department. U Mode 1 In Mode 1, the ratio of the external clock frequency to the center frequency of each 2nd order section is internally fixed at the part’s nominal ratio. Figure 3 illustrates Mode 1 providing 2nd order notch, lowpass and bandpass outputs. Mode 1 can be used to make high order Butterworth lowpass filters; it can also be used to make low Q notches and for cascading 2nd order bandpass functions tuned at the same center frequency. Mode 1 is faster than Mode 3. Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC. CC R3 R2 N VIN R1 S BP LP W – + AGND + Σ – ∫ ∫ 1067 F03 f fO = CLK ; fn = fO RATIO R2 R3 Q = R3 ; HON = – ;H =– R1 OBP R1 R2 HOLP = HON NOTE: RATIO = 100 FOR LTC1067 = 50 FOR LTC1067-50 Figure 3. Mode 1, 2nd Order Filter Providing Notch, Bandpass and Lowpass Outputs Mode 1b Mode 1b is derived from Mode 1. In Mode 1b (Figure 4) two additional resistors R5 and R6 are added to lower the amount of voltage fed back from the lowpass output into the input of the SA (or SB) switched-capacitor summer. This allows the filter’s clock-to-center frequency ratio to be adjusted beyond the part’s nominal ratio. Mode 1b maintains the speed advantages of Mode 1 and should be considered an optimum mode for high Q designs with fCLK to fCUTOFF (or fCENTER) ratios greater than the part’s nominal ratio. FilterCAD is a trademark of Linear Technology Corporation. Windows is a registered trademark of Microsoft Corporation. 9 LTC1067/LTC1067-50 ODES OF OPERATIO CC R6 R3 R5 R2 N VIN R1 S BP LP – + AGND + Σ – ∫ NOTE: RATIO = 100 FOR LTC1067 = 50 FOR LTC1067-50 f R6 fO = CLK ;f =f RATIO (R6 + R5) n O R3 R6 ; H = – R2 ; H Q = R3 =– R1 OBP R1 R2 (R6 + R5) ON R2 R6 + R5 HOLP = – R6 R1 √ √ ( Figure 4. Mode 1b, 2nd Order Filter Providing Notch, Bandpass and Lowpass Outputs The parallel combination of R5 and R6 should be kept below 5k. Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC. Mode 3 In Mode 3, the ratio of the external clock frequency to the center frequency of each 2nd order section can be adjusted above or below the part’s nominal ratio. Figure 5 illustrates Mode 3, the classical state variable configuration, providing highpass, bandpass and lowpass 2nd order filter functions. Mode 3 is slower than Mode 1. Mode 3 can be used to make high order all-pole bandpass, lowpass and highpass filters. Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC. Mode 2 Mode 2 is a combination of Mode 1 and Mode 3, shown in Figure 6. With Mode 2, the clock-to-center frequency ratio, fCLK/fO, is always less than the part’s nominal ratio. The advantage of Mode 2 is that it provides less sensitivity to resistor tolerances than does Mode 3. Mode 2 has a highpass-notch output where the notch frequency depends solely on the clock frequency and is therefore less than the center frequency, fO. 10 U Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC. CC R4 R3 R2 W ∫ 1067 F04 HP VIN R1 S BP LP – + + Σ – ∫ ∫ 1067 F05 ) AGND fO = fCLK RATIO 1 R3 R2 R2 R3 √ R4 ; Q = 1.005 (R2) √ R4 (1 – (RATIO)(0.32)(R4)) R3 (1 – (RATIO)(0.32)(R4)) 1 ; HOLP = – R4 R1 R3 HOHP = – R2 ; HOBP = – R1 R1 NOTE: RATIO = 100 FOR LTC1067 = 50 FOR LTC1067-50 Figure 5. Mode 3, 2nd Order Section Providing Highpass, Bandpass and Lowpass Outputs CC R4 R3 R2 HPN VIN R1 S BP LP – + + Σ – ∫ ∫ 1067 F06 AGND √ 1 + R4 ; f = RATIO R2 1 R3 Q = 1.005 ( ) 1 + R2 √ R4 R3 (1 – (RATIO)(0.32)(R4)) fO = fCLK RATIO R2 n fCLK HOHPN = – R2 R2 (AC GAIN, f >> fO); HOHPN = – R1 R1 1 R3 1– (RATIO)(0.32)(R4) ( 1 1 + R2 R4 ) (DC GAIN) HOBP = – R3 R1 ( ) ; HOLP = – R2 R1 ( 1 1 + R2 R4 ) NOTE: RATIO = 100 FOR LTC1067 = 50 FOR LTC1067-50 Figure 6. Mode 2, 2nd Order Filter Providing Highpass Notch, Bandpass and Lowpass Outputs LTC1067/LTC1067-50 ODES OF OPERATIO Mode 3a This is an extension of Mode 3 where the highpass and lowpass outputs are summed through two external resistors, RH and RL, to create a notch (see Figure 7). Mode 3a is more versatile than Mode 2 because the notch frequency can be higher or lower than the center frequency of the 2nd order section. The external op amp of Figure 7 is not always required. When cascading the sections of the LTC1067, the highpass and lowpass outputs can be summed directly into the inverting input of the next section. Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC. CC R4 R3 R2 HP VIN R1 S BP LP – + AGND + Figure 7. Mode 3a, 2nd Order Filter Providing a Highpass Notch or Lowpass Notch Output f fO = CLK 1 + R2 RATIO R4 f R fn = CLK 1+ H RATIO RL RG RG HOLPn (f = 0)= + RH RL CC R4 R3 R2 HP VIN R1 S BP LP – + AGND + Figure 8. Mode 2n, 2nd Order Filter Providing a Lowpass Notch Output U Mode 2n This mode extends the circuit topology of Mode 3a to Mode 2 (Figure 8) where the highpass-notch and lowpass outputs are summed through two external resistors, RH and RL, to create a lowpass output with a notch higher in frequency than the notch in Mode 2. This mode, shown in Figure 8, is most useful in lowpass elliptic designs. When cascading the sections of the LTC1067, the highpassnotch and lowpass outputs can be summed directly into the inverting input of the next section. Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC. W √ R4 f = RATIO √ R 1 R2 Q = 1.005 (R3) R2 √ R4 R3 (1 – (RATIO)(0.32)(R4)) R R (f = ∞) = ( ) ( R2 ) ; H (f = 0) = ( ) ( R4 ) H R R1 R R1 fO = fCLK RATIO R2 ;n fCLK RH L OHPn G H OLPn G L Σ – NOTE: RATIO = 100 FOR LTC1067 = 50 FOR LTC1067-50 ∫ RH ∫ RL RG – + HIGHPASS OR LOWPASS NOTCH OUTPUT EXTERNAL OP AMP OR INPUT OP AMP OF THE LTC1067, SIDES A OR B 1067 F07 √ √ ( )( ) ( R2 R1 1 1 + R2 R4 1 ) Q = 1.005 (R3) √ 1 + R2 R4 R2 R3 (1 – (RATIO)(0.32)(R4)) Σ – NOTE: RATIO = 100 FOR LTC1067 = 50 FOR LTC1067-50 ∫ RH ∫ RL RG – + LOWPASS NOTCH OUTPUT EXTERNAL OP AMP OR INPUT OP AMP OF THE LTC1067, SIDES A OR B 1067 F08 11 LTC1067/LTC1067-50 APPLICATIONS INFORMATION A switched-capacitor integrator generally exhibits a higher input offset than a discrete RC integrator. The larger offset is mainly due to the charge injection from the CMOS switches into the integrated capacitor. The integrator’s op amp offset, typically a couple of millivolts, also adds to the overall offset value. Figure 9 shows the input offsets from a single 2nd order section. Table 2 lists the formula for the output offset voltage for various modes and output pins. INV VOS1 HP/N BP LP – + +∑ – S VOS2 VOS3 1067 F09 Figure 9. Block Diagram of a 2nd Order Section Showing the Input Offsets Operating Limits The Maximum Q vs Frequency (fO) graphs, under Typical Performance Characteristics, define an upper limit of operating Q for each LTC1067 (or LTC1067-50) 2nd order section. These graphs indicate the power supply, fO and Q value conditions under which a filter implemented with an LTC1067 will remain stable when operated at temperatures of 70°C or less. For a 2nd order section, a bandpass gain error of 3dB or less is arbitrarily defined as a condition for stability. When the passband gain error begins to exceed 1dB, the use of capacitor CC will reduce the gain error (capacitor CC is connected from the lowpass node to the inverting node of a 2nd order section). Please refer to Figures 3 through 8. The value of CC can be best determined experimentally, and as a guide it should be about 5pF for each 1dB of gain error and not to exceed 15pF. When operating the LTC1067 near the Table 2. Output DC Offsets for a Second Order Section MODE 1 1b 2 3 VOSHP/N VOS1 [1 + (R2/R3) + (R2/R1)] – (VOS3)(R2/R3) VOS1 [1 + (R2/R3) + (R2/R1)] – (VOS3)(R2/R3) VOS1 [1 + (R2/R3) + (R2/R1) + (R2/R4) – (VOS3) (R2/R3)](R4/R2 + R4) + (VOS2)(R2/R2 + R4) VOS2 12 U W U U limits defined by the Typical Performance Characteristics graphs, passband gain variations of 2dB or more should be expected. Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter’s output pins. The clock feedthrough is tested with the filter’s input grounded and depends on PC board layout and on the value of the power supplies. With proper layout techniques, the typical values of clock feedthrough are listed under Electrical Characteristics. Any parasitic switching transients during the rising and falling edges of the incoming clock are not part of the clock feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The clock feedthrough, can be greatly reduced by adding a simple RC lowpass network at the final filter output. This RC will completely eliminate any switching transients. Wideband Noise The wideband noise of the filter is the total RMS value of the device’s noise spectral density and is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and cannot be reduced with post filtering. For a notch filter the noise of the filter is centered at the notch frequency. The total wideband noise (µVRMS) is nearly independent of the value of the clock. The clock feedthrough specifications are not part of the wideband noise. For a specific filter design, the total noise depends on the Q of each section and the cascade sequence. VOSBP VOS3 VOS3 VOS3 VOS3 VOSHP/N – VOS2 (VOSHP/N – VOS2)[1 + (R5/R6)] VOSHP/N – VOS2 VOS1 [1 + (R4/R1) + (R4/R2) + (R4/R3)] – (VOS2) (R4/R2) – (VOS3)(R4/R3) VOSLP LTC1067/LTC1067-50 APPLICATIONS INFORMATION Aliasing Aliasing is an inherent phenomenon of switched-capacitor filters and occurs when the frequency of the input signals that produce the strongest aliased components have a frequency, fIN, such as (fSAMPLING – fIN) that falls into the filter’s passband. For both the LTC1067 and the LTC1067-50, the sampling frequency is twice fCLK. If the input signal spectrum is not band limited, aliasing may occur. Output Loading The op amps on the LTC1067/LTC1067-50 have a rail-torail output stage. The output loading issues can be divided into resistive loading effects and capacitive loading effects. Resistive loading effects the maximum output signal swing. This effect is shown in the typical performance curves. Note that the load on the output must include both the feedback resistor and any external load resistor. For example, consider the following situation: the part is running on split power supplies, the section is configured in Mode 3, the R4 resistor is 20k and an external 20k load is connected from the LP node to ground. The load on the LP output is 20k in parallel with 20k, or 10k. All testing on the LTC1067/LTC1067-50 is done with a 10k load. For the best results, the load resistance on all output pins should be at least 10k. Capacitive loading reduces the stability of the op amps. The signal at the output of a switched-capacitor filter is composed of a series of very small steps. The op amp must respond to a step and fully settle before the next step. As the stability of the op amp is decreased, the output step response has increased ringing and a much longer settling time. This longer settling time drastically lowers the maximum usable clock speed and introduces errors. If the capacitive loading is sufficiently high, the stability will be decreased to the point of oscillation at the output. The LTC1067/LTC1067-50 are sensitive to capacitive loading. Capacitive loading should be kept below 20pF. Good, tight layout techniques should be maintained at all times. These parts should not drive long traces and never drive a long coaxial cable. When probing the LTC1067 or U W U U LTC1067-50, always use a 10× probe. Never use a 1× probe. A standard 10× probe has a capacitance of 10pF to 15pF while a 1× probe’s capacitance can be as high as 150pF. The 1× probe will probably cause oscillation. What to Do with an Unused Section If the LTC1067 or LTC1067-50 is used as a single 2nd order filter, the other 2nd order section is not used. Do not leave this section unconnected. If the section is unconnected, inputs and outputs are left to float to undetermined levels and oscillation may occur. The unused section should be connected as shown in Figure 10. V+ INV – ∑ + HP BP LP 1067 F10 Figure 10. Connections for an Unused Section Output Voltage Swing on a Single Supply Voltage The typical performance curves show the output voltage swing limitations. The curves show the output signal swing, in volts peak-to-peak, versus the output load resistance. The peak-to-peak swing is limited by the following three considerations: the op amp’s output swings closer to the negative supply than the positive supply, the AGND pin is biased at the midpoint of the supplies and all operating modes are inverting. The op amps in the LTC1067/LTC1067-50 swing closer to the negative supply rail than the positive supply rail. The positive output voltage swing for single supply operation is shown in Figures 11 and 12. The negative output voltage swing is about 15mV for the LTC1067 and 10mV for the LTC1067-50. The negative output voltage swing is nearly independent of load resistance since the load in this case is connected to the V – supply rail. For single supply applications, the on-chip resistor divider sets the voltage at the AGND pin to the midpoint of the V + and V – potentials. The AGND voltage is the reference for all internal op amps. If the input to the filter is at the V – rail, 13 LTC1067/LTC1067-50 APPLICATIONS INFORMATION 5.0 4.5 LTC1067 POSITIVE OUTPUT VOLTAGE SWING (V) 4.0 LTC1067-50 3.5 3.0 2.5 0 2 4 6 8 10 12 14 16 18 20 1067 F11 LOAD RESISTANCE (kΩ TO V –) Figure 11. LTC1067/LTC1067-50 Positive Output Voltage Swing vs Load Resistance, 5V Supply 3.3 POSITIVE OUTPUT VOLTAGE SWING (V) 3.0 2.7 2.4 2.1 1.8 1.5 0 2 4 LTC1067 VS = 3.3V LTC1067-50 VS = 3V 6 8 10 12 14 16 18 20 1067 F12 LOAD RESISTANCE (kΩ TO V –) Figure 12. LTC1067/LTC1067-50 Positive Output Voltage Swing vs Load Resistance, 3.3V/3V Supplies the output of the first section is near the positive rail (operating modes invert the signal). The output of the first stage will saturate at about 250mV (typical for 5V supply) from positive supply. The output from the second stage will be 250mV from the negative supply rail (assuming inversion again) even though the op amp’s output is capable of swinging to within 15mV. The positive output voltage swing being less than the negative swing, coupled with the AGND potential set at the midpoint of the supplies and inverting of the signal, yields the following equation for peak-to-peak output swing: VP-P Swing = (V + – V –) – 2(V+ – VPOSITIVE SWING) 14 U W U U Many applications are more concerned with the negative output swing than the positive output swing. Interfacing to an ADC running on a single 5V supply with a 4.096 reference voltage is a standard example. The LTC1067 or LTC1067-50 will easily reach the 4.096V level for a fullscale reading. The issue is how close does the output go to ground. The further the output is from ground, the more codes that are essentially lost. The previous example demonstrated that the lowest output voltage would be about 250mV, although, as is shown below, 15mV is achievable. To achieve a lower negative output swing voltage, the AGND voltage must be adjusted down below the midpoint. The AGND voltage is determined by two equal, on-chip resistors. These resistors are typically 15k each. While the ratio of these two resistors is tightly matched, the absolute value of the resistors is not tightly controlled. Adjusting the AGND voltage by simply adding an external resistor can be done, but caution must be exercised. In Figure 13, a resistor is used to adjust the AGND voltage for use with a 5V powered ADC with a full-scale input of 4.096V. The resistor value was chosen carefully to assure that a 4.096V input signal to the filter yields a full-scale reading from the ADC and a 0V input signal gives the lowest possible value (15mV for the LTC1067 and 10mV for the LTC1067-50). The circuit works well over temperature and part variations. For this application, the 5V supply must be above 4.75V. 1 2 5V (4.75VMIN) 0.1µF 3 4 5 6 7 8 V+ NC V+ SA LPA BPA HPA/NA INV A LTC1067 LTC1067-50 CLK AGND V– SB LPB BPB HPB/NB INV B 16 15 14 13 12 11 10 9 1067 F13 64.9k 1% 1µF Figure 13. Power and AGND Connections for 5V ADC with 4.096V Full Scale LTC1067/LTC1067-50 APPLICATIONS INFORMATION Figure 14 illustrates how a resistor adjusts the AGND voltage for use with a 3V/3.3V powered ADC with a fullscale input of 2.048V. As in the previous circuit, the resistor value was chosen carefully to assure that a 2.048V input signal to the filter yields a full-scale reading from the ADC and a 0V input signal gives the lowest possible value. For this application, the power supply must be above 2.7V for an LTC1067-50 filter and above 3V for an LTC1067 filter. 1 2 3V TO 3.6V (LTC1067) 2.7V TO 3.6V (LTC1067-50) 0.1µF 3 4 5 6 7 8 V+ NC V+ SA LPA BPA HPA/NA INV A LTC1067 LTC1067-50 CLK AGND V– SB LPB BPB HPB/NB INV B 16 15 14 13 12 11 10 9 1067 F14 1µF Figure 14. Power and AGND Connections for 3V/3.3V ADC with 2.048V Full Scale Semi-Custom Filter Program Linear Technology has in place a program to deliver fully integrated filters, custom designed for any specified application. These semi-custom filters are based on an existing universal filter product with integrated, on-chip resistors. The final filter is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested solution in a smaller package. For the LTC1067 or LTC1067-50 parts, a semicustom filter comes in the SO-8 package and requires only a clock and a decoupling capacitor. For more details on the semi-custom filter program, contact Linear Technology’s marketing department. Demonstration Board There is a demonstration board available for the LTC1067/ LTC1067-50. Demonstration board 150A has the LTC1067 part installed and the board 150B has the LTC1067-50 installed. The schematic for the board is shown in Figure 15 and the assembly drawing is shown in Figure 16. To U W U U obtain a demonstration board, call your local representative or Linear Technology’s marketing department. The demonstration board has all integrated circuits, connectors and decoupling capacitors installed. The board is ready to be configured with the appropriate resistors and jumper connections. There are two sets of power supply connections. One is for the LTC1067/LTC1067-50 and the other is for the buffering op amp on the board. Having separate connections gives the board the most flexibility. The two sets of supplies can be connected together if a common supply is desired. When configuring the board for split supply operation, a jumper wire must be installed in the JPAGND position. This connects the AGND pin of the device to the ground plane of the board. The JPVNEG jumper must be left open. The power supply is then connected to V +, V – and GND turrets (all of the GND turrets on the board are the same). For single supply operation, insert a wire in the JPVNEG jumper and leave the JPAGND jumper open. This connects the V – pin to the board’s ground plane. The JPAGND jumper must be left open so that the on-chip resistor network can set the AGND potential at the midpoint of the supply. Connect the power supply to V + and any GND turret. The V – turret can be left open or shorted to the adjacent GND turret. If the buffering op amp is run on the same single voltage supply, the VOA + turret and the V + turrets must be connected together and the VOA – turret must be shorted to the adjacent GND turret. The J1 BNC connector is the clock input. There is a 200Ω series resistor connected between the connector and the CLK pin of the part. This resistor, coupled with the CLK pin’s input capacitance, slows down the rise and fall times of the clock signal and decreases high frequency coupling. The clock input is not terminated to 50Ω or 75Ω. An external terminator should be used. Jumpers JP51 and JP61 are connected in parallel with R51 and R61 respectively. Jumper JP51 connects the LPA pin of the part with the SA pin. This can be used for operating modes 1 or 2. Alternatively, a 0Ω resistor in the R51 position fulfills the same requirement. The JP61 jumper connects the SA pin of the part to the AGND pin. 33.2k 1% 15 LTC1067/LTC1067-50 APPLICATIONS INFORMATION This would be used for operating Mode 3. Here, a 0Ω resistor in the R61 position also works. Jumpers JP52 and JP62 perform the same functions on the B side of the part. The buffering amplifier can be configured for inverting or noninverting operation. For inverting applications, connect jumper JP2 positions 1 and 2. Additionally, connect jumper JP4 for split supply applications or JP8 for a single supply. For a noninverting application, connect jumper JP2 positions 2 and 3. Several other jumpers should be connected as follows: JP1: Install a jumper wire from position 1 to position 2, leave the other positions open. JP5: Install a jumper wire if split supply, leave open if single supply. JP6: Leave open. JP7: Install a jumper wire. JP9: Install a jumper wire if single supply, leave open if split supply. J1 TP1 V+ C3 + 10µF 16V TP9 R51 R41 R31 R21 TP4 VIN TP10 1 3 JP1 2 R11 4 RH1 RB1 D1 MBR0630T1 JP61 R61 JP51 C6, 0.1µF 1 2 3 4 5 V+ NC V+ CLK AGND V– CLOCK IN R1 200Ω 1% 16 15 14 C2, 0.1µF C7 0.1µF R62 JP52 R52 RL2 RB2 RH2 C13 R42 R32 R22 RL1 1/2 4 LT1498 JP9 JP6 JP5 R4 + 5 6 7 1/2 LT1498 JP7 C12 Figure 15. Schematic for the LTC1067/LTC1067-50 Demo Board 16 + – – 2 + LTC1067 13 OR SB LTC1067-50 12 LPA LPB 6 11 BPA BPB 7 10 HPA/NA HPB/NB 8 9 INV A INV B SA + + U W U U CONNECT THIS JUMPER FOR DUAL SUPPLIES JPAGND C1 10µF, 6.3V CONNECT THIS JUMPER FOR SINGLE SUPPLIES. THE LTC1067 HAS ON-CHIP RESISTORS TO GENERATE 1/2 SUPPLY FOR AGND D2 MBR0630T1 JPVNEG JP62 TP2 V– JP3 C5 C4 10µF 16V TP8 R2 JP8 JP4 R3 TP3 VOA+ JP2 123 3 C8 0.1µF 8 1 + C9 10µF 36V TP5 VOUT TP6 TP7 VOA– C11 10µF 36V TP11 C10 0.1µF 1067 F15 LTC1067/LTC1067-50 APPLICATIONS INFORMATION Figure 16. Silkscreen for the LTC1067/LTC1067-50 Demo Board TYPICAL APPLICATIONS 5th Order Lowpass with Input RC (Fixed Frequency) 5V 0.1µF 1 2 3 4 R41, 20k VIN RIN1 16.9k CIN1 1500pF 5% RIN2 22.6k R31, 47.5k R21, 22.6k 5 6 7 8 V+ NC V+ SA LTC1067 LPA BPA LPB BPB CLK AGND 16 15 0.1µF fCLK –5V HPA/NA HPB/NB INV A INV B Frequency Response (fCUTOFF = 10kHz) 10 0 –10 –20 GAIN (dB) –40 –50 –60 –70 –80 –90 1 10 FREQUENCY (kHz) 100 1067 TA05b GAIN (dB) –30 U W U U U 14 V– SB 13 12 11 10 9 R42, 47.5k R32, 29.4k R22, 45.3k VS fCUTOFF CIN1 fCLK ± 5V 20k 15k 750pF 1000pF 2MHz 1.5MHz 5V 10k 1500pF 1MHz 3V 5k 3000pF 500kHz 1067 TA05a RH1, 118k RL1, 24.3k VOUT Passband Gain Variation Due to CIN 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 –1.25 –1.50 1 2 4 6 8 10 FREQUENCY (kHz) 20 1067 TA05c CIN1 = 1500pF – 5% CIN1 = 1500pF CIN1 = 1500pF + 5% 17 LTC1067/LTC1067-50 TYPICAL APPLICATIONS 1kHz Linear Phase Bandpass Filter 5V R61 40.2k R51 4.99k R31, 56.2k R21, 10k R11 60.4k VIN 0.1µF 1 2 3 4 5 6 7 8 V+ NC V + Gain and Group Delay vs Frequency 10 5 0 –5 GAIN INPUT (500mV/DIV) GAIN (dB) –10 –15 –20 –25 –30 –35 –40 600 760 920 1080 FREQUENCY (Hz) 1240 DELAY 5V R61 7.32k 1µF R51 4.99k R31, 255k R21, 4.99k R11 267k VIN 0.1µF 18 U CLK AGND V LTC1067 16 15 100kHz –5V 0.1µF – 14 SA LPA BPA SB LPB BPB 13 12 11 10 9 R42, 80.6k R32, 53.6k R22, 10k VS ± 5V MAXIMUM FREQUENCY 5kHz CENTER 5V (OR ±2.5V) 3V (OR ±1.5V) 2.5kHz 2.2kHz HPA/NA HPB/NB INV A INV B RB1, 36.5k 1067 TA06a VOUT Sine Burst Response DELAY (ms) 16 15 14 3.0 2.5 2.0 1.5 1.0 0.5 0 1400 OUTPUT (50mV/DIV) 5ms/DIV 1067 TA06c 1067 TA06b Single Supply, 4th Order Bandpass Filter fCENTER = fCLK/64, – 3dB BW = fCENTER/20 1 2 3 4 V+ NC V+ SA CLK AGND V– 64kHz 13 SB LTC1067-50 12 5 LPA LPB 6 7 8 BPA HPA/NA INV A BPB HPB/NB INV B RB1, 115k 11 10 9 R62 R52 4.99k 8.66k R32, 255k R22, 4.99k VS SINGLE 5V SINGLE 3.3V SINGLE 3V MAXIMUM fCENTER 12kHz 7.5kHz 5.5kHz NOISE (FILTER INPUT AT V +/2) 426 µVRMS 333 µVRMS 290 µVRMS 1067 TA07a VS SINGLE 5V SINGLE 3.3V SINGLE 3V VOUT LTC1067/LTC1067-50 TYPICAL APPLICATIONS Single Supply, 4th Order Bandpass Filter VS = 5V, fCLK = 64kHz Gain vs Frequency –5 0 5 10 1 0 –1 –2 GAIN (dB) GAIN (dB) 15 20 25 30 35 40 45 500 700 900 1100 1300 FREQUENCY (kHz) 1500 1067 TA07b LTC1067 Dual Bandpass Filters VS = ± 5V, fCLK = 150kHz (fCENTER1 =1.3kHz, fCENTER2 = 2.1kHz) 5V 0.1µF R61 15k R51 4.99k R31, 232k R21, 4.99k R11 232k VIN1 VOUT1 1 2 3 4 5 6 7 8 V+ NC V + SA LTC1067 LPA BPA SB LPB BPB 12 11 10 9 R42, 5.23k R32, 75k R22, 4.99k GAIN (dB) HPA/NA HPB/NB INV A VIN2 INV B PACKAGE DESCRIPTION 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.016 – 0.050 (0.406 – 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0° – 8° TYP Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U Gain vs Frequency Sine Burst Response VIN (500mV/DIV) –3 –4 –5 –6 –7 –8 –9 960 980 1000 1020 FREQUENCY (kHz) 1040 1067 TA07b VOUT (50mV/DIV) 5ms/DIV 1067 TA07d Frequency Response 5 0 VOUT1 VOUT2 CLK AGND V 16 15 150kHz –5V 0.1µF – 14 –5 –10 –15 –20 –25 –30 –35 –40 –45 13 R12,140k VOUT2 1067 TA08a 1 2 3 4 FREQUENCY (kHz) 5 1067 TA08b Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 0.053 – 0.068 (1.351 – 1.727) 0.004 – 0.0098 (0.102 – 0.249) 16 15 14 13 12 11 10 9 0.008 – 0.012 (0.203 – 0.305) 0.025 (0.635) BSC 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) GN16 (SSOP) 1197 1 23 4 56 7 8 19 LTC1067/LTC1067-50 PACKAGE DESCRIPTION 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0° – 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE TYPICAL APPLICATION 1.02kHz Notch Filter for Telecom System 5V 1 0.1µF 2 3 R61, 9.88k* 4 R51, 4.99k* 5 R31, 61.9k R21, 10k C21, 300pF** VIN*** R11, 18.7k * R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORS ** C21 AND C22 IMPROVE THE NOTCH DEPTH WHERE 1 (30)(f NOTCH) < < (75)(f NOTCH) 2π(R2x)(C2X) WITHOUT C21 AND C22 THE NOTCH DEPTH IS LIMITED TO –35dB 1067 TA03 *** VIN ≤ 1.25VP-P 6 7 8 V+ NC V+ SA LPA BPA HPA/NA INV A LTC1067 16 15 1µF R62, 10k* 200Ω 0 CLK AGND SB LPB BPB 13 12 R52, 4.99k* 11 10 9 R32, 464k GAIN (dB) HPB/NB INV B RH1, 40.2k RELATED PARTS PART NUMBER LTC1068-25 LTC1068-50 LTC1068-200 LTC1068 LTC1562 DESCRIPTION High Speed Quad Universal Building Block Filter Low Power Quad Universal Building Block Filter Low Noise, Oversampled Quad Universal Building Block Filter Quad Universal Building Block Filter Quad, Universal, Continuous Time Building Block COMMENTS 25:1 Clock-to-fO Ratio 50:1 Clock-to-fO Ratio 200:1 Clock-to-fO Ratio 100:1 Clock-to-fO Ratio 10kHz < fC < 150kHz 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 0.004 – 0.010 (0.101 – 0.254) 16 15 14 13 12 11 10 9 0.050 (1.270) TYP 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) S16 0695 1 2 3 4 5 6 7 8 U Frequency Response fCLK = 125kHz –10 –20 –30 –40 –50 –60 –70 14 V– R22, 75k C22, 30pF** VOUT –80 –90 –100 800 900 1000 1100 FREQUENCY (kHz) 1200 1067 TA04 10675f LT/TP 0698 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1997