LTC1149CN

LTC1149 LTC1149-3.3/LTC1149-5 High Efficiency Synchronous Step-Down Switching Regulators FEATURES s s s DESCRIPTIO s s s s s s s Operation to 48V Input Voltage Ultrahigh Efficiency: Up to 95% Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained over Wide Current Range Logic-Controlled Micropower Shutdown Short-Circuit Protection Very Low Dropout Operation: 100% Duty Cycle Synchronous FET Switching for High Efficiency Adaptive Nonoverlap Gate Drives Available in 16-Pin Narrow SO Package The LTC ®1149 series is a family of synchronous stepdown switching regulator controllers featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. These devices drive external complementary power MOSFETs at switching frequencies up to 250kHz using a constant off-time current-mode architecture. Special onboard regulation and level-shift circuitry allow operation at input voltages from dropout to 48V (60V absolute max). The constant off-time architecture maintains constant ripple current in the inductor, easing the design of wide input range converters. Current mode operation provides excellent line and load transient response. The operating current level is user-programmable via an external current sense resistor. The LTC1149 series incorporates automatic power saving Burst Mode operation when load currents drop below the level required for continuous operation. Standby power is reduced to only about 8mW at VIN = 12V. In shutdown, both MOSFETs are turned off. APPLICATI s s s s s s S Notebook and Palmtop Computers Portable Instruments Battery-Operated Digital Devices Industrial Power Distribution Avionics Systems Telecom Power Supplies , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. TYPICAL APPLICATI 1N4148 CAP 0.068µF VIN VIN 1N4148 PGATE PDRIVE 0.047µF D1 1N5819 P-CHANNEL IRFR9024 L* 62µH + CIN 100µF 100V + VCC 3.3µF VCC EFFICIENCY (%) LTC1149-5 0V = NORMAL >2V = SHUTDOWN 3300µF 1k CT 470pF SHDN1 SHDN2 ITH CT SGND SENSE + SENSE – NGATE P, RGNDS 1000pF RSENSE** 0.05Ω VOUT 5V/2A N-CHANNEL IRFR024 + COUT 220µF 60 0.02 1149 F01 *COILTRONICS CTX62-2-MP **KRL SL-1-C1-0R050J Figure 1. High Efficiency Step-Down Regulator U LTC1149-5 Efficiency 100 FIGURE 1 CIRCUIT VIN = 12V 90 VIN = 24V 80 70 0.2 LOAD CURRENT (A) 2 1149 TA01 UO UO 1 LTC1149 LTC1149-3.3/LTC1149-5 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW PGATE VIN VCC PDRIVE VCC CT ITH SENSE – 1 2 3 4 5 6 7 8 16 CAP 15 SHDN2 14 RGND 13 NGATE 12 PGND 11 SGND VFB / 10 SHDN1* 9 SENSE + S PACKAGE 16-LEAD PLASTIC SO Input Supply Voltage (Pin 2)...................... – 15V to 60V VCC Output Current (Pin 3) .................................. 50mA VCC Input Voltage (Pin 5)........................................ 16V Continuous Output Current (Pins 4, 13) .............. 50mA Sense Voltages (Pins 8, 9) VIN ≥ 12.7V .......................................... 13V to – 0.3V VIN < 12.7V ............................. (VCC + 0.3V) to – 0.3V Shutdown Voltages (Pins 10, 15) ............................. 7V Operating Temperature Range .................... 0°C to 70°C Extended Commercial Temperature Range ............................... – 40°C to 85°C Junction Temperature (Note 1) ............................ 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1149CN LTC1149CN-3.3 LTC1149CN-5 LTC1149CS LTC1149CS-3.3 LTC1149CS-5 N PACKAGE 16-LEAD PDIP *FIXED OUTPUT VERSIONS TJMAX = 125°C, θJA = 70°C/ W (N) TJMAX = 125°C, θJA = 110°C/ W (S) Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL V10 I10 VOUT PARAMETER Feedback Voltage (LTC1149 Only) Feedback Current (LTC1149 Only) Regulated Output Voltage LTC1149-3.3 LTC1149-5 Output Voltage Line Regulation Output Voltage Load Regulation LTC1149-3.3 LTC1149-5 Burst Mode Output Ripple I2 Input DC Supply Current (Note 3) Normal Mode Burst Mode Shutdown VCC V2 – V3 VIN – V1 Internal Regulator Voltage (Sets MOSFET Gate Drive Levels) VCC Dropout Voltage P-Gate to Source Voltage (Off) VIN = 9V TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted. MIN q q CONDITIONS TYP 1.25 0.2 MAX 1.29 1 3.43 5.2 40 65 100 UNITS V µA V V mV mV mV mVP-P 1.21 VIN = 9V ILOAD = 700mA ILOAD = 700mA VIN = 9V to 48V, ILOAD = 50mA 5mA < ILOAD < 2A 5mA < ILOAD < 2A ILOAD = 0A VIN = 12V VIN = 48V VIN = 12V VIN = 48V VIN = 12V, V15 = 2V VIN = 48V, V15 = 2V VIN = 12V to 48V I3 = 20mA VIN = 5V, I3 = 10mA VIN = 12V VIN = 48V q q 3.23 4.9 – 40 3.33 5.05 0 40 60 50 2.0 2.2 0.6 0.8 135 300 ∆VOUT q q 2.8 3.0 0.9 1.1 170 390 11 250 q 9.75 10.25 200 q q – 0.2 – 0.2 0 0 2 U mA mA mA mA µA µA V mV V V W U U WW W LTC1149 LTC1149-3.3/LTC1149-5 ELECTRICAL CHARACTERISTICS SYMBOL V 9 – V8 PARAMETER Current Sense Threshold Voltage LTC1149 LTC1149-3.3 LTC1149-5 V10 V15 I15 I6 tOFF tr, tf Shutdown 1 Threshold LTC1149-3.3, LTC1149-5 Shutdown 2 Threshold Shutdown 2 Input Current CT Pin Discharge Current Off-Time (Note 4) Driver Output Transition Times V15 = 5V TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted. MIN TYP 25 150 25 150 25 150 0.8 1.4 18 50 4 70 2 5 100 MAX UNITS mV mV mV mV mV mV V V µA µA µA µs ns CONDITIONS V8 = 5V, V10 = 1.32V (Forced) V8 = VOUT – 100mV V8 = 3.5V (Forced) V8 = VOUT – 100mV V8 = 5.3V (Forced) V8 = VOUT – 100mV q q q 130 130 130 0.5 0.8 170 170 170 2 2 25 90 10 6 200 VOUT In Regulation, VSENSE– = VOUT VOUT = 0V CT = 390pF, ILOAD = 700mA CL = 3000pF (Pins 4, 13), VIN = 6V – 40°C ≤ TA ≤ 85°C (Note 5), unless otherwise noted. SYMBOL V10 VOUT PARAMETER Feedback Voltage LTC1149 Only Regulated Output Voltage LTC1149-3.3 LTC1149-5 Input DC Supply Current (Note 3) Normal Mode Burst Mode Shutdown VCC V9 – V 8 V15 tOFF Internal Regulator Voltage (Sets MOSFET Gate Drive Levels) Current Sense Threshold Voltage Shutdown 2 Threshold Off-Time (Note 4) CT = 390pF, ILOAD = 700mA, VIN = 10V VIN = 9V ILOAD = 700mA ILOAD = 700mA VIN = 12V VIN = 48V VIN = 12V VIN = 48V VIN = 12V, V15 = 2V VIN = 48V, V15 = 2V VIN = 12V to 48V I3 = 20mA Low Threshold (Forced) High Threshold (Forced) 9.75 CONDITIONS MIN 1.2 3.17 4.85 TYP 1.25 3.33 5.05 2.0 2.2 0.6 0.8 135 300 10.25 25 150 1.4 5 MAX 1.3 3.43 5.2 3.2 3.5 1.05 1.30 230 520 11 UNITS V V V mA mA mA mA µA µA V mV mV V µs I2 125 0.8 3.8 175 2 6 The q denotes specifications which apply over the full operating temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1149CN, LTC1149CN-3.3, LTC1149CN-5: TJ = TA + (PD )(70°C/W) LTC1149CS, LTC1149CS-3.3, LTC1149CS-5: TJ = TA + (PD)(110°C/W) Note 2: Pin 10 is a shutdown pin on the LTC1149-3.3 and LTC1149-5 fixed output voltage versions and must be at ground potential for testing. Note 3: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power dissipation at high input voltages. See Typical Performance Characteristics and Applications Information. Note 4: In applications where RSENSE is placed at ground potential, the offtime increases approximately 40%. Note 5: The LTC1149, LTC1149-3.3, and LTC1149-5 are not tested and not quality assurance sampled at – 40°C and 85°C. These specifications are guaranteed by design and/or correlation. 3 LTC1149 LTC1149-3.3/LTC1149-5 TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Input Voltage 100 FIGURE 1 CIRCUIT ILOAD = 1A 95 EFFICIENCY (%) 60 40 20 90 FIGURE 1 CIRCUIT ILOAD = 1A ∆VOUT (mV) ∆VOUT (mV) 85 –40 80 –60 0 10 20 30 INPUT VOLTAGE (V) 40 50 1149 G02 0 10 30 20 INPUT VOLTAGE (V) DC Supply Current 3.0 2.5 400 SUPPLY CURRENT (mA) ACTIVE MODE 2.0 1.5 1.0 0.5 0 0 10 20 30 INPUT VOLTAGE (V) 40 50 1149 G04 SUPPLY CURRENT (µA) 300 NORMALIZED FREQUENCY SLEEP MODE Gate Charge Supply Current 30 25 20 QP + QN = 100nC 15 10 QP + QN = 50nC 5 0 50 100 150 200 OPERATING FREQUENCY (kHz) 250 1149 G07 GATE CHARGE CURRENT (mA) SENSE VOLTAGE (mV) OFF-TIME (µs) 4 UW 40 50 1149 G01 Line Regulation 20 0 –20 –40 –60 –80 –100 Load Regulation FIGURE 1 CIRCUIT VIN = 24V 0 –20 0 0.5 1.0 1.5 2.0 LOAD CURRENT (A) 2.5 1149 G03 Supply Current in Shutdown 2.0 VSD2 = 2V 1.5 Operating Frequency vs (VIN – VOUT) VOUT = 5V T = 0°C T = 25°C T = 70°C 1.0 200 100 0.5 0 0 10 30 20 INPUT VOLTAGE (V) 40 50 1149 G05 0 0 5 15 20 10 (VIN – VOUT) VOLTAGE (V) 25 1149 G06 Off-Time vs VOUT 80 70 60 50 40 30 20 10 LTC1149-3.3 0 0 1 3 4 2 OUTPUT VOLTAGE (V) 5 1149 G08 Current Sense Threshold Voltage 160 140 120 100 80 60 40 20 0 0 20 60 40 TEMPERATURE (°C) 80 100 1149 G09 MAXIMUM THRESHOLD LTC1149-5 MINIMUM THRESHOLD LTC1149 LTC1149-3.3/LTC1149-5 PI FU CTIO S PGATE (Pin 1): Level-Shifted Gate Drive Signal for Top P-Channel MOSFET. The voltage swing at Pin 1 is from VIN to VIN – VCC. VIN (Pin 2): Main Supply Input Pin. VCC (Pin 3): Output Pin of Low Dropout 10V Regulator. Pin 3 is not protected against DC short circuits. PDRIVE (Pin 4): High Current Gate Drive for Top P-Channel MOSFET. The voltage swing at Pin 4 is from VCC to ground. VCC (Pin 5): Regulated 10V Input for Driver and Control Supplies. Must be closely decoupled to power ground. CT (Pin 6): External capacitor CT from Pin 6 to ground sets the operating frequency. (The frequency is also dependent on the ratio VOUT/VIN.) ITH (Pin 7): Gain Amplifier Decoupling Point. The current comparator threshold increases with the Pin 7 voltage. SENSE – (Pin 8): Connects to internal resistive divider which sets the output voltage in LTC1149-3.3 and LTC1149-5 versions. Pin 8 is also the (–) input for the current comparator. SENSE+ (Pin 9): The (+) Input for the Current Comparator. A built-in offset between Pins 8 and 9 in conjunction with RSENSE sets the current trip threshold. SHDN1/VFB (Pin 10): In fixed output voltage versions, Pin 10 serves as a shutdown pin for the control circuitry only (VCC is not affected). Taking Pin 10 of the LTC1149-3.3 or LTC1149-5 high holds both MOSFETs off. Must be at ground potential for normal operation. For the LTC1149 adjustable version, Pin 10 serves as the feedback pin from an external resistive divider used to set the output voltage. SGND (Pin 11): Small-Signal Ground. Must be routed separately from other grounds to the (–) terminal of COUT. PGND (Pin 12): Driver Power Ground. Connects to source of N-channel MOSFET and the (–) terminal of CIN. NGATE (Pin 13): H igh Current Drive for Bottom N-channel MOSFET. The voltage swing at Pin 13 is from ground to VCC. RGND (Pin 14): Low Dropout Regulator Ground. Connects to power ground. SHDN2 (Pin 15): Master Shutdown Pin. Taking Pin 15 high shuts down VCC and all control circuitry; requires a logic signal with tr, tf < 1µs. CAP (Pin 16): Charge Compensation Pin. A capacitor from Pin 16 to VCC provides the charge required by the P-drive level-shift capacitor during supply transitions. The Pin 16 capacitor must be larger than the Pin 4 capacitor. OPERATIO The LTC1149 series uses a current mode, constant offtime architecture to synchronously switch an external pair of complementary power MOSFETs. Operating frequency is set by an external capacitor at the timing capacitor, Pin 6. The output voltage is sensed either by an internal voltage divider connected to SENSE–, Pin 8 (LTC1149-3.3 and LTC1149-5) or an external divider returned to VFB Pin 10 (LTC1149). A voltage comparator V, and a gain block G, compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1149 series automatically switches between two modes of operation, burst and continuous. The voltage comparator is the primary control element for Burst Mode operation, while the gain block controls the output voltage in continuous mode. U U U U (Refer to Functional Diagram) A low dropout 10V regulator provides the operating voltage VCC for the MOSFET drivers and control circuitry. The driver outputs at Pins 4 and 13 are referenced to ground, which fulfills the N-channel MOSFET gate drive requirement. The P-channel gate drive at Pin 1 must be referenced to the main supply input VIN, which is accomplished by level-shifting the Pin 4 signal via an internal 500k resistor and external capacitor. During the switch “ON” cycle in continuous mode, current comparator C monitors the voltage between Pins 8 and 9 connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the PGATE output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor connected to Pin 6 is now allowed to discharge at a rate determined by the off-time controller. The discharge 5 LTC1149 LTC1149-3.3/LTC1149-5 OPERATIO current is made proportional to the output voltage (measured by Pin 8) to model the inductor current, which decays at a rate which is also proportional to the output voltage. While the timing capacitor is discharging, the NGATE output is high, turning on the N-channel MOSFET. When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the NGATE output to go low (turning off the N-channel MOSFET) and the PGATE output to also go low (turning the P-channel MOSFET back on). The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal SLEEP line to go low and the N-channel MOSFET to turn off. FU CTIO AL DIAGRA VIN 2 CAP 16 SHDN2 15 LOW DROPOUT 10V REGULATOR 14 RGND VCC 3 V R SLEEP S C VTH1 Q 25mV TO 150mV VOS 13k G T S – VTH2 6 CT OFF-TIME CONTROL VIN SENSE – 7 ITH 11 SGND 6 + + + – – + – + – W U (Refer to Functional Diagram) The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode, much of the circuitry is turned off, dropping the supply current from several milliamperes (with the MOSFETs switching) to 600µA. When the output capacitor has discharged by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and this process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the N-gate output can go high, the P-drive output must also be high. Likewise, the P-drive output is prevented from going low when the N-gate output is high. Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the frequency variation as dropout is approached, the offtime controller increases the discharge current as VIN drops below VOUT + 1.5V. In dropout the P-channel MOSFET is turned on continuously. U U Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149. 1 PGATE 5 VCC 500k 4 PDRIVE 500k 13 NGATE 12 PGND 9 SENSE + 8 SENSE – 100k 1.25V REFERENCE 10 SHDN1 (VFB) 1149 FD LTC1149 LTC1149-3.3/LTC1149-5 TEST CIRCUIT + 0.1µF VIN 0.068µF IRF9Z34 MBR380 1 2 0.047µF 3 4 1µF 5 6 7 390pF 3300pF 8 V8 1000pF VOUT 1149 TC + 220µF 100V PGATE VIN VCC PDRIVE LTC1149 VCC CT ITH SENSE – CAP SHDN2 RGND NGATE PGND SGND 16 15 14 13 12 11 + V15 IRFZ34 + 50µH + 25k V10 + 1k VFB / 10 SHDN1 9 SENSE + V9 – V8 75k APPLICATIO S I FOR ATIO Typical Application Circuit The basic LTC1149 series application circuit is shown in Figure 1. External component selection is driven by the input voltage and output load requirement, and begins with the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected and the loop is compensated. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 48V. If the application does not require greater than 15V operation, then the LTC1148 should be used. RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1149 series current comparator has a threshold range which extends from a minimum of 25mV/RSENSE to a maximum of 150mV/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for Operating Frequency). Solving for RSENSE and allowing a margin for variations in the LTC1149 series and external component values yields: RSENSE = 100mV IMAX A graph for selecting RSENSE versus maximum output current is given in Figure 2. The LTC1149 series works well with values of RSENSE from 0.02Ω to 0.2Ω. The load current below which Burst Mode operation commences, IBURST, and the peak short-circuit current, ISC(PK), both track IMAX. Once RSENSE has been chosen, IBURST and ISC(PK) can be predicted from the following equations: IBURST ≈ 15mV RSENSE ISC(PK) = 150mV RSENSE + + 220µF 0.05Ω U W U U 7 LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO The LTC1149 series automatically extends tOFF during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current ISC(AVG) to be reduced to approximately IMAX. 0.20 0.18 0.16 0.14 RSENSE (Ω) 0.12 0.10 0.08 0.06 0.04 0.02 0 0 1 3 4 2 MAXIMUM OUTPUT CURRENT (A) 5 1149 F02 Figure 2. RSENSE vs Maximum Output Current L and CT Selection for Operating Frequency The LTC1149 series uses a constant off-time architecture with tOFF determined by an external timing capacitor CT. Each time the P-channel MOSFET switch turns on, the voltage on CT is reset to approximately 3.3V. During the off-time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the current in inductor L, which likewise decays at a rate proportional to VOUT. Thus the inductor value must track the timing capacitor value. The value of CT is calculated from the desired continuous mode operating frequency, f: –5 V CT = (7.8)(10 ) 1 – OUT VIN f CT CAPACITANCE (pF) ) ) A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency is given by: 8 U f= 1 tOFF W UU ) 1– VOUT VIN ) )) VREG VOUT where: tOFF = (1.3)(104)(CT) VREG is the desired output voltage (i.e., 5V, 3.3V), while VOUT is the actual output voltage. Thus VREG/VOUT = 1 when in regulation. Note that as VIN decreases, the frequency decreases. When the input to output voltage differential drops below 1.5V, the LTC1149 series reduces tOFF by increasing the discharge current in CT. This prevents audible operation prior to dropout. Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 25mV/RSENSE of peakto-peak inductor ripple current. This results in a minimum required inductor value of: LMIN =( 5.1)(105)(RSENSE)(CT)(VREG) As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used, the inductor current will decrease past zero and change polarity. A consequence of this is that the LTC1149 series may not enter Burst Mode operation and efficiency will be severely degraded at low currents. 1400 VOUT = 5V 1200 1000 800 600 400 200 0 0 50 150 100 FREQUENCY (kHz) 200 250 1149 F03 VIN = 48V VIN = 24V VIN = 12V Figure 3. Timing Capacitor Selection LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause Burst Mode operation to be falsely triggered in the LTC1149 series. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ . Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new surface mount designs available from Coiltronics do not increase the height significantly. P-Channel MOSFET Selection Two external power MOSFETs must be selected for use with the LTC1149 series: a P-channel MOSFET for the main switch, and an N-channel MOSFET for the synchronous switch. The minimum input voltage determines whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V) may be used. If VIN is expected to drop below 8V, logiclevel threshold MOSFETs (VGS(TH) < 2.5V) are strongly recommended. When logic-level MOSFETs are used, the absolute maximum VGS rating for the MOSFETs must be greater than the LTC1149 series internal regulator voltage VCC. U Selection criteria for the P-channel MOSFET include the on-resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1149 is operating in continuous mode, the duty cycle for the P-channel MOSFET is given by: V P-Ch Duty Cycle = OUT VIN The P-channel MOSFET dissipation at maximum output current is given by: V P-Ch PD = OUT (IMAX)2(1 + ∂P) RDS(ON) VIN + K(VIN)2(IMAX)(CRSS)(f) W U U where ∂ is the temperature dependency of RDS(ON) and K is a constant related to the gate drive current. Note the two distinct terms in the equation. The first gives the I2R losses, which are highest at low input voltages, while the second gives the transition losses, which are highest at high input voltages. For VIN < 24V, the high current efficiency generally improves with larger MOSFETs (although gate charge losses begin eating into the gains. See Efficiency Considerations). For VIN > 24V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. This is illustrated in the Design Example section. The term (1 + ∂) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but ∂ = 0.007/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET electrical characteristics. The constant K is much harder to pin down, but K = 5 can be used for the LTC1149 series to estimate the relative contributions of the two terms in the P-channel dissipation equation. N-Channel MOSFET and D1 Selection The same input voltage constraints apply to the N-channel MOSFET as to the P-channel with regard to when logiclevel devices are required. However, the dissipation calculation is quite different. The duty cycle and dissipation for Kool Mµ is a registered trademark of Magnetics, Inc. 9 LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO the N-channel MOSFET operating in continuous mode are given by: V –V N-Ch Duty Cycle = IN OUT VIN V –V N-Ch PD = IN OUT (IMAX)2 (1 + ∂N)RDS(ON) VIN where ∂ is the temperature dependency of RDS(ON). Note that there is no transition loss term in the N-channel dissipation equation because the drain-to-source voltage is always low when the N-channel MOSFET is turning on or off. The remaining I2R losses are the greatest at high input voltage or during a short circuit, when the N-channel duty cycle is nearly 100%. Fortunately, low RDS(ON) N-channel MOSFETs are readily available which reduce losses to the point that heat sinking is not required, even during continuous short-circuit operation. The Schottky diode D1 shown in Figure 1 only conducts during the dead-time between the conduction of the two power MOSFETs. D1’s sole purpose in life is to prevent the body diode of the N-channel MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D1 is omitted). Therefore, D1 should be selected for a forward voltage of less than 0.7V when conducting IMAX. Finally, both MOSFETs and D1 must be selected for breakdown voltages higher than the maximum VIN. CIN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IMAX [VOUT (VIN – VOUT)]1/2 CIN Required IRMS ≈ VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IMAX/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s 10 U ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. An additional 0.1µF ceramic capacitor may also be required on VIN for high frequency decoupling. The selection of COUT is driven by the required effective series resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1149 series: COUT Required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2RSENSE, the efficiency degrades by less than 1%. If the ESR is greater than 2RSENSE, the voltage ripple on the output capacitor will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon, Chemicon and Sprague should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR for its size, at a somewhat higher price. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. In surface mount applications multiple capacitors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For example, if 200µF/10V is called for in an application requiring 3mm height, two AVX 100µF/10V (P/N TPSD 107K010) could be used. Consult the manufacturer for other specific recommendations. At low supply voltages, a minimum value of COUT is suggested to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is too small, the W U U LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO output ripple at low frequencies will be large enough to trip the voltage comparator. This causes the Burst Mode operation to be activated when the LTC1149 series would normally be in continuous operation. The effect is most pronounced with low values of RSENSE and can be improved by operating at higher frequencies with lower values of L. The output remains in regulation at all times. Checking Transient Response Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to (∆ILOAD)(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT until the 1000 L = 50µH RSENSE = 0.02Ω 800 L = 25µH RSENSE = 0.02Ω COUT (µF) 600 400 L = 50µH RSENSE = 0.05Ω 200 0 0 1 3 4 2 (VIN – VOUT) VOLTAGE (V) 5 1149 F04 Figure 4. Minimum Suggested COUT VIN 1N4148 CAP 0.068µF VIN PGATE 1N4148 IRF9Z34 0.047µF PDRIVE NGATE IRFZ34 + VCC 1µF VCC LTC1149 0V = NORMAL >2V = SHUTDOWN SHDN2 VFB 100pF ITH 3300pF 1k CT 200pF CT GNDS SENSE + SENSE – 1000pF Figure 5. High Efficiency Step-Down Regulator with VOUT > VCC U regulator loop adapts to the current change and returns VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing which would indicate a stability problem. The Pin 7 external components shown in the Figure 1 circuit will prove adequate compensation for most applications. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. LTC1149 Adjustable Applications When an output voltage other than 3.3V or 5V is required, the LTC1149 adjustable version is used with an external resistive divider from VOUT to VFB Pin 10. The regulated voltage is determined: W U U VOUT = 1.25 1 + R2 R1 ) ) In applications where VOUT is greater than the LTC1149 internally regulated VCC voltage, RSENSE must be moved to + 150µF 50V 100µH 1N5819 R2 215k 1% R1 25k 1% + 150µF 16V OS-CON VOUT LOAD VOUT = 1.25 1 + R2 R1 () RSENSE 0.05Ω OUTPUT GROUND CONNECTION 1149 F05 VALUES SHOWN FOR VOUT = 12V 11 LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO the ground side of the output to prevent the absolute maximum voltage ratings of the sense pins from being exceeded. This is shown in Figure 5. When the current sense comparator is operating at 0V common mode, the off-time increases approximately 40%, requiring the use of a smaller timing capacitor CT. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100 – (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1149 series circuits: 1) LTC1149 DC supply current, 2) MOSFET gate charge current, 3) I2R losses and 4) P-channel transition losses. 1. The DC supply current is the current which flows into VIN Pin 2 less the gate charge current. For VIN = 12V the LTC1149 DC supply current is 0.6mA for no load, and increases proportionally with load up to 2mA after the LTC1149 series has entered continuous mode. Because the DC supply current is drawn from VIN, the resulting loss increases with input voltage. For VIN = 24V, the DC bias losses are generally less than 3% for load currents over 300mA. However, at very low load currents the DC bias current accounts for nearly all of the loss. 2. MOSFET gate charge current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN which is typically much larger than the DC supply current. In continuous 12 U mode, IGATECHG = f (QN + QP). The typical gate charge for a 0.1Ω N-channel power MOSFET is 25nC, and for a P-channel about twice that value. This results in IGATECHG = 7.5mA in 100kHz continuous operation, for a 5% to 10% typical mid-current loss with VIN = 24V. Note that the gate charge loss increases directly with both input voltage and operating frequency. This is the principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it argues against using larger MOSFETs than necessary to control I2R losses, since overkill can cost efficiency as well as money! 3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor and current shunt. In continuous mode all of the output current flows through L and RSENSE, but is “chopped” between the P-channel and N-channel MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω and RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This results in losses ranging from 3% to 12% as the output current increases from 0.5A to 2A. I2R losses cause the efficiency to roll-off at high output currents. 4. Transition losses apply only to the P-channel MOSFET, and only when operating at high input voltages (typically 24V or greater). Transition losses can be estimated from: Transition Loss ≈ 5(VIN)2 (IMAX)(CRSS)(f) For example, if VIN = 48V, IMAX = 2A, CRSS = 300pF (a very large MOSFET) and f = 100kHz, the transition loss is 0.7W. A loss of this magnitude would not only kill efficiency but would probably require additional heat sinking for the MOSFET! See Design Example for further guidelines on how to select the P-channel MOSFET. Other losses including CIN and COUT ESR dissipative losses, Schottky conduction losses during dead-time, and inductor core losses, generally account for less than 2% total additional loss. W UU LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO LTC1149 Package Dissipation High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1149 series to be exceeded. The LTC1149 supply current is dominated by the gate charge supply current, which is given as a function of operating frequency in the Typical Performance Characteristics. The LTC1149 series junction temperature can be estimated by using the equations given in Note 1 of the Electrical Characteristics. For example, the LT1149CS is limited to less than 11mA from a 48V supply: TJ = 70°C + (11mA)(48V)(110°C/W) = 128°C exceeds absolute maximum To prevent the maximum junction temperature from being exceeded, the Pin 2 supply current must be checked in continuous mode when operating at the maximum VIN. Design Example As a design example, assume VIN = 24V, VOUT = 5V, IMAX = 2.5A and f = 100kHz. RSENSE, CT and L can immediately be calculated: RSENSE = 100mV = 0.039Ω 2.5 (7.8)(10 –5) 5V CT = 1– = 620pF 24V 100kHz ) ) LMIN = (5.1)(105)(0.039Ω)(620pF)(5V) = 62µH Selection of the P-channel MOSFET involves doing calculations for different sized MOSFETs to determine the relative loss contributions. Taking an International Rectifier IRF9Z34 for example, R DS(ON) = 0.14Ω Max, QP = 35nC and CRSS = 200pF (VDS = VIN/2). These values can be used to estimate the I2R losses, transition losses and gate charge supply current losses: Est. I2R Loss (TJ = 100°C) = (5V/24V)(2.5)2 (1 + 0.5)0.14Ω = 270mW Est. Transition Loss = 5(24V)2 (2.5A)(200pF)(100kHz) = 145mW Est. Gate Charge Loss = (100kHz)(35nC)(24V) = 85mW U The same calculations were repeated for a smaller device, the Motorola MTD2955 (RDS(ON) = 0.3Ω) and a larger one, the Harris RFP30P05 (RDS(ON) = 0.065Ω). The results are summarized in the table. CONDITIONS VIN = 24V, VOUT = 5V F = 100kHz, IOUT = 2.5A Est. I2R Loss (100°C) Est. Transition Loss Est. Gate Charge Loss Est. Total Loss P-CHANNEL MOSFET MTD2955 550mW 110mW 60mW 720mW IRF9Z34 270mW 145mW 85mW 500mW RFP30P05 120mW 290mW 240mW 650mW W UU For this set of conditions, the midsized P-channel MOSFET actually produces the lowest total losses at IMAX. The resulting efficiency differences will be even more pronounced at lower output currents. Note that only the I2R and transition losses are dissipated in the MOSFET; the gate charge supply current loss is dissipated by the LTC1149 series. Selection of the N-channel MOSFET is somewhat easier; it need only be sized for the anticipated I2R losses at 100% duty cycle (worst-case assumption for short circuit.) The Siliconix Si9410, for example, has RDS(ON) = 0.03Ω Max and QN = 30nC. This will produce an I2R loss of 250mW at 100°C and a gate charge supply current loss of 75mW. As with the P-channel device, the use of a larger MOSFET may actually result in lower midcurrent efficiency. CIN will require an RMS current rating of at least 1.25A at temperature, and COUT will require an ESR of 0.04Ω for optimum efficiency. The output capacitor ESR requirement can be fulfilled by a single OS-CON or by two or more surface mount tantalums in parallel. Auxiliary Windings – Suppressing Burst Mode Operation The LTC1149 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. Burst Mode operation can be suppressed at low output currents with a simple external network which cancels the 13 LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO 25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from certain types of inductors in high current (IOUT > 5A) applications when they are lightly loaded. An external offset is put in series with the SENSE – pin to subtract from the built-in 25mV offset. An example of this technique is shown in Figure 6. Two 100Ω resistors are inserted in series with the leads from the sense resistor. With the addition of R3, a current is generated through R1 causing an offset of: VOFFSET = VOUT ) R1 R1 + R3 ) If VOFFSET > 25mV, the minimum threshold will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be lower: RSENSE ≈ 75mV IMAX To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Pins 8 and 9. L LTC1149 SENSE + SENSE – 9 1000pF 8 R3 R2 100Ω R1 100Ω 1149 F06 RSENSE Figure 6. Suppressing Burst Mode Operation Output Crowbar An added feature to using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. Pulling the timing capacitor Pin 6 above 1.5V when the output voltage is greater than the desired regulated value, will turn on the N-channel MOSFET. A fault condition which causes the output voltage to go above a maximum value can be detected by external 14 U circuitry. Turning on the N-channel MOSFET when this fault is detected will then force the system fuse to blow. The N-channel MOSFET needs to be sized so it will safely handle this overcurrent condition. The typical delay from pulling the CT Pin 6 high to when the NGATE Pin 13 goes high is 250ns. Under shutdown conditions, the N-channel is held off and pulling Pin 6 high will not cause the output to be crowbarred. A small N-channel FET can be used as an interface between the overvoltage detect circuitry and the LTC1149 as shown in Figure 7. 5 CROWBAR VN2222LL 6 ACTIVE WHEN CROWBAR = VIN OFF WHEN CROWBAR = GROUND 1149 F07 W UU VCC LTC1149 CT Figure 7. Output Crowbar Interface + Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1149 series. These items are also illustrated graphically in the layout diagram of Figure 8. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1149 signal ground Pin 11 must connect separately to the (–) plate of COUT. The other ground Pins 12 and 14 should return to the source of the N-channel MOSFET, anode of the Schottky diode and (–) plate of CIN, which should have as short lead lengths as possible. 2. Does the LTC1149 SENSE – Pin 8 connect to a point close to RSENSE and the (+) plate of COUT? In adjustable applications, the resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. 3. Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The differential decoupling capacitor between Pins 8 and 9 should be as close as possible to the LTC1149. Up to 100Ω may be placed COUT LTC1149 LTC1149-3.3/LTC1149-5 APPLICATIO S I FOR ATIO 1N4148 0.068µF 1µF BOLD LINES INDICATE HIGH CURRENT PATHS 1N4148 CIN P-CHANNEL + + 1 2 0.047µF 3 4 5 6 7 CT 3300pF 1k 8 PGATE VIN VCC PDRIVE VCC CT ITH SENSE – SENSE + 1000pF 9 R2 1149 F08 Figure 8. LTC1149 Series Layout Diagram (see Layout Checklist) in series with each sense lead to help decouple Pins 8 and 9. However, when these resistors are used, the capacitor should be no larger than 1000pF. 4. Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? An additional 0.1µF ceramic capacitor between VIN and power ground may be required in some applications. 5. Is the VCC decoupling capacitor connected closely between Pin 5 of the LTC1149 and power ground? This capacitor carries the MOSFET driver peak currents. 6. Is the SHDN1 Pin 10 (fixed output versions only) actively pulled to ground during normal operation? The SHDN1 pin is high impedance and must not be allowed to float. In adjustable versions, Pin 10 is the feedback pin and is very sensitive to pickup from the switch node. Care must be taken to isolate VFB from possible capacitive coupling of the inductor switch signal. Troubleshooting Hints Since efficiency is critical to LTC1149 series applications, it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the timing capacitor Pin 6. In continuous mode (ILOAD > IBURST) the voltage on Pin 6 should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 9a. When load currents are low (ILOAD < IBURST) Burst Mode operation should occur with the CT pin waveform periodically falling to ground as shown in Figure 9b. If Pin 6 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist. 3.3V (a) CONTINUOUS MODE OPERATION 3.3V Figure 9. CT Pin 6 Waveforms + U + VIN D1 N-CHANNEL 16 15 14 13 12 11 10 100pF R1 COUT RSENSE VOUT L SHUTDOWN W U U – CAP SD2 RGND NGATE PGND SGND VFB/ SHDN1 – + OUTPUT DIVIDER REQUIRED WITH ADJUSTABLE VERSION ONLY 0V 0V (b) Burst Mode OPERATION 1149 F09 15 LTC1149 LTC1149-3.3/LTC1149-5 TYPICAL APPLICATIO S VIN 8V TO 20V 1N4148 0.068µF 0.047µF + 1µF 390pF 3300pF 1k Figure 10. High Efficiency 8V to 20V Input 3.3V/1A Output Regulator 1N4148 0.068µF 0.047µF + 3.3µF 470pF 3300pF 1k Figure 11. High Efficiency 8V to 20V Input 3.3V/3A Output Regulator 16 U 1N4148 IRFR9024 L* 68µH + 100µF 35V RSENSE** 0.1Ω 1 2 3 4 5 6 7 8 PGATE VIN VCC CAP SHDN2 R-GND 16 15 14 13 IRFR024 VOUT 3.3V/1A + 1N5818 P-DRIVE NGATE LTC1149-3.3 12 VCC PGND CT ITH SENSE – SGND SHDN1 SENSE + 11 10 9 220µF 6.3V AVX 0V = NORMAL >2V = SHUTDOWN 1000pF 1149 F10 *COILTRONICS CTX02-11932 **DALE WSC-1/2-0.1 VIN 8V TO 20V 1N4148 IRF9Z34 L* 33µH + 220µF 35V RSENSE** 0.033Ω 1 2 3 4 5 6 7 8 PGATE VIN VCC CAP SHDN2 RGND 16 15 14 13 IRFZ34 VOUT 3.3V/3A + 1N5818 PDRIVE NGATE LTC1149-3.3 12 VCC PGND CT ITH SENSE – 220µF 6.3V × 2 AVX SGND SHDN1 SENSE + 11 10 9 1000pF SHUTDOWN 100Ω 100Ω 1149 F11 *COILTRONICS CTX33-4-KM **KRL SL-1-C1-0R033J LTC1149 LTC1149-3.3/LTC1149-5 TYPICAL APPLICATIO S VIN 5.5V TO 25V 1N4148 0.068µF 0.047µF + 1µF 220pF 3300pF 1k Figure 12. Ultra Wide Input Range (5.5V to 25V) High Efficiency 5V Regulator 1N4148 0.068µF 0.047µF + 1µF 180pF 3300pF 1k *DALE LPE-6562-220MB **KRL SL-1-C1-0R050J Figure 13. 250kHz High Efficiency 12V Input 5V/2A Output Regulator U 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1N4148 Si9435DY L* 33µH + 220µF 35V RSENSE** 0.05Ω PGATE VIN VCC CAP SHDN2 RGND 16 15 14 13 Si9410DY VOUT 5V/2A + 1N5818 PDRIVE NGATE LTC1149-5 12 VCC PGND CT ITH SENSE – 220µF 10V × 2 AVX S-GND SHDN1 SENSE + 11 10 9 1000pF 1149 F12 SHUTDOWN *COILTRONICS CTX33-4 Kool Mµ **KRL SL-1-C1-0R050J VIN 8V TO 16V 1N4148 Si9430DY L* 22µH + 100µF 25V RSENSE** 0.05Ω PGATE VIN VCC CAP SHDN2 RGND 16 15 14 13 Si9410DY VOUT 5V/2A + 1N5818 PDRIVE NGATE LTC1149-5 12 VCC PGND CT ITH SENSE – SGND SHDN1 SENSE + 11 10 9 220µF 10V AVX SHUTDOWN 1000pF 1149 F13 17 LTC1149 LTC1149-3.3/LTC1149-5 TYPICAL APPLICATIO S VIN 48V 1N4148 1N4148 MTD2955 L* 68µH 0.068µF 0.047µF + 3.3µF 620pF 3300pF 1k Figure 14. High Efficiency 48V Input 5V/2.5A Output Regulator 1N4148 1 0.068µF 0.047µF 2 3 4 5 6 PGATE VIN VCC PDRIVE LTC1149 VCC CT ITH SENSE – + 7 1µF 390pF 3300pF 1k 8 *COILTRONICS CTX50-2-MP **IRC LR2010-01-R050-G Figure 15. Logic Selectable 5V/2A or 3.3V/2A High Efficiency Regulator 18 U 1 2 3 4 5 6 7 8 + 100µF 100V RSENSE** 0.04Ω 0.1µF PGATE VIN VCC CAP SHDN2 RGND 16 15 14 13 IRFZ34 VOUT 5V/2.5A + MBR380 PDRIVE NGATE LTC1149-5 12 VCC PGND CT ITH SENSE – SGND SHDN1 11 10 220µF 10V OS-CON SHUTDOWN 100Ω 1000pF 100Ω 1149 F14 9 SENSE + *HURRICANE LAB HL-KI168M **IRC LR2512-01-R040-G VIN 8V TO 20V 1N4148 RFD15P05SM L* 50µH SHUTDOWN + 100µF 35V RSENSE** 0.05Ω CAP SHDN2 RGND NGATE PGND SGND VFB SENSE + 16 15 14 13 12 VOUT 3.3V/2A OR 5V/2A + RFD14N05SM 1N5818 220µF 10V × 2 AVX VN2222LL 11 10 9 1000pF 1149 F15 0V: VOUT = 3.3V 5V: VOUT = 5V 100pF R1A 33k 1% R1B 43k 1% R2 56k 1% LTC1149 LTC1149-3.3/LTC1149-5 TYPICAL APPLICATIO S VIN 12V TO 36V 1N4148 220Ω 1 2 0.1µF 3 4 PGATE VIN VCC 13 PDRIVE NGATE LTC1149-5 5 12 VCC PGND 6 CT ITH SENSE – SGND SHDN1 SENSE + 11 10 9 1000pF *COILTRONICS CTX50-5-52 **DALE LVR-3-0.02 100Ω 100Ω 0V = NORMAL >2V = SHUTDOWN + 7 3.3µF 820pF 3300pF 1k 8 Figure 16. 25W High Efficiency Regulator Using N-Channel MOSFET Switches PACKAGE DESCRIPTIO 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 0.125 (3.175) MIN 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U + 10k 2N3906 1000µF 63V VN2222LL CAP SHDM2 RGND 16 15 14 470Ω 2N2222 0.1µF MUR110 MTP30N06EL L* 50µH RSENSE** 0.02Ω VOUT 5V/5A IRFZ44 MBR380 + 220µF 10V × 2 OS-CON 1149 F16 SEE APPLICATIONS INFORMATION TO SUPPRESS Burst ModeTM OPERATION AT LOW CURRENTS Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.045 – 0.065 (1.143 – 1.651) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9 0.255 ± 0.015* 0.065 (6.477 ± 0.381) (1.651) TYP 0.018 ± 0.003 (0.457 ± 0.076) 1 2 3 4 5 6 7 8 N16 1197 19 LTC1149 LTC1149-3.3/LTC1149-5 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 16 15 14 13 12 11 10 9 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1 2 3 4 5 6 7 8 S16 0695 TYPICAL APPLICATION 1N4148 1N4148 0.068µF 0.047µF + 3.3µF 300pF 3300pF 1k *HURRICANE LAB HL-EK210M **KRL SL-1-C1-0R033J Figure 17. High Efficiency 24V Input 12V/3A Output Regulator RELATED PARTS PART NUMBER LTC1148HV LTC1159 LTC1435A LTC1438 DESCRIPTION High Efficiency, Synchronous Step-Down Switching Regulator High Efficiency, Synchronous Step-Down Switching Regulator High Efficiency, Low Noise, Synchronous Switching Regulator Dual, Low Noise, Synchronous Switching Regulator COMMENTS 4V < VIN < 20V 4V < VIN < 40V, ISHUTDOWN = 20µA 3.5V < VIN < 36V, N-Channel Driver 3.5V < VIN < 36V, N-Channel Driver 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U 1 2 3 4 6 7 8 VIN 20V TO 30V + MTP23P06 L* 100µH SHUTDOWN 220µF 50V PGATE VIN VCC CAP SHDN2 RGND 16 15 14 VOUT 12V/3A R2 172k 1% + 13 PDRIVE NGATE LTC1149 5 12 VCC PGND CT ITH SENSE – SGND VFB SENSE + 11 10 9 1000pF 100pF 150µF 16V × 2 OS-CON MTP36N06E MBR160 R1 20k 1% 100Ω 100Ω RSENSE** 0.033Ω OUTPUT GROUND CONNECTION 1149 F17 1149fa LT/TP 0898 REV A 2K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1993