LTC1165CS8

LTC1163/LTC1165 Triple 1.8V to 6V High-Side MOSFET Drivers FEATURES s s s s s s s s s s DESCRIPTIO Operates from 1.8V to 6V 0.01µA Standby Current 95µA Operating Current per Channel at 3.3V Fully Enhances N-Channel Switches No External Charge Pump Components Built-In Gate Voltage Clamps Easily Protected Against Supply Transients Controlled Switching ON and OFF Times Compatible with 5V, 3V and Sub-3V Logic Families Available in 8-Pin SOIC The LTC1163/LTC1165 triple low voltage MOSFET drivers make it possible to switch supply or ground referenced loads through inexpensive, low RDS(ON) N-channel switches from as little as a 1.8V supply. The LTC1165 has inverting inputs and makes it possible to directly replace P-channel MOSFET switches while maintaining system drive polarity. The LTC1163 has noninverting inputs. Micropower operation, with 0.01µA standby current and 95µA operating current, coupled with a power supply range of 1.8V to 6V, make the LTC1163/LTC1165 ideally suited for 2- to 4-cell battery-powered applications. The LTC1163/LTC1165 are also well suited for sub-3V, 3.3V and 5V nominal supply applications. The LTC1163/LTC1165 internal charge pumps boost the gate voltage 8V above a 3.3V rail, fully enhancing inexpensive N-channels for high- or low-side switch applications. The LTC1163/LTC1165 are available in both an 8-pin DIP and an 8-pin SOIC. APPLICATI s s s s s s s s S PCMCIA Card 3.3V/5V Switch 2-Cell High-Side Load Switching Boost Regulator Shutdown to Zero Standby Current Replacing P-Channel Switches Notebook Computer Power Management Palmtop Computer Power Management Portable Medical Equipment Mixed 3.3V and 5V Supply Switching TYPICAL APPLICATI (1.8V TO 3V) 2-Cell Triple High-Side Switch 18 + 2-CELL BATTERY PACK + 10µF 16 GATE OUTPUT VOLTAGE (V) RFD14N05LSM RFD14N05LSM RFD14N05LSM 14 12 10 8 6 4 2 IN1 CONTROL LOGIC OR µP VS OUT1 IN2 LTC1163 OUT2 LTC1165 IN3 OUT3 GND 2-CELL LOAD 2-CELL LOAD 2-CELL LOAD LTC1163 HAS NONINVERTING INPUTS LTC1165 HAS INVERTING INPUTS LTC1163/65 • TA01 0 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 U MOSFET Switch Gate Voltage LTC1163/65 • TA02 UO UO 1 LTC1163/LTC1165 ABSOLUTE AXI U RATI GS Operating Temperature Range LTC1163C/LTC1165C ........................... 0°C to 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C Supply Voltage ......................................................... 7V Any Input Voltage .......................... 7V to (GND – 0.3V) Any Output Voltage ....................... 20V to (GND – 0.3V) Current (Any Pin)................................................. 50mA PACKAGE/ORDER I FOR ATIO TOP VIEW IN1 1 IN2 2 IN3 3 GND 4 8 7 6 5 VS OUT1 OUT2 OUT3 ORDER PART NUMBER LTC1163CN8 LTC1165CN8 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 100°C, θJA = 130°C/W ELECTRICAL CHARACTERISTICS SYMBOL IQ PARAMETER Quiescent Current OFF CONDITIONS VS = 1.8V to 6V, TA = 25°C, unless otherwise noted. LTC1163C/LTC1165C MIN TYP MAX 0.01 0.01 0.01 60 95 180 q q q q VS = 1.8V, VIN1 = VIN2 = VIN3 = VOFF (Note 1,2) VS = 3.3V, VIN1 = VIN2 = VIN3 = VOFF (Note 1,2) VS = 5V, VIN1 = VIN2 = VIN3 = VOFF (Note 1,2) VS = 1.8V, VIN = VON (Note 2,3) VS = 3.3V, VIN = VON (Note 2,3) VS = 5V, VIN = VON (Note 2,3) 1.8V < VS < 2.7V 2.7V < VS < 6V 1.8V < VS < 6V 0V ≤ VIN ≤ VS VS = 1.8V, VIN = VON (Note 2) VS = 2V, VIN = VON (Note 2) VS = 2.2V, VIN = VON (Note 2) VS = 3.3V, VIN = VON (Note 2) VS = 5V, VIN = VON (Note 2) VS = 3.3V, CGATE = 1000pF Time for VGATE > VS + 1V Time for VGATE > VS + 2V VS = 5V, CGATE = 1000pF Time for VGATE > VS + 1V Time for VGATE > VS + 2V 80% × VS 70% × VS Quiescent Current ON VINH VINL IIN CIN VGATE – VS Input High Voltage Input Low Voltage Input Current Input Capacitance Gate Voltage Above Supply tON Turn-ON Time 2 U U W WW U W TOP VIEW IN1 1 IN2 2 IN3 3 GND 4 8 VS 7 OUT1 6 OUT2 5 OUT3 ORDER PART NUMBER LTC1163CS8 LTC1165CS8 S8 PART MARKING 1163 1165 S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 100°C, θJA = 150°C/W UNITS µA µA µA µA µA µA V V 1 1 1 120 200 400 15% × VS ±1 5 3.5 4.0 4.5 6.0 5.0 40 60 30 40 4.1 4.6 5.2 8.0 9.0 120 180 95 130 6.0 7.0 8.0 9.5 13.0 400 600 300 400 V µA pF V V V V V µs µs µs µs q q q q q LTC1163/LTC1165 ELECTRICAL CHARACTERISTICS SYMBOL tOFF PARAMETER Turn-OFF Time CONDITIONS VS = 1.8V to 6V, TA = 25°C, unless otherwise noted. LTC1163C/LTC1165C MIN TYP MAX 20 15 65 45 200 150 UNITS µs µs VS = 3.3V, CGATE = 1000pF Time for VGATE < 0.5V VS = 5V, CGATE = 1000pF Time for VGATE < 0.5V The q denotes specifications which apply over the full operating temperature range. Note 1: Quiescent current OFF is for all channels in OFF condition. Note 2: LTC1163: VOFF = 0V, VON = VS. LTC1165: VOFF = VS, VON = 0V Note 3: Quiescent current ON is per driver and is measured independently. TYPICAL PERFOR A CE CHARACTERISTICS Standby Supply Current 5 TA = 25°C ALL THREE INPUTS = OFF 4 SUPPLY CURRENT (µA) 3 2 1 0 –1 SUPPLY CURRENT (µA) 500 400 300 200 100 0 600 TA = 25°C ONE INPUT = ON OTHER INPUTS = OFF VGATE – VS (V) 0 1 2 3 4 SUPPLY VOLTAGE (V) LTC1163/65 • TPC01 Input Threshold Voltage 6 TA = 25°C INPUT THRESHOLD VOLTAGE (V) 5 4 3 VHI 2 1 0 VLO TURN-ON TIME (µs) 500 400 300 200 100 0 600 TURN-OFF TIME (µs) 0 1 2 3 4 SUPPLY VOLTAGE (V) LTC1163/65 •TPC04 UW 5 6 5 6 Supply Current per Driver ON 12 Gate Voltage Above Supply TA = 25°C 10 8 6 4 2 0 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 LTC1163/65 • TPC02 LTC1163/65 • TPC03 Turn-ON Time 300 CGATE = 1000pF 250 200 150 100 50 0 Turn-OFF Time CGATE = 1000pF TIME FOR VGATE < 0.5V VGS = 2V VGS = 1V 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 LTC1163/65 • TPC05 LTC1163/65 • TA06 3 LTC1163/LTC1165 TYPICAL PERFOR A CE CHARACTERISTICS Standby Supply Current 5 4 SUPPLY CURRENT (µA) GATE DRIVE CURRENT (µA) 3 2 1 0 –1 SUPPLY CURRENT (µA) 0 10 50 20 30 40 TEMPERATURE (°C) LTC1163/65 • TPC07 PI FU CTIO S Input Pins The LTC1163 is noninverting; i.e., the MOSFET gate is driven above the supply when the input pin is held high. The LTC1165 is inverting and drives the MOSFET gate high when the input pin is held low. The inverting inputs of the LTC1165 allow P-channel switches to be replaced by lower resistance/cost N-channel switches while maintaining system drive polarity. The LTC1163/LTC1165 logic inputs are high impedance CMOS gates with ESD protection diodes to ground and therefore should not be forced below ground. The inputs can however, be driven above the power supply rail as there are no clamping diodes connected between the input pins and supply pin. This facilitates operation in mixed 5V/3V systems. Output Pins The output pin is either driven to ground when the switch is turned OFF or driven above the supply rail when the switch is turned ON. The output is clamped to about 14V above ground by a built-in Zener clamp. This pin has a relatively high impedance when driven above the rail (the equivalent of a few hundred kΩ). Care should be taken to minimize any loading of this pin by parasitic resistance to ground or supply. Supply Pin A 150Ω resistor should be inserted in series with the ground pin or supply pin if negative supply voltage transients are anticipated. This will limit the current flowing from the power source into the LTC1163/LTC1165 to tens of milliamps during reverse battery conditions. OPERATIO The LTC1163/LTC1165 are triple micropower MOSFET drivers designed for operation over the 1.8V to 6V supply range and include the following functional blocks: 3V Logic Compatible Inputs The LTC1163/LTC1165 inputs have been designed to accommodate a wide range of 3V and 5V logic families. 4 UW 60 70 Supply Current per Driver ON 300 250 MOSFET Gate Drive Current 1000 TA = 25°C 100 VS = 5V 10 VS = 3.3V 1 VS = 1.8V VS = 2.2V 10 200 VS = 5V 150 100 50 0 VS = 3.3V VS = 1.8V 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 0.1 0 2 4 6 8 GATE VOLTAGE ABOVE SUPPLY (V) LTC1163/65 • TPC08 LTC1163/65 • TPC09 U U U U The input threshold voltage is set at roughly 50% of the supply voltage and approximately 200mV of input hysteresis is provided to ensure clean switching. The input enables all of the following circuit blocks: the bias generator, the high frequency oscillator and gate charge pump. Therefore, when the input is turned off, the entire circuit powers down and the supply current drops below 1µA. LTC1163/LTC1165 OPERATIO Gate Charge Pump Gate drive for the power MOSFET is produced by an internal charge pump circuit which generates a gate voltage substantially higher than the power supply voltage. The charge pump capacitors are included on chip and therefore no external components are required to generate gate drive. BLOCK DIAGRA APPLICATIO S I FOR ATIO Logic-Level MOSFET Switches The LTC1163/LTC1165 are designed to operate with logic-level N-channel MOSFET switches. Although there is some variation among manufacturers, logic-level MOSFET switches are typically rated with VGS = 4V with a maximum continuous VGS rating of ±10V. RDS(ON) and maximum VDS ratings are similar to standard MOSFETs and there is generally little price differential. Logic-level MOSFETs are frequently designated by an “L” and are usually available in surface mount packaging. Some logic-level MOSFETs are rated with VGS up to ±15V and can be used in applications which require operation over the entire 1.8V to 6V range. Powering Large Capacitive Loads Electrical subsystems in portable battery-powered equipment are typically bypassed with large filter capacitors to reduce supply transients and supply induced glitching. If not properly powered however, these capacitors may themselves become the source of supply glitching. U W W UU U Controlled Gate Rise and Fall Times When the input is switched ON and OFF, the gate is charged by the internal charge pump and discharged in a controlled manner. The charge and discharge rates have been set to minimize RFI and EMI emissions. (One Channel) LTC1165 HIGH FREQUENCY OSCILLATOR CHARGE PUMP GATE LTC1163 INPUT BIAS GENERATOR GATE DISCHARGE LOGIC 14V LTC1163/65 • BD For example, if a 100µF capacitor is powered through a switch with a slew rate of 0.1V/µs, the current during startup is: ISTART = C(∆V/∆t) = (100 × 10 – 6)(1 × 105) = 10A Obviously, this is too much current for the regulator (or output capacitor) to supply and the output will glitch by as much as a few volts. The startup current can be substantially reduced by limiting the slew rate at the gate of an N-channel as shown in Figure 1. The gate drive output of the LTC1163/LTC1165 is passed through a simple RC network, R1 and C1, which substantially slows the slew rate of the MOSFET gate to approximately 1.5 × 10 – 4V/µs. Since the MOSFET is operating as a source follower, the slew rate at the source is essentially the same as that at the gate, reducing the startup current to approximately 15mA which is easily 5 LTC1163/LTC1165 APPLICATIO S I FOR ATIO VIN LT1129-3.3 3.3V + 3.3µF R1 100k R2 1k MTD3055EL C1 0.1µF VS OUT1 1/3 LTC1163 ON/OFF IN1 GND + CL 100µF LTC1163/65 • F01 Figure 1. Powering a Large Capacitive Load managed by the system regulator. R2 is required to eliminate the possibility of parasitic MOSFET oscillations during switch transitions. It is a good practice to isolate the gates of paralleled MOSFETs with 1k resistors to decrease the possibility of interaction between switches. Mixed 5V/3V Systems Because the input ESD protection diodes are referenced to ground instead of the supply pin, it is possible to drive the LTC1163/LTC1165 inputs from 5V CMOS or TTL logic even though the LTC1163/LTC1165 are powered from a 3.3V supply as shown in Figure 2. The input threshold voltage is approximately 50% of the supply voltage or 1.6V TYPICAL APPLICATIO S PCMCIA Card 3.3V/5V VCC Switch 5V PCMCIA CONTROLLER VCC 5V VCC 3V + 10µF 1/2 MMDF3N02HD IN1 IN2 IN3 GND LTC1163/65 • TA03 VS LTC1165 NOTE: USE LTC1163 WITH NONINVERTING PCMCIA CONTROLLERS 6 U on a 3.3V supply which is compatible with 5V TTL and CMOS logic. (The LTC1163/LTC1165 cannot however, be driven by 3V logic when powered from a 5V supply because the threshold is approximately 2.5V.) 3.3V 3.3V LOAD W U UU 5V VS OUT1 1/3 LTC1163 IN1 GND 3.3V LOAD LTC1163/65 • F01 MTD3055EL Figure 2. Direct Interface to 5V Logic Reverse Battery Protection The LTC1163/LTC1165 can be protected against reverse battery conditions by connecting a 150Ω resistor in series with the ground pin or supply pin. The resistor limits the supply current to less than 24mA with –3.6V applied. Because the LTC1163/LTC1165 draw very little current while in normal operation, the drop across the resistor is minimal. The 3.3V µP (or control logic) can be protected by adding 10k resistors in series with the input pins. VCC OUT1 OUT2 MMDF3N02HD OUT3 + 1µF PC CARD SOCKET 3.3V LTC1163/LTC1165 TYPICAL APPLICATIO S 2-Cell to 3.3V, 5V and 12V High-Side Switch/Converter with 0.01µA Standby Current + 2-CELL BATTERY PACK VS CONTROL LOGIC OR µP OUT1 LTC1163 OUT2 LTC1165 OUT3 IN3 GND IN1 IN2 RFD14N05LSM RFD14N05LSM RFD14N05LSM 1 7 3 8 LT1109CS8-12 4 VCC = 3.3V OR 5V 1M 1/4 74HC02 1N4148 EN0 1N4148 1/4 74HC02 1/4 74HC02 EN1 3.3V + 10µF 3.3V LOGIC OR µP IN1 IN2 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U + + 100µF 6.3V 100µH 22µH MBRS120T3 12V 1 7 3 8 22µH MBRS120T3 5V 47Ω 1 2 3 8 MBRS120T3 3.3V 39k + LT1109CS8-5 10µF 20V 4 + LT1173CS8 22µF 16V 4 5 + 24k 220µF 6.3V LTC1163/65 • TA04 PCMCIA Card Socket VPP Switch/Reglator 7,8 100µF 6.3V 2 4 5,6 MMDF3N02HD 1 3 33µH MURS120T3 VPP = 0V, 3.3V, 5V, 12V, OR HI-Z 3 1 LT1109ACS8-12 7 4 OUT1 OUT2 OUT3 GND LTC1163/65 • TA05 8 + 47µF 16V VS IN1 IN2 IN3 LTC1163 EN0 0 1 0 1 EN1 0 0 1 1 OUTPUT 0V 12V VCC HI-Z 2N7002 Ultra-Low Drop Triple 3.3V High-Side Switch MTD 3055EL OUT1 (11V) (11V) (11V) MTD 3055EL MTD 3055EL VS LTC1163 OUT2 LTC1165 OUT3 IN3 GND 3.3V LOAD 3.3V LOAD 3.3V LOAD LTC1163/65 • TA06 7 LTC1163/LTC1165 TYPICAL APPLICATI 5V + 10µF 5V LOGIC OR µP IN1 IN2 3-Cell to 3.3V Ultra-Low Drop Regulator with 2 Ramped Switches + 3-CELL BATTERY PACK + 10µF CONTROL LOGIC OR µP IN1 LTC1163 OUT2 IN2 LTC1165 OUT3 IN3 GND 100k 100k PACKAGE DESCRIPTIO N8 Package 8-Lead Plastic DIP 0.300 – 0.320 (7.620 – 8.128) 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 +0.635 8.255 –0.381 ) 0.010 – 0.020 × 45° (0.254 – 0.508) S8 Package 8-Lead Plastic SOIC 0.008 – 0.010 (0.203 – 0.254) 0.016 – 0.050 0.406 – 1.270 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 U UO VS S Mixed Voltage High- and Low-Side Switches 3.3V Si9956DY VS OUT1 LTC1163 OUT2 LTC1165 OUT3 IN3 GND 5V LOAD 3.3V LOAD 12V + 10µF + 12V LOAD 10µF IRFR024 LTC1163/65 • TA07 MTD3055EL 3.3V OUTPUT 1 OUT1 LT1431 3 510pF 8 3.3k + MTD3055EL 220µF 6.3V 1k MTD3055EL 1k 5 6 680Ω 10k 0.1µF 3.3V LOAD 3.3V LOAD 0.1µF LTC1163/65 • TA08 Dimensions in inches (millimeters) unless otherwise noted. 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 8 0.400 (10.160) MAX 7 6 5 0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN 0.250 ± 0.010 (6.350 ± 0.254) 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 1 2 3 4 0.018 ± 0.003 (0.457 ± 0.076) 0.189 – 0.197 (4.801 – 5.004) 8 7 6 5 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.004 – 0.010 (0.101 – 0.254) 0.228 – 0.244 (5.791 – 6.197) 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC 1 2 3 4 0.150 – 0.157 (3.810 – 3.988) LT/GP 1093 10K REV 0 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1993