LTC1198-2ACS8-PBF

LTC1196/LTC1198 8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options FEATURES n n n n n n n n n n n n DESCRIPTION The LTC®1196/LTC1198 are 600ns, 8-bit A/D converters with sampling rates up to 1MHz. They are offered in 8-pin SO packages and operate on 3V to 6V supplies. Power dissipation is only 10mW with a 3V supply or 50mW with a 5V supply. The LTC1198 automatically powers down to a typical supply current of 1nA whenever it is not performing conversions. These 8-bit switched-capacitor successive approximation ADCs include sample-and-holds. The LTC1196 has a differential analog input; the LTC1198 offers a software selectable 2-channel MUX. The 3-wire serial I/O, SO-8 packages, 3V operation and extremely high sample rate-to-power ratio make these ADCs an ideal choice for compact, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans below 1V full scale (LTC1196) allow direct connection to signal sources in many applications, eliminating the need for gain stages. The A grade devices are specified with total unadjusted error of ±1/2LSB maximum over temperature. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. High Sampling Rates: 1MHz (LTC1196) 750kHz (LTC1198) Low Cost Single Supply 3V and 5V Specifications Low Power: 10mW at 3V Supply 50mW at 5V Supply Auto-Shutdown: 1nA Typical (LTC1198) ±1/2LSB Total Unadjusted Error over Temperature 3-Wire Serial I/O 1V to 5V Input Span Range (LTC1196) Converts 1MHz Inputs to 7 Effective Bits Differential Inputs (LTC1196) 2-Channel MUX (LTC1198) SO-8 Plastic Package APPLICATIONS n n n n High Speed Data Acquisition Disk Drives Portable or Compact Instrumentation Low Power or Battery-Operated Systems TYPICAL APPLICATION Single 5V Supply, 1Msps, 8-Bit Sampling ADC 1μF 5V EFFECTIVE NUMBER OF BITS (ENOBs) Effective Bits and S/(N + D) vs Input Frequency 8 7 6 5 4 3 2 1 0 1k TA = 25°C 10k 100k INPUT FREQUENCY (Hz) 1M 1196/98 G24 50 VREF = VCC = 2.7V fSMPL = 383kHz (LTC1196) fSMPL = 287kHz (LTC1198) VREF = VCC = 5V fSMPL = 1MHz (LTC1196) fSMPL = 750kHz (LTC1198) 44 S/(N + D) (dB) 1 2 ANALOG INPUT 0V TO 5V RANGE 3 4 CS +IN –IN GND LTC1196 VCC CLK DOUT VREF 8 7 6 5 1196/98 TA01 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP, OR SHIFT REGISTERS 119698fa 1 LTC1196/LTC1198 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND .................................... 7V Voltage Analog Reference ....................... –0.3V to VCC + 0.3V Digital Inputs ......................................... –0.3V to 7V Digital Outputs ........................... –0.3V to VCC + 0.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1196-1AC, LTC1198-1AC, LTC1196-1BC, LTC1198-1BC, LTC1196-2AC, LTC1198-2AC, LTC1196-2BC, LTC1198-2BC ................. 0°C to 70°C Storage Temperature Range.................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) ................ 300°C PIN CONFIGURATION LTC1196 CS 1 +IN 2 –IN 3 GND 4 TOP VIEW 8 7 6 5 VCC CLK DOUT VREF LTC1198 CS/ 1 SHUTDOWN CH0 2 CH1 3 GND 4 TOP VIEW 8 7 6 5 VCC (VREF) CLK DOUT DIN S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W ORDER INFORMATION LEAD FREE FINISH LTC1196-1ACS8#PBF LTC1196-1BCS8#PBF LTC1196-2ACS8#PBF LTC1196-2BCS8#PBF LTC1198-1ACS8#PBF LTC1198-1BCS8#PBF LTC1198-2ACS8#PBF LTC1198-2BCS8#PBF TAPE AND REEL LTC1196-1ACS8#TRPBF LTC1196-1BCS8#TRPBF LTC1196-2ACS8#TRPBF LTC1196-2BCS8#TRPBF LTC1198-1ACS8#TRPBF LTC1198-1BCS8#TRPBF LTC1198-2ACS8#TRPBF LTC1198-2BCS8#TRPBF PART MARKING 11961A 11961B 11962A 11962B 11981A 11981B 11982A 11982B PACKAGE DESCRIPTION 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 119698fa 2 LTC1196/LTC1198 RECOMMENDED OPERATING CONDITIONS the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL VCC fCLK tCYC tSMPL thCS tsuCS thDI tsuDI tWHCLK tWLCLK tWHCS tWLCS PARAMETER Supply Voltage Clock Frequency Total Cycle Time Analog Input Sampling Time Hold Time CS Low After Last CLK↑ Setup Time CS↓ Before First CLK↑ (See Figures 1, 2) Hold Time DIN After CLK↑ Setup Time DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer LTC1196 LTC1198 LTC1198 LTC1198 fCLK = fCLK(MAX) fCLK = fCLK(MAX) LTC1196 LTC1198 CONDITIONS MIN 2.7 0.01 0.01 12 16 2.5 10 20 20 20 40% 40% 25 11 15 The l denotes the specifications which apply over LTC1196-1 LTC1198-1 TYP LTC1196-2 LTC1198-2 TYP MAX 6 12.0 9.6 MAX 6 14.4 12.0 MIN 2.7 0.01 0.01 12 16 2.5 13 26 26 26 40% 40% 32 11 15 UNITS V MHz MHz CLK CLK CLK ns ns ns ns 1/fCLK 1/fCLK ns CLK CLK VCC = 5V Operation l CONVERTER AND MULTIPLEXER CHARACTERISTICS LTC1196-1 LTC1198-1 TYP The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-2 LTC1198-2 TYP MAX ±1 ±1 ±1 ±1 PARAMETER No Missing Codes Resolution Offset Error Linearity Error Full-Scale Error Total Unadjusted Error (Note 4) Analog and REF Input Range Analog Input Leakage Current CONDITIONS l l l l l MIN 8 MAX ±1/2 ±1/2 ±1/2 ±1/2 MIN 8 UNITS Bits LSB LSB LSB LSB V (Note 3) LTC1196, VREF = 5.000V LTC1198, VCC = 5.000V LTC1196 (Note 5) –0.05V to VCC + 0.05V l ±1 ±1 μA DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL VIH VIL IIH IIL VOH PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10μA VCC = 4.75V, IO = 360μA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. MIN l l l l l l TYP MAX 0.8 2.5 –2.5 UNITS V V μA μA V V 119698fa 2.0 4.5 2.4 4.74 4.71 3 LTC1196/LTC1198 DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL VOL IOZ ISOURCE ISINK IREF ICC PARAMETER Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current, LTC1196 Supply Current CONDITIONS VCC = 4.75V, IO = 1.6mA CS = High VOUT = 0V VOUT = VCC CS = VCC fSMPL = fSMPL(MAX) CS = VCC, LTC1198 (Shutdown) CS = VCC, LTC1196 fSMPL = fSMPL(MAX), LTC1196/LTC1198 l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. MIN TYP MAX 0.4 ±3 –25 45 0.001 0.5 0.001 7 11 3 1 3 15 20 UNITS V μA mA mA μA mA μA mA mA DYNAMIC ACCURACY SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion THD IMD Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Full-Power Bandwidth The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. CONDITIONS 500kHz/1MHz Input Signal 500kHz/1MHz Input Signal 500kHz/1MHz Input Signal fIN1 = 499.37kHz fIN2 = 502.446kHz MIN LTC1196 TYP 47/45 49/47 55/48 51 8 1 MAX MIN LTC1198 TYP 47/45 49/47 55/48 51 8 1 MAX UNITS dB dB dB dB MHz MHz Full Linear Bandwidth [S/(N + D) > 44dB AC CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-1 LTC1198-1 TYP LTC1196-2 LTC1198-2 TYP SYMBOL tCONV PARAMETER Conversion Time (See Figures 1, 2) CONDITIONS l MIN MAX 600 710 MIN MAX 710 900 UNITS ns ns MHz MHz MHz MHz fSMPL(MAX) Maximum Samping Frequency LTC1196 LTC1196 LTC1198 LTC1198 CLOAD = 20pF l l l l l l l l 1.20 1.00 0.90 0.75 55 70 30 30 45 5 5 30 5 5 15 15 64 73 120 50 1.00 0.80 0.75 0.60 68 88 43 30 55 10 10 30 5 5 20 20 78 94 150 63 tdDO tDIS ten thDO tf tr CIN Delay Time, CLK↑ to DOUT Data Valid Delay Time CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↑ DOUT Fall Time DOUT Rise Input Capacitance ns ns ns ns ns ns ns pF pF pF 119698fa CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF Analog Input On Channel Analog Input Off Channel Digital Input 4 LTC1196/LTC1198 RECOMMENDED OPERATING CONDITIONS SYMBOL fCLK tCYC tSMPL thCS tsuCS thDI tsuDI tWHCLK tWLCLK tWHCS tWLCS PARAMETER Clock Frequency Total Cycle Time Analog Input Sampling Time Hold Time CS Low After Last CLK↑ Setup Time CS↓ Before First CLK↑ (See Figures 1, 2) Hold Time DIN After CLK↑ Setup Time DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer LTC1196 LTC1198 LTC1198 LTC1198 fCLK = fCLK(MAX) fCLK = fCLK(MAX) LTC1196 LTC1198 CONDITIONS l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V Operation. LTC1196-1 LTC1198-1 TYP LTC1196-2 LTC1198-2 TYP MIN 0.01 0.01 12 16 2.5 20 40 40 40 40% 40% 50 11 15 MAX 5.4 4.6 MIN 0.01 0.01 12 16 2.5 40 78 78 78 40% 40% 96 11 15 MAX 4 3 UNITS MHz MHz CLK CLK CLK ns ns ns ns 1/fCLK 1/fCLK ns CLK CLK CONVERTER AND MULTIPLEXER CHARACTERISTICS LTC1196-1 LTC1198-1 TYP The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-2 LTC1198-2 TYP MAX ±1 ±1 ±1 ±1 PARAMETER No Missing Codes Resolution Offset Error Linearity Error Full-Scale Error Total Unadjusted Error (Note 4) Analog and REF Input Range Analog Input Leakage Current CONDITIONS l l l l l MIN 8 MAX ±1/2 ±1/2 ±1/2 ±1/2 MIN 8 UNITS Bits LSB LSB LSB LSB V (Note 3) LTC1196, VREF = 2.5.000V LTC1198, VCC = 2.700V LTC1196 (Note 5) –0.05V to VCC + 0.05V l ±1 ±1 μA DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL VIH VIL IIH IIL VOH VOL IOZ PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage CONDITIONS VCC = 3.6V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10μA VCC = 2.7V, IO = 360μA VCC = 2.7V, IO = 400μA CS = High The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted. MIN l l l l l l l l TYP MAX 0.45 2.5 –2.5 UNITS V V μA μA V V 1.9 2.3 2.1 2.60 2.45 0.3 ±3 V μA 119698fa 5 LTC1196/LTC1198 DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL ISOURCE ISINK IREF ICC PARAMETER Output Source Current Output Sink Current Reference Current, LTC1196 Supply Current CONDITIONS VOUT = 0V VOUT = VCC CS = VCC fSMPL = fSMPL(MAX) CS = VCC = 3.3V, LTC1198 (Shutdown) CS = VCC = 3.3V, LTC1196 fSMPL = fSMPL(MAX), LTC1196/LTC1198 l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted. MIN TYP –10 15 0.001 0.25 0.001 1.5 2.0 3.0 0.5 3.0 4.5 6.0 MAX UNITS mA mA μA mA μA mA mA DYNAMIC ACCURACY SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion THD IMD Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Full-Power Bandwidth The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. CONDITIONS 190kHz/380kHz Input Signal 190kHz/380kHz Input Signal 190kHz/380kHz Input Signal fIN1 = 189.37kHz fIN2 = 192.446kHz MIN LTC1196 TYP 47/45 49/47 53/46 51 5 0.5 MAX MIN LTC1198 TYP 47/45 49/47 55/46 51 5 0.5 MAX UNITS dB dB dB dB MHz MHz Full Linear Bandwidth [S/(N + D) > 44dB AC CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1196-1 LTC1198-1 TYP LTC1196-2 LTC1198-2 TYP SYMBOL tCONV PARAMETER Conversion Time (See Figures 1, 2) CONDITIONS l MIN MAX 1.58 1.85 MIN MAX 2.13 2.84 UNITS μs μs kHz kHz kHz kHz fSMPL(MAX) Maximum Samping Frequency LTC1196 LTC1196 LTC1198 LTC1198 CLOAD = 20pF l l l l l l l l 450 383 337 287 100 110 80 45 90 10 10 30 5 5 30 30 150 180 220 130 333 250 250 187 130 120 100 45 120 15 15 30 5 5 40 40 200 250 250 200 tdDO tDIS ten thDO tf tr CIN Delay Time, CLK↑ to DOUT Data Valid Delay Time CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↑ DOUT Fall Time DOUT Rise Input Capacitance ns ns ns ns ns ns ns pF pF pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF Analog Input On Channel Analog Input Off Channel Digital Input Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 119698fa 6 LTC1196/LTC1198 ELECTRICAL CHARACTERISTICS Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 4: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. Note 5: Channel leakage current is measured after the channel selection. TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Clock Rate 9 8 SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 FREQUENCY (MHz) 14 16 0.000002 VCC = 2.7V TA = 25°C CS = 0V VREF = VCC VCC = 5V SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 LTC1198 0 2.5 3.0 “SHUTDOWN” MODE CS = VCC 5.5 6.0 0.001 100 1k “ACTIVE” MODE CS = 0V LTC1196 LTC1198 SUPPLY CURRENT (mA) 1 LT1196 VCC = 2.7V Supply Current vs Supply Voltage TA = 25°C 10 Supply Current vs Sample Rate LT1196 VCC = 5V 0.1 LT1198 VCC = 5V 0.01 LT1198 VCC = 2.7V TA = 25°C 10k 100k SAMPLE RATE (Hz) 1M 1196/98 G03 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 1196/98 G01 1196/98 G02 Supply Current vs Temperature VREF) 10 9 8 SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1196/98 G04 Offset vs Reference Voltage 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G05 Offset vs Supply Voltage 0.5 0.4 MAGNITUDE OF OFFSET (LSB) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 TA = 25°C VREF = VCC fCLK = 3MHz CS = 0V VCC = 5V VCC = 2.7V MAGNITUDE OF OFFSET (LSB = 1 256 TA = 25°C VCC = 5V fCLK = 12MHz 1196/98 G06 119698fa 7 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Linearity Error vs Reference Voltage 1.0 0.9 0.8 LINEARITY ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G07 Linearity Error vs Supply Voltage MAGNITUDE OF GAIN ERROR (LSB) TA = 25°C VCC = 5V fCLK = 12MHz LINEARITY ERROR (LSB) 0.5 TA = 25°C 0.4 VREF = VCC f = 3MHz 0.3 CLK 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 Supply Current vs Sample Rate TA = 25°C VCC = 5V fCLK = 12MHz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G09 1196/98 G08 Gain vs Supply Voltage 0.5 MAGNITUDE OF GAIN ERROR (LSB) MAXIMUM CLOCK FREQUENCY (MHz) TA = 25°C 0.4 fCLK = 3MHz VREF = VCC 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 19 17 15 13 11 9 7 Maximum Clock Frequency vs Supply Voltage TA = 25°C VREF = VCC CLOCK FREQUENCY (MHz) 18 16 14 12 10 8 6 4 2 0 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 Maximum Clock Frequency vs Source Resistance TA = 25°C VCC = VREF = 5V VIN +IN –IN RSOURCE– 5 2.5 1 1k 10 10k 100 SOURCE RESISTANCE (Ω) 100k 1196/98 G10 1196/98 G11 1196/98 G12 Minimum Clock Rate for 0.1LSB* Error 100 MINIMUM CLOCK FREQUENCY (kHz) 90 80 70 60 50 40 30 20 10 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1196/98 G13 ADC Noise vs Referenced and Supply Voltage 0.35 PEAK-TO-PEAK ADC NOISE (LSB) 0.30 0.25 0.20 0.15 0.10 0.05 0 2.5 100 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 1 10000 TA = 25°C VREF = VCC S&H ACQUISITION TIME (ns) Sample-and-Hold Acquisition Time vs Source Resistance TA = 25°C VCC = VREF = 5V VCC = 5V VREF = 5V RSOURCE+ VIN +IN –IN 1000 100 10 1k SOURCE RESISTANCE (Ω) 10k 1196/98 G15 1196/98 G14 *AS THE FREQUENCY IS DECREASED FROM 12MHz, MINIMUM CLOCK FREQUENCY (ΔERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 12MHz VALUE IS FIRST DETECTED. 119698fa 8 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Digital Input Logic Threshold vs Supply Voltage 1.9 1.7 DOUT DELAY TIME, tdDO (ns) LOGIC THRESHOLD (V) 1.5 1.3 1.1 0.9 0.7 0.5 2.5 TA = 25°C 140 120 100 80 60 40 20 0 2.5 DOUT Delay Time vs Supply Voltage 160 TA = 25°C VREF = VCC DOUT DELAY TIME, tdDO (ns) 140 120 100 80 60 40 20 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 DOUT Delay Time vs Temperature VREF = VCC VCC = 2.7V VCC = 5V 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1196/98 G18 1196/98 G16 1196/98 G17 Input Channel Leakage Current vs Temperature 1000 0.5 INTEGRAL NONLINEARITY ERROR (LSB) VCC = 5V VREF = 5V Integral Nonlinearity vs Code at 5V VCC = 5V VREF = 5V fCLK = 12MHz DIFFERENTIAL NONLINEARITY ERROR (LSB) 0.5 Differential Nonlinearity vs Code at 5V VCC = 5V VREF = 5V fCLK = 12MHz 100 LEAKAGE CURRENT (nA) 10 ON CHANNEL 1 OFF CHANNEL 0.1 0 0 0.01 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1196/98 G19 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G20 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G21 Integral Nonlinearity vs Code at 2.7V INTEGRAL NONLINEARITY ERROR (LSB) VCC = 2.7V VREF = 2.5V fCLK = 3MHz DIFFERENTIAL NONLINEARITY ERROR (LSB) 0.5 0.5 Differential Nonlinearity vs Code at 2.7V EFFECTIVE NUMBER OF BITS (ENOBs) VCC = 2.7V VREF = 2.5V fCLK = 3MHz 8 7 6 5 4 3 2 1 0 Effective Bits and S/(N + D) vs Input Frequency 50 VREF = VCC = 2.7V fSMPL = 383kHz (LTC1196) fSMPL = 287kHz (LTC1198) VREF = VCC = 5V fSMPL = 1MHz (LTC1196) fSMPL = 750kHz (LTC1198) 44 S/(N + D) (dB) 0 0 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G22 –0.5 0 32 64 TA = 25°C 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1196/98 G24 96 128 160 192 224 256 CODE 1196/98 G23 119698fa 9 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS 4096 Point FFT Plot at 5V 0 –10 –20 MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 100 300 200 FREQUENCY (kHz) 400 500 1196/98 G25 4096 Point FFT Plot at 2.7V 0 –10 –20 MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 50 150 100 FREQUENCY (kHz) 200 1196/98 G26 FFT Output of 455kHz AM Signal Digitized at 1Msps 0 –10 –20 MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 100 300 200 FREQUENCY (kHz) 400 500 1196/98 G27 VCC = 5V fIN = 29kHz fSMPL = 882kHz VCC = 2.7V fIN = 29kHz fSMPL = 340kHz VCC = 5V fIN = 455kHz WITH 20kHz AM fSMPL = 1MHz Power Supply Feedthrough vs Ripple Frequency TA = 25°C = 20mV) V (V –10 f CC = RIPPLE CLK 12MHz FEEDTHROUGH (dB) FEEDTHROUGH (dB) –20 –30 –40 –50 –60 –70 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M 1196/98 G28 Power Supply Feedthrough vs Ripple Frequency SIGNAL TO NOISE PLUS DISTORTION (dB) TA = 25°C = 10mV) V (V –10 f CC = RIPPLE CLK 5MHz –20 –30 –40 –50 –60 –70 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M 1196/98 G29 S/(N + D) vs Reference Voltage and Input Frequency 50 fIN = 500kHz 0 0 45 fIN = 200kHz fIN = 100kHz 40 35 - 30 VCC = 5V 25 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 REFERENCE VOLTAGE (V) 1196/98 G30 Intermodulation Distortion at 2.7V 0 –10 –20 MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 50 150 100 FREQUENCY (kHz) 200 250 1196/98 G31 Intermodulation Distortion at 5V 0 –10 –20 MAGNITUDE (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 100 300 200 FREQUENCY (kHz) 400 1196/98 G32 S/(N + D) vs Input Level 50 SIGNAL TO NOISE-PLUS-DISTORTION (dB) VREF = VCC = 5V fIN = 500kHz fSMPL = 1MHz VCC = 2.7V f1 = 100kHz f2 = 110kHz fSMPL = 420kHz VCC = 5V f1 = 200kHz f2 = 210kHz fSMPL = 750kHz 40 30 20 10 0 –40 –35 –30 –25 –20 –15 –10 INPUT LEVEL (dB) –5 0 1196/98 G33 119698fa 10 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Output Amplitude vs Input Frequency 100 SPURIOUS-FREE DYNAMIC RANGE (dB) 70 60 50 40 30 20 10 0 1k 100k 10k 1M INPUT FREQUENCY (Hz) 10M 1196/98 G34 Spurious-Free Dynamic Range vs Frequency VCC = 5V fCLK = 12MHz PEAK-TO-PEAK OUTPUT (%) 80 VREF = VCC = 5V 60 VREF = VCC = 2.7V VCC = 3V fCLK = 5MHz 40 20 0 TA = 25°C 1k 10k 100k FREQUENCY (Hz) 1196/98 G35 1M 10M PIN FUNCTIONS LTC1196 CS (Pin 1): Chip Select Input. A logic low on this input enables the LTC1196. A logic high on this input disables the LTC1196. IN+ (Pin 2): Analog Input. This input must be free of noise with respect to GND. IN– (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. LTC1198 CS/SHUTDOWN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1198. A logic high on this input disables the LTC1198 and disconnects the power to THE LTC1198. CHO (Pin 2): Analog Input. This input must be free of noise with respect to GND. CH1 (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this input. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (VREF)(Pin 8): Power Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. 119698fa 11 LTC1196/LTC1198 BLOCK DIAGRAM VCC (VCC/VREF) CS (CS/SHUTDOWN) CLK BIAS AND SHUTDOWN CIRCUIT IN+ (CH0) SERIAL PORT DOUT CSMPL IN– (CH1) PIN NAMES IN PARENTHESES REFER TO THE LTC1198 GND TEST CIRCUITS On and Off Channel Leakage Current 5V ION A IOFF A ON CHANNEL DOUT 100pF 3k TEST POINT • • • • POLARITY OFF CHANNEL 1196/98 TC01 Voltage Waveform for DOUT Rise and Fall Times, tr , tf DOUT VOH VOL tr tf 1196/98 TC04 12 + – SAR HIGH SPEED COMPARATOR CAPACITIVE DAC 1196/98 BD VREF (DIN) Load Circuit for tdDO, tr and tf 1.4V 1196/98 TC02 Voltage Waveform for DOUT Delay Time, tdDO , thDO CLK VIH tdDO thDO VOH DOUT VOL 1196/98 TC03 119698fa LTC1196/LTC1198 TEST CIRCUITS Load Circuit for tdis and ten TEST POINT CS 3k DOUT 20pF tdis WAVEFORM 1 1196/98 TC05 Voltage Waveforms for tdis VIH VCC tdis WAVEFORM 2, ten DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2) 10% 90% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1196/98 TC06 Voltage Waveforms for ten LTC1196 CS CLK 1 2 3 4 DOUT VOL ten B7 1196/98 TC07 Voltage Waveforms for ten LTC1198 CS DIN START CLK 1 2 3 4 5 6 7 DOUT ten B7 VOL 1196/98 TC08 119698fa 13 LTC1196/LTC1198 APPLICATIONS INFORMATION OVERVIEW The LTC1196/LTC1198 are 600ns sampling 8-bit A/D converters packaged in tiny 8-pin SO packages and operating on 3V to 6V supplies. The ADCs draw only 10mW from a 3V supply or 50mW from a 5V supply. Both the LTC1196 and the LTC1198 contain an 8-bit, switched-capacitor ADC, a sample-and-hold, and a serial port (see Block Diagram). The on-chip sample-and-holds have full-accuracy input bandwidths of 1MHz. Although they share the same basic design, the LTC1196 and LTC1198 differ in some respects. The LTC1196 has a differential input and has an external reference input pin. It can measure signals floating on a DC common mode voltage and can operate with reduced spans below 1V. The LTC1198 has a 2-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. It also automatically powers down when not performing conversion, drawing only leakage current. SERIAL INTERFACE The LTC1196/LTC1198 will interface via three or four wires to ASICs, PLDs, microprocessors, DSPs, or shift registers (see Operating Sequence in Figures 1 and 2). To run at their fastest conversion rates (600ns), they must be clocked at 14.4MHz. HC logic families and any high speed ASIC or PLD will easily interface to the ADCs at that speed (see Data Transfer and Typical Application sections). Full speed operation from a 3V supply can still be achieved with 3V ASICs, PLDs or HC logic circuits. tCYC (12 CLKs) CS tsuCS tdDO DOUT B0 Hi-Z tSMPL NULL BITS B7 B6 B5 B4 B3 B2 B1 B0* tSMPL Hi-Z NULL BITS tCYC (8.5 CLKs) *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1196/98 F01 Figure 1. LTC1196 Operating Sequence tCYC (16 CLKs) CS tsuCS CLK START ODD/ SIGN DUMMY DON’T CARE SGL/ DIFF DUMMY NULL BITS B7 B6 B5 B4 tdDO B3 B2 B1 B0* Hi-Z POWER DOWN DIN DOUT HI-Z tSMPL (2.5 CLKs) tCONV (8.5 CLKs) *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1196/98 F02 Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH1, CH0) 119698fa 14 LTC1196/LTC1198 APPLICATIONS INFORMATION Connection to a microprocessor or a DSP serial port is quite simple (see Data Transfer section). It requires no additional hardware, but the speed will be limited by the clock rate of the microprocessor or the DSP which limits the conversion time of the LTC1196/LTC1198. Data Transfer Data transfer differs slightly between the LTC1196 and the LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK and DOUT . A falling CS initiates data transfer as shown in the LTC1196 Operating Sequence. After CS falls, the first CLK pulse enables DOUT . After two null bits, the A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1196 for the next data exchange. The LTC1198 can transfer data with 3 or 4 wires. The additional input, DIN, is used to select the 2-channel MUX configuration. The data transfer between the LTC1198 and the digital systems can be broken into two sections: Input Data Word and A/D Conversion Result. First, each bit of the input data word is captured on the rising CLK edge by the LTC1198. Second, each bit of the A/D conversion result on the DOUT line is updated on the rising CLK edge by the LTC1198. This bit should be captured on the next rising CLK edge by the digital systems (see A/D Conversion Result section). Data transfer is initiated by a falling chip select (CS) signal as shown in the LTC1198 Operating Sequence. After CS falls the LTC1198 looks for a start bit. After the start bit is received, the 4-bit input word is shifted into the DIN input. The first two bits of the input word configure the LTC1198. The last two bits of the input word allow the ADC to acquire the input voltage by 2.5 clocks before the conversion starts. After the conversion starts, two null bits and the conversion result are output on the DOUT line. At CS DIN1 DOUT1 SHIFT MUX ADDRESS IN 2 NULL BITS SHIFT A/D CONVERSION RESULT OUT 1196/98 AI01 the end of the data exchange CS should be brought high. This resets the LTC1198 in preparation for the next data exchange. Input Data Word The LTC1196 requires no DIN word. It is permanently configured to have a single differential input. The conversion result is output on the DOUT line in an MSB-first sequence, followed by zeros indefinitely if clocks are continuously applied with CS low. The LTC1198 clocks data into the DIN input on the rising edge of the clock. The input data word is defined as follows: START SGL/ DIFF ODD/ SIGN DUMMY DUMMY DUMMY BITS 119698 AI02 MUX ADDRESS Start Bit The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1198 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. Multiplexer (MUX) Address The 2 bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND. LTC1198 Channel Selection DIN2 DOUT2 SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 CHANNEL # 0 1 + + – + + – GND – – 1196/98 AI03 119698fa 15 LTC1196/LTC1198 APPLICATIONS INFORMATION Dummy Bits The last 2 bits of the input word following the MUX Address are dummy bits. Either bit can be a “logical one” or a “logical zero.” These 2 bits allow the ADC 2.5 clocks to acquire the input signal after the channel selection. A/D Conversion Result Both the LTC1196 and the LTC1198 have the A/D conversion result appear on the DOUT line after two null bits (see Operating Sequence in Figures 1 and 2). Data on the DOUT line is updated on the rising edge of the CLK line. The DOUT data should also be captured on the rising CLK edge by the digital systems. Data on the DOUT line remains valid for a minimum time of thDO (30ns at 5V) to allow the capture to occur (see Figure 3). CLK VIH tdDO thDO VOH DOUT VOL 1196/98 TC03 Unipolar Output Code OUTPUT CODE 11111111 11111110 • • • 00000001 00000000 INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V INPUT VOLTAGE (VREF = 5.000V) 4.9805V 4.9609V • • • 0.0195V 0V 1196/98 AI05 Operation with DIN and DOUT Tied Together The LTC1198 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the digital systems. Data is transmitted in both directions on a single wire. The pin of the digital systems connected to this data line should be configurable as either an input or an output. The LTC1198 will take control of the data line and drive it low on the 5th falling CLK edge after the start bit is received (see Figure 4). Therefore the port line of the digital systems must be switched to an input before this happens to avoid a conflict. REDUCING POWER CONSUMPTION The LTC1196/LTC1198 can sample at up to a 1MHz rate, drawing only 50mW from a 5V supply. Power consumption can be reduced in two ways. Using a 3V supply lowers the power consumption on both devices by a factor of five, to 10mW. The LTC1198 can reduce power even further because it shuts down whenever it is not converting. Figure 5 shows the supply current versus sample rate for the LTC1196 and LTC1198 on 3V and 5V. To achieve such a low power consumption, especially for the LTC1198, several things must be taken into consideration. Shutdown (LTC1198) Figure 2 shows the operating sequence of the LTC1198. The converter draws power when the CS pin is low and powers itself down when that pin is high. For lowest power consumption in shutdown, the CS pin should be driven with CMOS levels (0V to VCC) so that the CS input buffer of the converter will not draw current. Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO Unipolar Transfer Curve The LTC1196/LTC1198 are permanently configured for unipolar only. The input span and code assignment for this conversion type are shown in the following figures. Unipolar Transfer Curve 11111111 11111110 • • • 00000001 00000000 0V 1LSB VREF VREF – 1LSB VREF – 2LSB VIN 1196/98 AI04 119698fa 16 LTC1196/LTC1198 APPLICATIONS INFORMATION CS DUMMY BITS LATCHED BY LTC1198 1 CLK 2 3 4 5 DATA (DIN/DOUT) START SGL/DIFF ODD/SIGN DUMMY THE DIGITAL SYSTEM CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1198 THE DIGITAL SYSTEM MUST RELEASE DATA LINE AFTER 5TH RISING CLK AND BEFORE THE 5TH FALLING CLK LTC1198 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO THE DIGITAL SYSTEM LTC1198 TAKES CONTROL OF DATA LINE ON 5TH FALLING CLK 1196/98 F04 Figure 4. LTC1198 Operation with DIN and DOUT Tied Together 10 LT1198 VCC = 5V Minimize CS Low Time (LTC1198) In systems that have significant time between conversions, lowest power drain will occur with the minimum CS low time. Bringing CS low, transfering data as quickly as possible, then bringing it back high will result in the lowest current drain. This minimizes the amount of time the device draws power. OPERATING ON OTHER THAN 5V SUPPLIES SUPPLY CURRENT (mA) 1 LT1196 VCC = 2.87V 0.1 LT1198 VCC = 5V 0.01 LT1198 VCC = 2.87V 0.001 100 1k 10k 100k SAMPLE RATE (Hz) 1196/98 F05 1M Figure 5. Supply Current vs Sample Rate for LTC1196/LTC1198 Operating on 5V and 2.7V Supplies The LTC1196/LTC1198 operate from single 2.7V to 6V supplies. To operate the LTC1196/LTC1198 on other than 5V supplies, a few things must be kept in mind. Input Logic Levels The input logic levels of CS, CLK and DIN are made to meet TTL on 5V supply. When the supply voltage varies, the input logic levels also change (see typical curve of Digital Input Logic Threshold vs Supply Voltage). For these two ADCs to sample and convert correctly, the digital inputs have to be in the logical low and high relative to the operating supply voltage. If achieving micropower consumption is desirable on the LTC1198, the digital inputs must go railto-rail between supply voltage and ground (see Reducing Power Consumption section). When the CS pin is high (= supply voltage), the LTC1198 is in shutdown mode and draws only leakage current. The status of the DIN and CLK input has no effect on the supply current during this time. There is no need to stop DIN and CLK with CS = high; they can continue to run without drawing current. 119698fa 17 LTC1196/LTC1198 APPLICATIONS INFORMATION Clock Frequency The maximum recommended clock frequency is 14.4MHz at 25°C for the LTC1196/LTC1198 running off a 5V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve of Maximum Clock Rate vs Supply Voltage). If the supply is reduced, the clock rate must be reduced also. At 3V the devices are specified with a 5.4MHz clock at 25°C. Mixed Supplies It is possible to have a digital system running off a 5V supply and communicate with the LTC1196/LTC1198 operating on a 3V supply. Achieving this reduces the outputs of DOUT from the ADCs to toggle the equivalent input of the digital system. The CS, CLK and DIN inputs of the ADCs will take 5V signals from the digital system without causing any problem (see typical curve of Digital Input Logic Threshold vs Supply Voltage). With the LTC1196 operating on a 3V supply, the output of DOUT only goes between 0V and 3V. This signal easily meets TTL levels (see Figure 6). 3V 4.7μF supply is clean, the LTC1196/LTC1198 can also operate with smaller 0.1μF surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single-point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. SAMPLE-AND-HOLD Both the LTC1196 and the LTC1198 provide a built-in sample-and-hold (S&H) function to acquire the input signal. The S&H acquires the input signal from “+” input during tSMPL as shown in Figures 1 and 2. The S&H of the LTC1198 can sample input signals in either single-ended or differential mode (see Figure 7). Single-Ended Inputs The sample-and-hold of the LTC1198 allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins as the bit preceding the first DUMMY bit is shifted in and continues until the falling CLK edge after the second DUMMY bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. Differential Inputs With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 8.5 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input, this error would be: VERROR(MAX) = VPEAK • 2 • π • f(“–”) • 8.5/fCLK where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. MPU (e.g., 8051) CS DIFFERENTIAL INPUTS COMMON MODE RANGE 0V TO 3V +IN –IN GND LTC1196 VCC CLK DOUT VREF 3V 1196/98 F06 5V P1.4 P1.3 P1.2 Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System BOARD LAYOUT CONSIDERATIONS Grounding and Bypassing The LTC1196/LTC1198 are easy to use if some care is taken. They should be used with an analog ground plane and single-point grounding techniques. The GND pin should be tied directly to the ground plane. The VCC pin should be bypassed to the ground plane with a 1μF tantalum with leads as short as possible. If the power 119698fa 18 LTC1196/LTC1198 APPLICATIONS INFORMATION S A M P LE “+” INPUT MUST SETTLE DURING THIS TIME CS tSMPL tCONV H O LD CLK DIN START SGL/DIFF ODD/SIGN DUMMY DUMMY DON’T CARE DOUT 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME B7 “+” INPUT “–” INPUT 1196/98 F07 Figure 7. LTC1198 “+” and “–” Input Settling Windows VERROR is proportional to f(“–”) and inversely proportional to fCLK. For a 60Hz signal on the “–” input to generate a 1/4LSB error (5mV) with the converter running at CLK = 12MHz, its peak value would have to be 18.7V. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1196/LTC1198 have one capacitive switching input current spike per conversion. These current spikes settle quickly and do not cause a problem. However, if source resistances larger than 100Ω are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. “+” Input Settling The input capacitor of the LTC1196 is switched onto “+” input at the end of the conversion and samples the input signal until the conversion begins (see Figure 1). The input capacitor of the LTC1198 is switched onto “+” input during the sample phase (tSMPL, see Figure 7). The sample phase is 2.5 CLK cycles before conversion starts. The voltage on the “+” input must settle completely within tSMPL for the LTC1196/LTC1198. Minimizing RSOURCE+ will improve the input settling time. If a large “+” input source resistance must be used, the sample time can be increased by allowing more time between conversions for the LTC1196 or by using a slower CLK frequency for the LTC1198. 119698fa 19 LTC1196/LTC1198 APPLICATIONS INFORMATION “–” Input Settling At the end of the tSMPL, the input capacitor switches to the “–” input and conversion starts (see Figures 1 and 7). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settle completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– will improve settling time. If a large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figures 1 and 7). Again, the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. To achieve the full sampling rate, the analog input should be driven with a low impedance source ( 7) LTC1198-1 PDISS PDISS (Shutdown) Max fSMPL Min tCONV INL (Max) Typical ENOBs Linear Input Bandwidth (ENOBs > 7) 50mW 15μW 750kHz 600ns 0.5LSB 7.9 at 300kHz 1MHz 10mW 9μW 287kHz 1.6μs 0.5LSB 7.9 at 100kHz 500kHz 5V 50mW 1MHz 600ns 0.5LSB 7.9 at 300kHz 1MHz 3V 10mW 383kHz 1.6μs 0.5LSB 7.9 at 100kHz 500kHz TYPICAL APPLICATIONS PLD Interface Using the Altera EPM5064 The Altera EPM5064 has been chosen to demonstrate the interface between the LTC1196 and a PLD. The EPM5064 is programmed to be a 12-bit counter and an equivalent 74HC595 8-bit shift register as shown in Figure 12. The circuit works as follows: bringing ENA high makes the CS output high and the EN input low to reset the LTC1196 and disable the shift register. Bringing ENA low, the CS output goes high for one CLK cycle with every 12 CLK cycles. The inverted signal, EN, of the CS output makes the 8-bit data available on the B0-B7 lines. Figures 13 and 14 show the interconnection between the LTC1196 and EPM5064 and the timing diagram of the signals between these two devices. The CLK frequency in this circuit can run up to fCLK(MAX) of the LTC1196. VCC 1μF 8-BIT SHIFT REGISTER DATA CLK CLK 12-BIT CONVERTER ENA ENA CS 1196/98 F12 CLK 3, 14, 25, 36 33 1 37 38 39 40 41 42 44 DATA 1 CLK EN B0-B7 B0-B7 CS +IN –IN GND LTC1196 VCC CLK DOUT VREF 8 7 6 5 ENA EPM5064 CLK DATA B7 23 34 35 + – 2 3 4 CS RESERVE PINS OF EPM5064: 2, 4-8,15-20, 22, 24, 26-30 9-13, 21, 31, 32, 43 B0 1196/98 F13 Figure 12. An Equivalent Circuit of the EPM5064 Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD 119698fa 23 LTC1196/LTC1198 TYPICAL APPLICATIONS DATA CLK CS B7 B6 B5 B4 B3 B2 B1 B0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1196/98 F14 TIME (ns) Figure 14. The Timing Diagram Interfacing the LTC1198 to the TMS320C25 DSP Figure 15 illustrates the interface between the LTC1198 8-bit data acquisition system and the TMS320C25 digital signal processor (DSP). The interface, which is optimized for speed of transfer and minimum processor supervision, can complete a conversion and shift the data in 4μs with fCLK = 5MHz. The cycle time, 4μs, of each conversion is limited by maximum clock frequency of the serial port of the TMS320C25 which is 5MHz. The supply voltage for the 5MHz CLK LTC1198 in Figure 15 can be 2.7V to 6V with fCLK = 5MHz. At 2.7V, fCLK = 5MHz will work at 25°C. See Recommended Operating Conditions for limits over temperature. Hardware Description The circuit works as follows: the LTC1198 clock line controls the A/D conversion rate and the data shift rate. Data is transferred in a synchronous format over DIN and DOUT . The serial port of the TMS320C25 is compatible with that of the LTC1198. The data shift clock lines (CLKR, CLKX) are inputs only. The data shift clock comes from an external source. Inverting the shift clock is necessary because the LTC1198 and the TMS320C25 clock the input data on opposite edges. The schematic of Figure 15 is fed by an external clock source. The signal is fed into the CLK pin of the LTC1198 directly. The signal is inverted with a 74HC04 and then applied to the data shift clock lines (CLKR, CLKX). The framing pulse of the TMS320C25 is fed directly to the CS of the LTC1198. DX and DR are tied directly to DIN and DOUT respectively. CLKX CLKR FSR TMS320C25 FSX DX DR CLK LTC1198 CS DIN DOUT CH0 CH1 1196/98 F15 Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP 119698fa 24 LTC1196/LTC1198 TYPICAL APPLICATIONS The timing diagram of Figure 16 was obtained from the circuit of Figure 15. The CLK was 5MHz for the timing diagram and the TMS320C25 clock rate was 40MHz. Figure 17 shows the timing diagram with the LTC1198 running off a 2.7V supply and 5MHz CLK. CS Software Description The software configures and controls the serial port of the TMS320C25. The code first sets up the interrupt and reset vectors. On reset the TMS320C25 starts executing code at the label INIT. Upon completion of a 16-bit data transfer, an interrupt is generated and the DSP will begin executing code at the label RINT. In the beginning, the code initializes registers in the TMS320C25 that will be used in the transfer routine. The interrupts are temporarily disabled. The data memory page pointer register is set to zero. The auxiliary register pointer is loaded with one and auxiliary register one is loaded with the value 200 hexadecimal. This is the data memory location where the data from the LTC1198 will be stored. The interrupt mask register (IMR) is configured to recognize the RINT interrupt, which is generated after receiving the last of 16 bits on the serial port. This interrupt is still disabled at this time. The transmit framing synchronization pin (FSX) is configured to be an output. The F0 bit of the status register ST1, is initialized to zero which sets up the serial port to operate in the 16-bit mode. Next, the code in TXRX routine starts to transmit and receive data. The DIN word is loaded into the ACC and shifted left eight times so that it appears as in Figure 18. This DIN word configures the LTC1198 for CH0 with respect to CH1. The DIN word is then put in the transmit register and the RINT interrupt is enabled. The NOP is repeated 3 times to mask out the interrupts and minimize the cycle time of the conversion to be 20 clock cycles. All clocking and CS functions are performed by the hardware. VERTICAL: 5V/DIV CLK DIN DOUT 1196/98 F16 NULL BITS MSB (B7) LSB (B0) HORIZONTAL: 1500ns/DIV Figure 16. Scope Trace the LTC1198 Running Off 5V Supply in the Circuit of Figure 15 CS VERTICAL: 5V/DIV CLK DIN DOUT 1196/98 F17 NULL BITS MSB (B7) LSB (B0) B15 0 1 START 0 S/D 0 O/S 0 1 DUMMY DUMMY 0 HORIZONTAL: 500ns/DIV B8 0 L1196/98 F18 Figure 17. Scope Trace the LTC1198 Running Off 1.7V Supply in the Circuit of Figure 15 Figure 18. DIN Word in ACC of TMS20C25 for the Circuit in Figure 15 119698fa 25 LTC1196/LTC1198 TYPICAL APPLICATIONS Once RINT is generated the code begins execution at the label RINT. This code stores the DOUT word from the LTC1198 in the ACC and then stores it in location 200 hex. The data appears in location 200 hex right-justified as shown in Figure 19. The code is set up to continually loop, so at this point the code jumps to label TXRX and repeats from here. LABEL MNEMONIC AORG B AORG B INIT AORG DINT LDPK LARP LRLK LACK SACL STXM FORT LACK SFSM RPTK SFL SACL EINT RPTK NOP RINT ZALS SACL B END 0 INIT >26 RINT >32 >0 >1 AR1, >200 >10 >4 0 >44 7 >1 2 >0 *, 0 TXRX MSB X X X X X X X X 7 6 5 4 3 2 1 LSB 0 > 200 DOUT FROM LTC1198 STORED IN TMS320C25 RAM L1196/98 F19 Figure 19. Memory Map for the Circuit in Figure 15 COMMENTS ON RESET CODE EXECUTION STARTS AT 0 BRANCH TO INITIALIZATION ROUTINE ADDRESS TO RINT INTERRUPT VECTOR BRANCH TO RINT SERVICE ROUTINE MAIN PROGRAM STARTS HERE DISABLE INTERRUPTS SET DATA MEMORY PAGE POINTER TO 0 SET AUXILIARY REGISTER POINTER TO 1 SET AUXILIARY REGISTER 1 TO >200 LOAD IMR CONFIG WORD INTO ACC STORE IMR CONFIG WORD INTO IMR CONFIGURE FSX AS AN OUTPUT SET SERIAL PORT TO 16-BIT MODE LOAD LTC1198 DIN WORD INTO ACC FSX PULSES GENERATED ON XSR LOAD REPEAT NEXT INSTRUCTION 8 TIMES SHIFTS DIN WORD TO RIGHT POSITION PUT DIN WORD IN TRANSMIT REGISTER ENABLE INTERRUPT (DISABLE ON RINT) MINIMIZE THE CONVERSION CYCLE TIME TO BE 20 CLOCK CYCLES STORE LTC1198 DOUT WORD IN ACC STORE ACC IN LOCATION >200 BRANCH TO TRANSMIT RECEIVE ROUTINE TXRX Figure 20. TMS320C25 Code for the Circuit in Figure 15 119698fa 26 LTC1196/LTC1198 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 8 7 6 5 .045 ±.005 .050 BSC .245 MIN .160 ±.005 .228 – .244 (5.791 – 6.197) .150 – .157 (3.810 – 3.988) NOTE 3 .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 0°– 8° TYP 1 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0303 119698fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC1196/LTC1198 RELATED PARTS PART NUMBER ADCs LTC1402 LTC1403/LTC1403A LTC1403-1/LTC1403A-1 LTC1405 LTC1407/LTC1407A LTC1407-1/LTC1407A-1 LTC1411 LTC1412 LCT1414 LTC1420 LTC1604 LTC1608 LTC1609 LTC1864/LTC1865 LTC2355-12/ LTC2355-14 LTC2356-12/LTC2356-14 DACs LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs LTC1592 References LT1790-2.5 LT1461-2.5 LT1460-2.5 Micropower Series Reference in SOT-23 Precision Voltage Reference Micropower Series Voltage Reference 0.05% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.1% Initial Accuracy, 10ppm Drift 16-Bit, Serial SoftSpan™ IOUT DAC 87dB SFDR, 20ns Settling Time ±1LSB INL/DNL, Software Selectable Spans 12-Bit, 2.2Msps Serial ADC 12-/14-Bit, 2.8Msps Serial ADCs 12-/14-Bit, 2.8Msps Serial ADCs 12-Bit, 5Msps Parallel ADC 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 14-Bit, 2.5Msps Parallel ADC 12-Bit, 3Msps Parallel ADC 14-Bit, 2.2Msps Parallel ADC 12-Bit, 10Msps Parallel ADC 16-Bit, 333ksps Parallel ADC 16-Bit, 500ksps Parallel ADC 16-Bit, 250ksps Serial ADC 16-Bit, 250ksps Serial ADCs 12-Bit, 3.5Msps Serial ADCs 12-/14-Bit, 3.5Msps Serial ADCs 5V or ±5V Supply, 4.096V or ±2.5V Span 3V, 15mW, Unipolar Inputs, MSOP Package 3V, 15mW, Bipolar Inputs, MSOP Package 5V, Selectable Spans, 115mW 3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package 3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package 5V, Selectable Spans, 80dB SINAD ±5V Supply, ±2.5V Span, 72dB SINAD ±5V Supply, ±2.5V Span, 78dB SINAD 5V, Selectable Spans, 72dB SINAD ±5V Supply, ±2.5V Span, 90dB SINAD ±5V Supply, ±2.5V Span, 90dB SINAD 5V, Configurable Bipolar/Unipolar Inputs 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package 3.3V Supply, 0V to 2.5V Span, MSOP Package 3.3V Supply, ±1.25V Span, MSOP Package DESCRIPTION COMMENTS SoftSpan is a trademark of Linear Technology Corporation. 119698fa 28 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0108 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 1993