LTC1257CN8

LTC1257 Complete Single Supply 12-Bit Voltage Output DAC in SO-8 FEATURES s s s s s s s s s DESCRIPTIO 8-Pin SO Package Buffered Voltage Output Built-In 2.048V Reference 500µV/LSB with 2.048V Full Scale 1/2LSB Max DNL Error Guaranteed 12-Bit Monotonic 3-Wire Cascadable Serial Interface Wide Single Supply Range: VCC = 4.75V to 15.75V Low Power: ICC Typ = 350µA with 5V Supply APPLICATIO S s s s The LTC ®1257 is a complete single supply, 12-bit voltage output D/A converter (DAC) in an SO-8 package. The LTC1257 includes an output buffer amplifier, 2.048V voltage reference and an easy to use three-wire cascadable serial interface. An external reference can be used to override the internal reference and extend the output voltage range to 12V. The power supply current is a low 350µA when operating from a 5V supply, making the LTC1257 ideal for battery-powered applications. The spacesaving 8-pin SO package and operation with no external components provide the smallest 12-bit D/A system available. , LTC and LT are registered trademarks of Linear Technology Corporation. Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment TYPICAL APPLICATIO Daisy-Chained Control Outputs 5V 0.5 Differential Nonlinearity vs Input Code VCC VOUT LTC1257 GND VREF DIN CLK LOAD DOUT µP DNL ERROR (LSBs) 0.1µF CONTROL OUTPUT 1 0.0 0.1µF CONTROL OUTPUT 2 VCC VOUT LTC1257 GND VREF DIN CLK LOAD DOUT –0.5 TO NEXT DAC 1257 TA01 0 512 1024 1536 2048 2560 3072 3584 4098 CODE 1257 TA05 U U U 1 LTC1257 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW CLK 1 DIN 2 LOAD 3 DOUT 4 N8 PACKAGE 8-LEAD PDIP TJMAX = 125°C, θJA = 100°C/W TOP VIEW CLK 1 DIN 2 LOAD 3 DOUT 4 8 VCC 7 VOUT 6 REF 5 GND 8 VCC 7 VOUT 6 REF 5 GND VCC to GND ............................................ – 0.5V to 16.5V TTL Input Voltage .......................... – 0.5V to VCC + 0.5V VOUT .............................................. – 0.5V to VCC + 0.5V REF ................................................ – 0.5V to VCC + 0.5V Operating Temperature Range LTC1257C ............................................. 0°C to 70°C LTC1257I ........................................ – 40°C to 85°C Maximum Junction Temperature Plastic Package ............................. – 65°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1257CN8 LTC1257IN8 LTC1257CS8 LTC1257IS8 S8 PART MARKING 1257 1257I S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 150°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted. SYMBOL DAC DNL INL OFF PARAMETER Resolution Differential Nonlinearity Integral Nonlinearity Offset Error CONDITIONS q MIN 12 TYP MAX UNITS Bits LSB LSB LSB LSB LSB mV mV LSB/°C µV/°C LSB LSB/°C V V LSB/°C LSB/ V LSB/V LSB V kΩ pF mA OFFTC Offset Error Tempco Gain Error Gain Error Tempco Guaranteed Monotonic (Note 4) LTC1257C (Note 4) LTC1257I (Note 4) When Using Internal Reference, LTC1257C When Using Internal Reference, LTC1257I When Using External Reference, LTC1257C When Using External Reference, LTC1257I When Using Internal Reference (Note 2) When Using External Reference (Note 2) (Note 2) IREF = 0, LTC1257C IREF = 0, LTC1257I IREF = 0 IREF = 0, LTC1257C IREF = 0, LTC1257I 0 ≤ IREF ≤ 100µA VCC > VREF + 2.7V (Note 2) VREF Shorted to GND q q q q q q q q q q q q q q q q q q q q ± 0.02 ± 15 0.5 ± 0.01 2.028 2.018 2.048 ± 0.06 ± 0.5 ± 3.5 ± 4.0 ±8 ±10 ±4 ±5 ± 0.066 ± 30 ±2 ± 0.02 2.068 2.078 ± 0.4 ± 0.7 ±1 12 18 90 Reference Reference Output Voltage Reference Output Tempco Reference Line Regulation Reference Load Regulation Reference Input Range Reference Input Resistance Reference Input Capacitance Short-Circuit Current 2.475 8 14 15 2 U W U U WW W LTC1257 ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted. SYMBOL VCC ICC PARAMETER Positive Supply Voltage Supply Current CONDITIONS For Specified Performance 4.75V ≤ VCC ≤ 5.25V 4.75V ≤ VCC ≤ 15.75V VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 5kΩ in Parallel with 100pF To ±1/2LSB, 5kΩ in Parallel with 100pF, VCC = 4.75V (Notes 2,3) q q q q q MIN 4.75 TYP MAX 15.75 UNITS V µA µA mA mA Ω V/µs Power Supply 350 800 600 1500 60 60 250 1.0 6 50 2.4 0.8 VCC – 1 0.4 ± 10 10 100 25 350 350 150 0 0 35 150 1.4 Note 3: DAC switched from all 1s to all 0s, and all 0s to all 1s code. Note 4: Guaranteed with internal VREF or with external VREF range of 2.475V to 12V. Tested at 10V. 500 Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital I/O VIH VIL VOH VOL ILEAK CIN t1 t2 t3 t4 t5 t6 t7 t8 fCLK Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time LOAD Pulse Width LSB CLK to LOAD LOAD High to CLK DOUT Output Delay Maximum Clock Frequency CLOAD = 15pF IOUT = –1mA, DOUT Only IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 2) V V V V µA pF ns ns ns ns ns ns ns ns MHz q q q q q µs nV/s q q q q Switching (Note 2) q q q q q q q q Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design; not subject to test. 3 LTC1257 TYPICAL PERFOR A CE CHARACTERISTICS Minimum Supply Voltage vs Load Current #1 5.0 4.8 MINIMUM SUPPLY VOLTAGE (V) MINIMUM SUPPLY VOLTAGE (V) 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 0.01 SUPPLY CURRENT (mA) VREF = INTERNAL VOUT = FULL SCALE TA = 25°C 0.1 1 OUTPUT LOAD CURRENT (mA) Supply Current vs Logic Input Voltage 0.59 VCC = 5V TA = 25°C OUTPUT VOLTAGE SWING (V) 0.54 SUPPLY CURRENT (mA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 FULL SCALE RL TIED TO GND ZERO SCALE RL TIED TO VCC OUTPUT PULL-DOWN VOLTAGE (mV) 0.49 0.44 0.39 0.34 0 1 3 2 LOGIC VOLTAGE (V) 4 5 1257 G04 Full-Scale Voltage vs Temperature 2.0495 2.0490 FULL-SCALE VOLTAGE (V) 0.9 VCC = 5V INTERNAL REFERENCE ZERO-SCALE VOLTAGE (mV) ERROR (LSB) 2.0485 2.0480 2.0475 2.0470 2.0465 –50 –25 50 25 75 0 TEMPERATURE (°C) 4 UW 100 Minimum Supply Voltage vs Load Current #2 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 0.01 0.1 1 OUTPUT LOAD CURRENT (mA) 10 1257 G02 Supply Current vs Temperature 0.38 0.37 0.36 0.35 0.34 VCC = 4.75V 0.33 0.32 0.31 –50 –25 VCC = 5V VREF = 10V VOUT = FULL SCALE TA = 25°C VCC = 5.25V 10 1257 G01 50 25 75 0 TEMPERATURE (°C) 100 125 1257 G03 Output Swing vs Load Resistance 5.0 4.5 VCC = 5V 1000 Pull-Down Voltage vs Output Sink Current Capability 100 10 HOT COLD 1 ROOM 0 10 0.1 100 1k LOAD RESISTANCE (Ω) 10k 1257 G05 1 10 100 OUTPUT SINK CURRENT (µA) 1000 1257 G06 Zero-Scale Voltage vs Temperature 2.0 VCC = 5V INTERNAL REFERENCE 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Integral Nonlinearity (INL) 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 VCC = 5V INTERNAL REFERENCE TA = 25°C 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1257 G09 125 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1257 G07 1257 G08 LTC1257 TYPICAL PERFOR A CE CHARACTERISTICS Differential Nonlinearity (DNL) REFERENCE COMPENSATION RESISTANCE (Ω) 0.5 DNL ERROR (LSBs) 0.0 30 20 10 0 0.01 –0.5 0 512 1024 1536 2048 2560 3072 3584 4098 CODE 1257 TA05 0.1 1 CL (µF) 10 100 1257 G11 0.1V/DIV PI FU CTIO S CLK (Pin 1): The TTL level input for the serial interface clock. DIN (Pin 2): The TTL level input for the serial interface data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. LOAD (Pin 3): The TTL level input for the serial interface load control. Data is loaded from the shift register into the DAC register, thus updating the DAC output when LOAD is pulled low. The DAC register is transparent as long as LOAD is held low. DOUT(Pin 4): The output of the shift register which becomes valid on the rising edge of the serial clock. The DOUT pin is driven from GND to VCC by an internal CMOS inverter. Multiple LTC1257s may be cascaded by connecting the DOUT pin to the DIN pin of the next chip. GND (Pin 5): Ground. REF (Pin 6): The output of the 2.048V reference and the input to the DAC resistor ladder. An external reference with voltage from 2.475V to VCC – 2.7V may be used to override the internal reference. VOUT (Pin 7): The buffered DAC output is capable of sourcing 2mA over temperature while pulling within 2.7V of VCC. The output will pull to ground through an internal 250Ω equivalent resistance. VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤ 15.75V. Requires a bypass capacitor to ground. UW Reference Compensation Resistance vs CL 70 60 50 40 Broadband Noise CODE = FFFH BW = 3Hz TO 1MHz GAIN = 1100 × TIME = 5ms/DIV 1257 G12 U U U 5 LTC1257 DEFI ITIO S LSB: The least significant bit or the ideal voltage difference between two successive codes. LSB = n= VOS = VFS = (VFS – VOS)/2n – 1 The number of digital input bits The zero code error or offset of the DAC The full-scale output voltage of the DAC measured when all bits are set to 1 Offset Error: The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below ground. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. OUTPUT VOLTAGE Resolution: The resolution is the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. INL: End-point integral nonlinearity is the maximum deviation from a straight line passing through the end-points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below ground, the linearity is measured between full-scale and the first code that guarantees a positive output. The INL error at a given input code is calculated as follows: INL = (VOUT – VIDEAL)/LSB VIDEAL = (Code)(LSB) + VOS VOUT = The output voltage of the DAC measured at the given input code DNL: Differential nonlinearity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB ∆VOUT = The measured voltage difference between two adjacent codes 6 U U NEGATIVE OFFSET { DAC CODE 0V 1257 F01 Figure 1. Effect of Negative Offset The offset of the part is measured at the first code that produces an output voltage 0.5LSB greater than the previous code: VOS = VOUT – [(Code)(VFS)/(2n – 1)] Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output voltages with all bits set to one (Code = 4095). The full-scale error includes the offset error and is calculated as follows: FSE = (VOUT – VIDEAL)/LSB VIDEAL = (VREF)(1 – 2–n) – VOS VREF = The reference voltage, either internal or external Gain Error: Gain error is the difference between the ideal and measured slope of the DAC transfer characteristic. Gain error is equal to full-scale error minus offset error. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). LTC1257 BLOCK DIAGRA W LOGIC SUPPLY 5V REGULATOR VCC CLK DIN 12-BIT SHIFT REGISTER 12 LOAD REF 2.048V REFERENCE 12-BIT LATCH 12 GND DOUT DAC + VOUT – 1257 BD TI I G DIAGRA CLK DIN LOAD t8 DOUT B11 (PREVIOUS WORD) W t1 t2 t6 t7 t4 t3 B11 MSB B10 B1 B0 LSB t5 B10 B1 B0 B11 CURRENT WORD 1257 TD UW 7 LTC1257 OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first and the LSB last. The DAC register loads the data from the shift register when LOAD is pulled low, and remains transparent until LOAD is pulled high and the data is latched. An internal 5V regulator provides the supply for the digital logic. By limiting the internal digital signal swings to 5V, digital noise is reduced. The buffered output of the 12-bit shift register is available on the DOUT pin which will swing from GND to VCC. Multiple LTC1257s may be daisy chained together by connecting the DOUT pin to the DIN pin of the next chip, while the clock and load signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the LOAD signal is pulled low to update all of them simultaneously. The maximum clocking rate is 1.4MHz. TYPICAL APPLICATIO S DAC with External Reference 15V IN LT1021-10 0.1µF GND OUT 0.1µF VCC CONTROL OUTPUT VREF DIN CLK LOAD DOUT 1257 TA03 VOUT LTC1257 GND 8 U U Reference The LTC1257 includes an internal 2.048V reference, making 1LSB equal to 500µV. The internal reference output is turned off when the pin is forced above the reference voltage, allowing an external reference to be connected to the reference pin. The external reference must be greater than 2.475V and less than VCC – 2.7V, and be capable of driving the 10k minimum DAC resistor ladder. If the reference output is driving a large capacitive load, a series resistor must be added to insure stability. For any capacitive load greater than 1µF, a 10Ω series resistor will suffice. Voltage Output The LTC1257 voltage output is able to pull within 2.7V of VCC while sourcing 2mA. A internal NMOS transistor with a 200Ω equivalent impedance pulls the output to ground. The output is protected against short circuits and is able to drive up to a 500pF capacitive load without oscillation. If digital noise on the output causes a problem, a simple 100Ω, 0.1µF RC circuit can be used to filter the noise. Filtering VREF and VOUT VCC DIN CLK LOAD µP VCC LTC1257 VOUT VREF 1µF 10Ω 5% 1257 TA06 100Ω 5% VOUT 0.1µF DOUT GND LTC1257 TYPICAL APPLICATIO S Auto Ranging 8-Channel ADC with Shutdown 22µF 5V CH0 8 ANALOG INPUT CHANNELS • • • VCC LTC1296 CS DOUT CLK DIN SSO µP 0.1µF 100k 2N3906 –IN VCC CS DOUT CLK LT1025A GND COMMON +IN GND VREF LTC1297 ADC CB/POWER DOWN CLK DATA DAC LOAD µP – + VIN J 10µF 1k U 5V CH7 COM REF + REF – 50k 50k 74HC04 0.1µF 100Ω 0.1µF VCC VOUT LTC1257 GND VREF DIN CLK LOAD DOUT VCC 100Ω VOUT LTC1257 GND VREF DIN CLK LOAD DOUT 1257 TA02 12-Bit Single 5V Control System with Shutdown 5V 10k 10µF 0.1µF + LTC1050 47k 1µF 1µF – 100k VCC DIN CLK LOAD DOUT 1257 TA04 VREF 74k CONTORL OUTPUT VOUT LTC1257 GND 9 LTC1257 PACKAGE DESCRIPTIO U N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 0.255 ± 0.015* (6.477 ± 0.381) 1 0.300 – 0.325 (7.620 – 8.255) 2 3 4 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 10 LTC1257 PACKAGE DESCRIPTIO U (Reference LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC SO8 1298 S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 (0.406 – 1.270) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1257 TYPICAL APPLICATI CLK 1 4 2 MOC5008 5 DIN 1 2 MOC5008 LOAD 1 2 RELATED PARTS PART NUMBER 12 Bit LTC1446/LTC1446L LTC1448 LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L LTC1659 14 Bit LTC1658 LTC1654 16 Bit LTC1655(L) DESCRIPTION Dual 12-Bit VOUT DACs in SO-8 Package Dual 12-Bit VOUT DAC in SO-8 Package, VCC: 2.7V to 5.5V Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package, VCC = 2.7V to 5.5V 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC = 2.7V to 5.5V Dual 14-Bit VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 COMMENTS LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF, REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF, REF Input Can Be Tied to VCC Output Swings from GND to REF, REF Input Can Be Tied to VCC Programmable Speed/Power, SO-8 Footprint VCC = 5V (3V), Low Power, Deglitched, VOUT = 0V to 4.096V (0V to 2.5V) 1257fb LT/TP 1101 REV B 1.5K • PRINTED IN USA 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q UO Driving LTC1257 with Optoisolators 12V 2k 5% 2k 5% 2k 5% LT1021-5 VOUT VIN 0.1µF MOC5008 CLK VCC 6 DIN VREF VOUT VOUT LOAD LTC1257 DOUT GND 6 4 5 6 4 5 1257 TA07 www.linear.com © LINEAR TECHNOLOGY CORPORATION 1994