LTC1264-7C

LTC1264-7 Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter FEATURES s s s s s DESCRIPTIO s s Steeper Roll-Off Than Bessel Filters High Speed: fC ≤ 200kHz Phase Equalized Filter in a 14-Pin Package Phase and Group Delay Response Fully Tested Transient Response Exhibits 5% Overshoot and No Ringing 65dB THD or Better Throughout a 100kHz Passband No External Components Needed The LTC1264-7 is a clock-tunable monolithic 8th order lowpass filter with linear passband phase and flat group delay. The amplitude response approximates a maximally flat passband and exhibits steeper roll-off than an equivalent 8th order Bessel filter. For instance, at twice the cutoff frequency the filter attains 28dB attenuation (vs 12dB for Bessel), while at three times the cutoff frequency the filter attains 55dB attenuation (vs 30dB for Bessel). The cutoff frequency of the LTC1264-7 is tuned via an external TTL or CMOS clock. The clock-to-cutoff frequency ratio of the LTC1264-7 can be set to 25:1 (pin 10 to V +) or 50:1 (pin 10 to V –). When the filter operates at clock-to-cutoff frequency ratio of 25:1, the input is double-sampled to lower the risk of aliasing. The LTC1264-7 is optimized for speed. Depending on the operating conditions, cutoff frequencies between 200kHz and 250kHz can be obtained. (Please refer to the Passband vs Clock Frequency graphs.) The LTC1264-7 is pin-compatible with the LTC1064-X series. APPLICATI s s s S Data Communication Filters Time Delay Networks Phase Matched Filters TYPICAL APPLICATI 1 VIN 2 3 8V 4 5 6 7 LTC1264-7 4-Level PAM Eye Diagram 14 13 12 11 10 9 8 1264-7 TA01 200kHz Linear Phase Lowpass Filter –8V fCLK = 5MHz 8V VOUT 1V/DIV NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A 0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT PIN AND THE fCLK LINE. fCLK = 5MHz fC = 200kHz U 500ns/DIV 1264-7 TA02 UO UO 1 LTC1264-7 ABSOLUTE AXI U RATI GS (Note 1) Operating Temperature Range LTC1264-7C ...................................... – 40°C to 85°C LTC1264-7M ................................... – 55°C to 125°C Lead Temperature (Soldering, 10 sec)................. 300°C Total Supply Voltage (V + to V –) .......................... 16.5V Power Dissipation............................................. 400mW Burn-In Voltage ................................................... 16.5V Voltage at Any Input ..... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V) Storage Temperature Range ............... – 65°C to 150°C PACKAGE/ORDER I FOR ATIO TOP VIEW NC VIN GND V+ NC LP (A) RIN (A) 1 2 3 4 5 6 7 14 OUT (C) 13 NC 12 V – 11 fCLK 10 25/50 9 8 VOUT NC ORDER PART NUMBER LTC1264-7CN LTC1264-7CJ LTC1264-7MJ J PACKAGE 14-LEAD CERAMIC DIP N PACKAGE 14-LEAD PLASTIC DIP TJMAX = 150°C, θJA = 65°C/W (J ) TJMAX = 110°C, θJA = 65°C/W (N ) ELECTRICAL CHARACTERISTICS PARAMETER Passband Gain Gain at 0.50 fCUTOFF (Note 3) Gain at 0.75 fCUTOFF Gain at fCUTOFF Gain at 2.0 fCUTOFF Gain with fCLK = 20kHz Gain with fCLK = 400kHz, VS = ± 2.375V Gain with fCLK = 4MHz VS = ± 7.5V, RL = 10k, TA = 25°C, fCUTOFF = 100kHz or 50kHz, fCLK = 2.5MHz, TTL or CMOS level (maximum clock rise or fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified. CONDITIONS 0.1Hz ≤ f ≤ 0.25 fCUTOFF fTEST = 25kHz, (f CLK / fC) = 25:1 fTEST = 50kHz, (f CLK / fC) = 25:1 fTEST = 25kHz, (f CLK / fC) = 50:1 fTEST = 75kHz, (f CLK / fC) = 25:1 fTEST = 100kHz, (f CLK / fC) = 25:1 fTEST = 50kHz, (f CLK / fC) = 50:1 fTEST = 200kHz, (f CLK / fC) = 25:1 fTEST = 100kHz, (f CLK / fC) = 50:1 fTEST = 200Hz, (f CLK / fC) = 50:1 fTEST = 8kHz, (fCLK / fC) = 25:1 fTEST = 16kHz, (f CLK / fC) = 25:1 fTEST = 160kHz, VIN = 1VRMS (fCLK / fC) = 25:1, TA = 0°C to 70°C (fCLK / fC) = 25:1 (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF MIN q q q q q q q q Phase Factor (F ) Phase = 180° – F (f/fC) (Note 1) Phase Nonlinearity (Note 1) 2 U U W WW U W TOP VIEW NC 1 VIN 2 GND 3 V+ 4 16 OUT (C) 15 NC 14 V – 13 NC 12 fCLK 11 25/50 10 NC 9 S PACKAGE 16-LEAD PLASTIC SOL VOUT ORDER PART NUMBER LTC1264-7CS NC 5 NC 6 LP (A) 7 RIN (A) 8 TJMAX = 110°C, θJA = 85°C/W TYP – 0.10 – 0.15 –1.0 – 3.0 – 3.0 – 28 – 30 – 0.3 0.15 – 2.70 0.00 ± 1.0 MAX 0.50 0.20 0.30 0.1 –1.9 – 2.3 – 20 – 27 0.1 0.5 – 1.4 UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB Deg Deg Deg Deg % % % % – 0.50 – 0.50 – 0.65 – 1.5 – 3.7 – 4.5 – 34 – 34 – 0.7 – 0.2 – 3.5 q 3.0 407 ± 2 388 ± 2 q q 392 374 ± 1.0 ± 1.0 423 414 q q ± 2.0 ± 2.0 LTC1264-7 ELECTRICAL CHARACTERISTICS VS = ± 7.5V, RL = 10k, TA = 25°C, fCUTOFF = 100kHz or 50kHz, fCLK = 2.5MHz, TTL or CMOS level (maximum clock rise or fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified. PARAMETER Group Delay (td) td = (F / 360)(1/fC); (Note 2, 3) Group Delay Ripple (Note 2) CONDITIONS (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1, f ≤ fCUTOFF (f CLK / fC) = 50:1, f ≤ fCUTOFF (f CLK / fC) = 25:1 (f CLK / fC) = 50:1 VS = Single 5V (GND = 2V) VS = ± 5V VS = ± 7.5V 25:1, ± 7.5V, f = fCLK VS = Single 5V VS = ± 5V VS = ± 7.5V VS = ± 2.375V VS = ± 5V VS = ± 7.5V 25:1, VS = ± 5V 50:1, VS = ± 5V 25:1, VS = ± 5V 50:1, VS = ± 5V VS = ± 2.375V VS = ± 5V q MIN TYP 11.3 21.6 MAX q q 10.9 20.8 ± 1.0 ± 1.0 11.7 22.9 q q ± 2.0 ± 2.0 Input Frequency Range (Table 9, 10) Maximum fCLK Clock Feedthrough Wideband Noise (1Hz ≤ f < fCLK) Input Impedance Output DC Voltage Swing (Note 4) Output DC Offset (fCLK = 1MHz) Output DC Offset TempCo Power Supply Current (fCLK = 1MHz) 30 q q ± 2.0 ± 3.0