LTC1279

LTC1279 12-Bit, 600ksps Sampling A/D Converter with Shutdown FEATURES s s s s s s s s s s DESCRIPTIO s Single Supply 5V or ± 5V Operation Sample Rate: 600ksps 70dB S/(N + D) and 74dB THD at Nyquist Power Dissipation: 60mW Typ Power Shutdown with Instant Wake-Up Internal Reference Can Be Overdriven Externally Internal Synchronized Clock; No Clock Required High Impedance Analog Input Input Range: 0V to 5V or ± 2.5V New Flexible, Friendly Parallel Interface Eases Connections to DSPs and FIFOs 24-Pin SO Wide Package The LTC®1279 is a 1.4µs, 600ksps, sampling 12-bit A/D converter which draws only 60mW from a single 5V or ± 5V supplies. This easy-to-use device comes complete with a 160ns sample-and-hold, a precision reference and an internally trimmed clock. Unipolar and bipolar conversion modes add to the flexibility of the ADC. The low power dissipation is reduced even more, drawing only 8.5mW in power shutdown mode. Instant wake-up from power shutdown allows the converter to be powered down even during brief inactive periods. The LTC1279 converts 0V to 5V unipolar inputs from a single 5V supply and ± 2.5V bipolar inputs from ± 5V supplies. Maximum DC specs include ± 1LSB INL and ± 1LSB DNL. Outstanding guaranteed AC performance includes 70dB S/(N + D) and 78dB THD at the input frequency of 100kHz over temperature. The internal clock is trimmed for 1.4µs conversion time. The clock automatically synchronizes to each sample command, eliminating problems with asynchronous clock noise found in competitive devices. A separate conversion start input and a data-ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATI s s s s s S High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Audio and Telecom Processing Spectrum Analysis TYPICAL APPLICATI Single 5V Supply, 600kHz, 12-Bit Sampling A/D Converter LTC1279 ANALOG INPUT 1 A AVDD (0V TO 5V) 2 IN VREF VSS 3 AGND BUSY 0.1µF 4 D11(MSB) CS 5 D10 RD 6 D9 CONVST 7 D8 SHDN 8 D7 DVDD 9 12-BIT D6 D0 PARALLEL 10 D5 D1 BUS 11 D4 D2 12 DGND D3 5V 24 23 22 21 20 19 18 17 16 15 14 13 10µF Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency 12 11 0.1µF 10µF EFFECTIVE NUMBER OF BITS 2.42V REFERENCE OUTPUT + + 10 9 8 7 6 5 4 3 2 1 0 10k µP CONTROL LINES CONVERSION-START INPUT POWER SHUTDOWN INPUT LTC1279 • TA01 U 74 68 NYQUIST FREQUENCY 62 56 50 SIGNAL/(NOISE + DISTORTION) (dB) UO UO fSAMPLE = 600kHz 100k 1M FREQUENCY (Hz) 5M 1279 G03 1 LTC1279 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW AIN VREF AGND D11(MSB) D10 D9 D8 D7 D6 1 2 3 4 5 6 7 8 9 24 AVDD 23 VSS 22 BUSY 21 CS 20 RD 19 CONVST 18 SHDN 17 DVDD 16 D0 15 D1 14 D2 13 D3 AVDD = DVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................ 7V Negative Supply Voltage (VSS) Bipolar Operation Only ......................... – 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation ................... – 0.3V to VDD + 0.3V Bipolar Operation............... VSS – 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) Unipolar Operation ............................... – 0.3V to 12V Bipolar Operation.......................... VSS – 0.3V to 12V Digital Output Voltage Unipolar Operation ................... – 0.3V to VDD + 0.3V Bipolar Operation..................... – 0.3V to VDD + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range LTC1279C............................................... 0°C to 70°C LTC1279I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER* LTC1279CSW LTC1279ISW D5 10 D4 11 DGND 12 SW PACKAGE 24-LEAD PLASTIC SO WIDE TJMAX = 110° C, θJA = 130°C/W *Consult factory for plastic DIP package. Consult factory for Military grade parts. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Bipolar Offset Error Unipolar Offset Error (Note 8) (Note 7) CONDITIONS With Internal Reference (Notes 5, 6) MIN q q q q q TYP MAX ±1 ±1 ±4 ±6 ±6 ±8 ± 15 UNITS Bits LSB LSB LSB LSB LSB LSB LSB ppm/°C 12 Gain Error Gain Error Tempco IOUT(REF) = 0 q ± 10 ± 45 A ALOG I PUT SYMBOL PARAMETER VIN IIN CIN (Note 5) CONDITIONS 4.95V ≤ VDD ≤ 5.25V (Unipolar) 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar) CS = High Between Conversions (Sample Mode) During Conversions (Hold Mode) q q q MIN TYP 0 to 5 ± 2.5 MAX UNITS V V Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance ±1 25 5 2 U µA pF pF W U U WW W U U U LTC1279 DY A IC ACCURACY SYMBOL S/(N + D) THD PARAMETER IMD I TER AL REFERE CE CHARACTERISTICS (Note 5) PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Load Regulation CONDITIONS IOUT = 0 IOUT = 0 4.95V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.95V – 5mA ≤ IOUT ≤ 800µA q DIGITAL I PUTS A D DIGITAL OUTPUTS (Note 5) SYMBOL VIH VIL IIN CIN VOH PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage VDD = 4.95V IO = – 10µA IO = – 200µA VDD = 4.95V IO = 160µA IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9 ) VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.95V VIN = 0V to VDD q q q VOL Low Level Output Voltage IOZ COZ ISOURCE ISINK High-Z Output Leakage D11 to D0 High-Z Output Capacitance D11 to D0 Output Source Current Output Sink Current U U U WU U (Notes 5, 10) CONDITIONS 100kHz Input Signal 300kHz Input Signal 100kHz Input Signal 300kHz Input Signal 100kHz Input Signal 300kHz Input Signal fIN1 = 94.189kHz, fIN2 = 97.705kHz 2nd Order Terms 3rd Order Terms fIN1 = 299.26kHz, fIN2 = 305.12kHz 2nd Order Terms 3rd Order Terms q q q MIN 70 TYP 72 70 – 82 – 74 – 82 – 80 – 81 – 78 – 77 – 74 5 500 MAX UNITS dB dB Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion First 5 Harmonics Peak Harmonic or Spurious Noise Intermodulation Distortion – 78 – 78 dB dB dB dB dB dB dB dB MHz kHz Full Power Bandwidth Full Linear Bandwidth (S/(N + D) ≥ 68dB) U MIN 2.400 TYP 2.420 ± 10 0.01 0.01 2 MAX 2.440 ± 45 UNITS V ppm/°C LSB/V LSB/V LSB/mA MIN 2.4 TYP MAX 0.8 ± 10 UNITS V V µA pF V V V V µA pF mA mA 5 4.9 q 4.0 0.05 0.10 q q q 0.4 ± 10 15 – 10 10 3 LTC1279 POWER REQUIRE E TS SYMBOL VDD VSS IDD ISS PD PARAMETER Positive Supply Voltage (Notes 11, 12) Negative Supply Voltage (Note 11, 12) Positive Supply Current Negative Supply Current Power Dissipation TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tSAMPLE(MIN) tCONV tACQ t1 t2 t3 t4 t5 PARAMETER Maximum Sampling Frequency Minimum Throughput Time (Acquisition Time Plus Conversion Time) Conversion Time Acquisition Time CS↓ to RD↓ Setup Time CS↓ to CONVST↓ Setup Time SHDN↑ to CONVST↓ Wake-Up Time CONVST Low Time CONVST↓ to BUSY↓ Delay t6 t7 t8 Data Ready Before BUSY↑ Wait Time RD↓ After BUSY↑ Data Access Time After RD↓ t9 Bus Relinquish Time t10 t11 t12 RD Low Time CONVST High Time Aperture Delay of Sample-and-Hold 4 UW (Note 5) CONDITIONS Unipolar Bipolar Bipolar Only fSAMPLE = 600ksps SHDN = 0V fSAMPLE = 600ksps, VSS = – 5V fSAMPLE = 600ksps SHDN = 0V q q q q q MIN 4.95 4.75 – 2.45 TYP MAX 5.25 5.25 – 5.25 UNITS V V V mA mA mA mW mW 12 1.7 0.12 60 8.5 24 3 0.30 120 15 UW (Note 5) CONDITIONS q q q MIN 600 TYP MAX 1.66 UNITS kHz µs µs ns ns ns 1.4 160 0 20 350 40 50 1.6 (Notes 9, 11) (Notes 9, 11) (Note 11) (Notes 11, 13) CL = 100pF Commercial Industrial CL = 20pF Mode 2, (See Figure 14) (Note 9) CL = 20pF (Note 9) Commercial Industrial CL = 100pF Commercial Industrial (3k and 10pF Connected as Shown in Test Circuits) Commercial Industrial (Note 9) (Notes 9, 13) Jitter < 50ps q q ns ns 110 130 140 ns ns ns ns ns 90 110 120 125 150 170 75 85 90 ns ns ns ns ns ns ns ns ns ns ns q q q q q q q 20 – 20 40 35 50 q q q q q q 10 10 10 t8 40 30 12 ns LTC1279 TI I G CHARACTERISTICS The q indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When the analog input voltage is taken below VSS (ground for unipolar mode) or above VDD, it will be clamped by internal diodes. This product can handle input currents greater than 80mA below VSS (ground for unipolar mode) or above VDD without latch-up. Note 4: When these pin voltages are taken below VSS (ground for unipolar mode), they will be clamped by internal diodes. This product can handle input currents greater than 60mA below VSS (ground for unipolar mode) without latch-up. These pins are not clamped to VDD. Note 5: AVDD = DVDD = VDD = 5V, (VSS = – 5V for bipolar mode), fSAMPLE = 600kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full scale specifications apply for unipolar and bipolar modes. TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity vs Output Code DIFFERENTIAL NONLINEARITY ERROR (LSB) 1.0 INTEGRAL NONLINEARITY ERROR (LSB) fSAMPLE = 600kHz 0.5 EFFECTIVE NUMBER OF BITS 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 1279 G01 UW UW (Note 5) Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 1/2LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: The AC test is for bipolar mode. The signal-to-noise plus distortion ratio is about 1dB lower for unipolar mode, so the typical S/(N + D) at 100kHz in unipolar mode is 71dB. Note 11: Recommended operating conditions. Note 12: AIN must not exceed VDD or fall below VSS by more than 50mV for specified accuracy. Therefore the minimum supply voltage for the unipolar mode is 4.95V. The minimum for the bipolar mode is 4.75V, – 2.45V. Note 13: The falling CONVST edge starts a conversion. If CONVST returns high at a bit decision point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 120ns after conversion start (i.e., before the first bit decision) or after BUSY rises (i.e., after the last bit test). See mode 1a and 1b (Figures 12 and 13) timing diagrams. Differential Nonlinearity vs Output Code 1.0 fSAMPLE = 600kHz 0.5 ENOBs and S/(N + D) vs Input Frequency 12 11 10 9 8 7 6 5 4 3 2 1 fSAMPLE = 600kHz 100k 1M FREQUENCY (Hz) 5M 1279 G03 74 68 NYQUIST FREQUENCY 62 56 50 SIGNAL/(NOISE + DISTORTION) (dB) 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 1279 G02 0 10k 5 LTC1279 TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude 80 80 VIN = 0dB 70 AMPLITUDE (dB BELOW THE FUNDAMENTAL) SIGNAL/(NOISE + DISTORTION) (dB) 70 60 50 40 30 20 10 0 10k SIGNAL-TO-NOISE RATIO (dB) VIN = – 20dB VIN = – 60dB fSAMPLE = 600kHz 100k 1M INPUT FREQUENCY (Hz) 10M 1279 G04 Peak Harmonic or Spurious Noise vs Input Frequency 0 SPURIOUS-FREE DYNAMIC RANGE (dB) –10 –20 fSAMPLE = 600kHz –40 –50 –60 –70 –80 –90 100k INPUT FREQUENCY (Hz) 1M 2M AMPLITUDE (dB) –30 –40 –50 –60 (2fa – fb) –80 (fb – fa) –70 –90 (3fb) (fa + 2fb) (2fb – fa) (fa + fb) (2fa + fb) (2fa) (2fb) (3fa) ACQUISITION TIME (ns) –100 10k Supply Current vs Temperature 15 AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) SUPPLY CURRENT, IDD (mA) REFERENCE VOLTAGE (V) 12 9 6 3 fSAMPLE = 600kHz 0 50 0 75 25 –55 –25 TEMPERATURE (°C) 6 UW 1279 G07 Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 Distortion vs Input Frequency fSAMPLE = 600kHz 60 50 40 30 20 10 0 10k fSAMPLE = 600kHz 100k 1M INPUT FREQUENCY (Hz) 10M 1279 G05 2ND HARMONIC THD 3RD HARMONIC –100 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1279 G06 Intermodulation Distortion Plot 0 –10 –20 –30 (fa) (fb) 2500 fSAMPLE = 600kHz fa = 94.189kHz fb = 97.705kHz Acquisition Time vs Source Impedance TA = 25°C 2000 1500 1000 –100 –110 –120 0 50 100 150 200 FREQUENCY (kHz) 250 300 500 0 10 100 1k SOURCE RESISTANCE (Ω) 10k 1279 G09 1279 G08 Power Supply Feedthrough vs Ripple Frequency 0 fSAMPLE = 600kHz –20 Reference Voltage vs Load Current 2.435 2.430 2.425 2.420 2.415 2.410 2.405 2.400 2.395 1M –40 –60 –80 –100 –120 VSS(VRIPPLE = 10mV) DGND(VRIPPLE = 100mV) AVDD(VRIPPLE = 1mV) 1k 10k 100k RIPPLE FREQUENCY (Hz) 100 125 2.390 –8 –7 –6 –5 –4 –3 –2 –1 LOAD CURRENT (mA) 0 1 2 1279 G10 1279 G11 1279 G12 LTC1279 PI FU CTIO S AIN (Pin 1): Analog Input. 0V to 5V (Unipolar), ± 2.5V (Bipolar). VREF (Pin 2): 2.42V Reference Output. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). AGND (Pin 3): Analog Ground. D11 to D4 (Pins 11 to 4): Three-State Data Outputs. D11 is the Most Significant Bit. DGND (Pin 12): Digital Ground. D3 to D0 (Pins 13 to 16): Three-State Data Outputs. DVDD (Pin 17 ): Digital Power Supply, 5V. Tie to AVDD pin. SHDN (Pin 18): Power Shutdown. The LTC1279 powers down when SHDN is low. CONVST (Pin 19): Conversion Start Input. It is active low. The falling edge of the CONVST signal initiates a conversion. The LTC1279 responds to CONVST signal only if the signal applied to CS is a logic low. RD (Pin 20): READ Input. A logic low signal applied to this pin enables the output data drivers when the signal applied to the CS pin is a logic low. CS (Pin 21): The CHIP SELECT input must be a logic low for the ADC to recognize the signals applied to the CONVST and RD inputs. BUSY (Pin 22): The BUSY output shows the converter status. It is a logic low during a conversion. VSS (Pin 23): Negative Supply. – 5V will select bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie to analog ground to select unipolar operation. AVDD (Pin 24): Positive Supply, 5V. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). FU CTIO AL BLOCK DIAGRA AIN CSAMPLE AVDD ZEROING SWITCH 2.42V REF VREF 12-BIT CAPACITIVE DAC COMPARATOR DVDD VSS (0V FOR UNIPOLAR MODE OR –5V FOR BIPOLAR MODE) 12 AGND DGND SUCCESSIVE APPROXIMATION REGISTER 12 OUTPUT LATCHES • • • D11 D0 INTERNAL CLOCK CONTROL LOGIC SHDN CONVST RD W U U U U U 1279 BD CS BUSY 7 LTC1279 TEST CIRCUITS Load Circuits for Access Timing 5V 3k DBN 3k DGND A) HIGH-Z TO VOH (t8) AND VOL TO VOH (t6) CL DBN CL DGND B) HIGH-Z TO VOL (t8) AND VOH TO VOL (t6) 1279 TC01 Load Circuits for Output Float Delay 5V 3k DBN 3k DGND A) VOH TO HIGH-Z 10pF DBN 10pF DGND B) VOL TO HIGH-Z 1279 TC02 TI I G DIAGRA S CS to RD Setup Timing CS t1 RD 1279 TD01 APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1279 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the acquire phase, and the comparator offset is nulled by the feedback switch. In this acquire phase, a minimum delay of 160ns will provide enough SAMPLE AIN HOLD CDAC DAC VDAC S A R CSAMPLE SAMPLE SI 8 U W W U U UW CS to CONVST Setup Timing SHDN to CONVST Wake-Up Timing CS t2 CONVST 1279 TD02 SHDN t3 CONVST 1279 TD03 – COMPARATOR + 12-BIT LATCH Figure 1. AIN Input 1279 F01 time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively com- LTC1279 APPLICATIONS INFORMATION pared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the AIN are loaded into the 12-bit output latches. DYNAMIC PERFORMANCE The LTC1279 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figures 2a and 2b show typical LTC1279 FFT plots. 0 –10 –20 –30 AMPLITUDE (dB) fSAMPLE = 600kHz fIN = 97.705kHz –40 –50 –60 –70 –80 –90 EFFECTIVE NUMBER OF BITS –100 –110 –120 0 50 100 150 200 FREQUENCY (kHz) 250 300 1279 F02a Figure 2a. LTC1279 Nonaveraged, 4096 Point FFT Plot with 100kHz Input Frequency 0 –10 –20 –30 AMPLITUDE (dB) fSAMPLE = 600kHz fIN = 292.822kHz –40 –50 –60 –70 –80 –90 –100 –110 –120 0 50 100 150 200 FREQUENCY (kHz) 250 300 1279 F02 Figure 2b. LTC1279 Nonaveraged, 4096 Point FFT Plot with 300kHz Input Frequency U W U U Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 600kHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 300kHz as shown in Figure 2b. Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the Effective Number of Bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 600kHz the LTC1279 maintains very good ENOBs up to the Nyquist input frequency of 300kHz. Refer to Figure 3. 12 11 10 9 8 7 6 5 4 3 2 1 0 10k fSAMPLE = 600kHz 100k 1M FREQUENCY (Hz) 5M 1279 G03 74 68 NYQUIST FREQUENCY 62 56 50 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency SIGNAL/(NOISE + DISTORTION) (dB) Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: 9 LTC1279 APPLICATIONS INFORMATION THD = 20log √V22 + V32 + V42 ... + VN2 V1 Figure 5 shows the IMD performance at a 100kHz input. 0 –10 –20 –30 (fa) (fb) fSAMPLE = 600kHz fa = 94.189kHz fb = 97.705kHz where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD versus input frequency is shown in Figure 4. The LTC1279 has good distortion performance up to the Nyquist frequency and beyond. AMPLITUDE (dB BELOW THE FUNDAMENTAL) AMPLITUDE (dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 THD 2ND HARMONIC 3RD HARMONIC fSAMPLE = 600kHz –100 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1279 G06 Figure 4. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while the 3rd order IMD terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD (fa ± fb) = 20log Amplitude at (fa ± fb) Amplitude at fa 10 U W U U –40 –50 –60 (2fa – fb) –80 (fb – fa) –70 –90 (3fb) (fa + 2fb) (2fb – fa) (fa + fb) (2fa + fb) (2fa) (2fb) (3fa) –100 –110 –120 0 50 100 150 200 FREQUENCY (kHz) 250 300 1279 G08 Figure 5. Intermodulation Distortion Plot Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Full Power and Full Linear Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1279 has been designed to optimize input bandwidth, allowing ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The LTC1279’s analog input is easy to drive. It draws only one small current spike while charging the sample-andhold capacitor at the end of conversion. During conversion the analog input draws no current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles in 160ns to small current transients will allow maximum speed operation. If slower LTC1279 APPLICATIONS INFORMATION op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC’s AIN input include the LT ®1360, LT1220, LT1223 and LT1224 op amps. Internal Reference The LTC1279 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.42V. It is internally connected to the DAC and is available at pin 2 to provide up to 800µA current to an external load. For minimum code transition noise, the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10µF tantalum in parallel with a 0.1µF ceramic). The VREF pin can be driven with a DAC or other means to provide input span adjustment in bipolar mode. The VREF pin must be driven to at least 2.45V to prevent conflict with the internal reference. The reference should be driven to no more than 4.8V to keep the input span within the ± 5V supplies. Figure 6 shows an LT1006 op amp driving the VREF pin. (In the unipolar mode, the input span is already 0V to 5V with INPUT RANGE ±1.033 × VREF(OUT) 5V OUTPUT CODE + LT1006 VREF(OUT) ≥ 2.45V 3Ω 10µF AIN VREF LTC1279 AGND – Figure 6. Driving the VREF with the LT1006 Op Amp INPUT RANGE ± 2.58V (= ±1.033 × VREF) OUTPUT CODE 5V VIN VOUT LT1019A-2.5 GND 3Ω 10µF –5V 1279 F07 AIN VREF LTC1279 AGND Figure 7. Supplying a 2.5V Reference Voltage to the LTC1279 with the LT1019A-2.5 U W U U the internal reference so driving the reference is not recommended, since the input span will exceed the supply and codes will be lost at the full scale.) Figure 7 shows a typical reference, the LT1019A-2.5 connected to the LTC1279. This will provide an improved drift (equal to the LT1019A-2.5’s maximum of 5ppm/°C) and a ± 2.582V full scale. UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT Figure 8a shows the ideal input/output characteristics for the LTC1279. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS – 1.5LSB). The output code is naturally binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure 8b shows the input/output transfer characteristics for the bipolar mode in two’s complement format. 111...111 111...110 111...101 111...100 1LSB = FS = 5V 4096 4096 000...011 000...010 000...001 000...000 0V UNIPOLAR ZERO 1 LSB INPUT VOLTAGE (V) FS – 1LSB 1279 F08a Figure 8a. LTC1279 Unipolar Transfer Characteristics –5V 1279 F06 011...111 011...110 BIPOLAR ZERO 5V 000...001 000...000 111...111 111...110 100...001 100...000 –FS/2 FS = 5V 1LSB = FS/4096 –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB 1279 F08b Figure 8b. LTC1279 Bipolar Transfer Characteristics 11 LTC1279 APPLICATI S I FOR ATIO Unipolar Offset and Full-Scale Error Adjustments In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 9a shows the extra components required for full-scale error adjustment. If both offset and full-scale adjustments are needed, the circuit in Figure 9b can be used. For zero offset error apply 0.61mV (i.e., 0.5LSB) at the input and adjust the offset trim until the LTC1279 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error apply an analog input of 4.99817V (i.e., FS – 1.5LSB or last code transition) at the input and adjust R5 until the LTC1279 output code flickers between 1111 1111 1110 and 1111 1111 1111. R1 50Ω V1 + A1 AIN R4 100Ω LTC1279 AGND – R2 10k R3 10k FULL-SCALE ADJUST ADDITIONAL PINS OMITTED FOR CLARITY ± 20LSB TRIM RANGE Figure 9a. Full-Scale Adjust Circuit ANALOG INPUT 0V TO 5V 5V R1 10k R2 10k R9 20Ω + AIN 10k – R4 100k R5 4.3k FULL-SCALE ADJUST R3 100k R7 100k R6 400Ω 5V R8 10k OFFSET ADJUST Figure 9b. LTC1279 Unipolar Offset and Full-Scale Adjust Circuit 12 U ANALOG INPUT R1 10k R2 10k W U UO + AIN – R4 100k LTC1279 R5 4.3k FULL-SCALE ADJUST 5V R3 R8 100k R7 100k 20k R6 200Ω OFFSET ADJUST –5V 1279 F09c Figure 9c. LTC1279 Bipolar Offset and Full-Scale Adjust Circuit Bipolar Offset and Full-Scale Error Adjustments Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Again, bipolar offset must be adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset of the op amp driving the analog input of the LTC1279 while the input voltage is 0.5LSB below ground. This is done by applying an input voltage of – 0.61mV (– 0.5LSB) to the input in Figure 9c and adjusting the R8 until the ADC output code flickers between 0000 0000 0000 and 1111 1111 1111. For full scale adjustment, an input voltage of 2.49817V (FS – 1.5LSBs) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. BOARD LAYOUT AND BYPASSING LTC1279 1279 F09a 1279 F09b Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1279, a printed circuit board is required. The printed circuit board’s layout should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital trace alongside an analog signal trace or underneath the ADC. The analog input should be screened by AGND. High quality tantalum and ceramic bypass capacitors should be used at the AVDD and VREF pins as shown in Figure 10. For the bipolar mode, a 0.1µF ceramic provides LTC1279 APPLICATI S I FOR ATIO 1 AIN AGND VREF 2 10µF ANALOG INPUT CIRCUITRY + – 3 ANALOG GROUND PLANE Figure 10. Power Supply Grounding Practice adequate bypassing for the VSS pin. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Input signal traces to AIN (pin 1) and signal return traces from AGND (pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between the signal source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. A single point analog ground, separate from the logic system ground, should be established with an analog ground plane at pin 3 (AGND) or as close as possible to the ADC. Pin 12 (DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. U LTC1279 AVDD 24 0.1µF 10µF 0.1µF DVDD 17 DGND 12 GROUND CONNECTION TO DIGITAL CIRCUITRY DIGITAL SYSTEM 1279 F10 W U UO DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 1.4µs. No external adjustments are required, and with the typical acquisition time of 160ns, throughput performance of 600ksps is assured. Power Shutdown The LTC1279 provides a power shutdown feature that saves power when the ADC is in inactive periods. To power down the ADC, pin 18 (SHDN) needs to be driven low. When in power shutdown mode, the LTC1279 will not start a conversion even though the CONVST goes low. All the power is off except the Internal Reference which is still active and provides 2.42V output voltage to the other circuitry. In this mode the ADC draws 8.5mW instead of 60mW (for minimum power, the logic inputs must be within 600mV of the supply rails). The wake-up time from the power shutdown to active state is 350ns. 13 LTC1279 APPLICATI S I FOR ATIO Timing and Control Conversion start and data read operations are controlled by three digital inputs: CS, CONVST and RD. Figure 11 shows the logic structure associated with these inputs. A logic “0” for CONVST will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is in progress. Figures 12 through 16 show several different modes of operation. In modes 1a and 1b (Figures 12 and 13) CS and RD are both tied low. The falling CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 14) CS is tied low. The falling CONVST signal again starts the conversion. Data outputs are in three-state until read by MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. RD CS D CONVST SHDN Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN CS = RD = 0 t4 SAMPLE N CONVST t5 BUSY t6 DATA DATA (N – 1) DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 1279 F12 tCONV SAMPLE N + 1 Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled. (CONVST = 14 U In Slow memory and ROM modes (Figures 15 and 16) CS is tied low and CONVST and RD are tied together. The MPU starts conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In Slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a WAIT state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor; the processor applies a logic high to RD (= CONVST) and reads the new conversion data. In ROM mode, the processor applies a logic low to RD (= CONVST), starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result (which will initiate another conversion). ACTIVE HIGH ENABLE THREE-STATE OUTPUTS DB11....DB0 BUSY Q CONVERSION START (RISING EDGE TRIGGER) FLIP FLOP CLEAR 1279 F11 W U UO ) LTC1279 APPLICATI S I FOR ATIO t11 SAMPLE N tCONV CS = RD = 0 CONVST t5 BUSY t6 DATA DATA (N – 1) DB11 TO DB0 Figure 13. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled.(CONVST = CS = 0 tCONV t4 SAMPLE N CONVST t5 BUSY t7 RD t8 DATA DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 t9 SAMPLE N + 1 t11 Figure 14. Mode 2. CONVST Starts a Conversion. Data is Read by RD CS = 0 SAMPLE N RD = CONVST t5 BUSY t8 DATA DATA (N – 1) DB11 TO DB0 t6 DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11-DB0 1279 F15 tCONV SAMPLE N + 1 Figure 15. Slow Memory Mode CS = 0 SAMPLE N RD = CONVST t5 BUSY t8 DATA DATA (N – 1) DB11 TO DB0 DATA N DB11 TO DB0 1279 F16 tCONV SAMPLE N + 1 t9 Figure 16. ROM Mode Timing Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U SAMPLE N + 1 t5 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 1279 F13 W U UO ) t10 1279 F14 t9 15 LTC1279 PACKAGE DESCRIPTIO 0.005 (0.127) RAD MIN 0.291 – 0.299 (7.391 – 7.595) (NOTE 2) 0.010 – 0.029 × 45° (0.254 – 0.737) 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). RELATED PARTS PART NUMBER LTC1272 LTC1273/ LTC1275/ LTC1276 LTC1274/ LTC1277 LTC1278 LTC1282 LTC1409 LTC1410 (12 Bit) COMMENTS Single 5V, Sampling 7572 Upgrade Complete with Clock, Reference Complete with Clock, Reference 70dB SINAD at Nyquist, Low Power 3V or ± 3V ADC with Reference, Clock Fast, Complete Low Power ADC Fast, Complete, Wideband ADC DESCRIPTION 12-Bit, 3µs, 250kHz Sampling A/D Converter 12-Bit, 300ksps Sampling A/D Converters with Reference 12-Bit, 10mW, 100ksps A/D Converters with 1µA Shutdown 12-Bit, 500ksps Sampling A/D Converter with Shutdown 3V, 140ksps 12-Bit Sampling A/D Converter with Reference 12-Bit, 800ksps Sampling A/D Converter with Shutdown 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 U Dimensions in inches (millimeters) unless otherwise noted. S Package 24-Lead Plastic SOL 0.598 – 0.614 (15.190 – 15.600) (NOTE 2) 20 19 18 17 16 24 23 22 21 15 14 13 NOTE 1 0.394 – 0.419 (10.007 – 10.643) 1 2 3 4 5 6 7 8 9 10 11 12 0.093 – 0.104 (2.362 – 2.642) 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.050 (1.270) TYP 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) SOL24 0392 LT/GP 0495 10K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1995