LTC1290DISW

LTC1290 Single Chip 12-Bit Data Acquisition System FEATURES s DESCRIPTIO s s s s Software Programmable Features – Unipolar/Bipolar Conversion – Four Differential/Eight Single-Ended Inputs – MSB- or LSB-First Data Sequence – Variable Data Word Length – Power Shutdown Built-In Sample-and-Hold Single Supply 5V or ± 5V Operation Direct Four-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports 50kHz Maximum Throughput Rate The LTC®1290 is a data acquisition component which contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology to perform either 12-bit unipolar or 11-bit plus sign bipolar A/D conversions. The 8-channel input multiplexer can be configured for either single-ended or differential inputs (or combinations thereof). An on-chip sample-and-hold is included for all single-ended input channels. When the LTC1290 is idle it can be powered down with a serial word in applications where low power consumption is desired. The serial I/O is designed to be compatible with industry standard full duplex serial interfaces. It allows either MSBor LSB-first data and automatically provides 2's complement output coding in the bipolar mode. The output data word can be programmed for a length of 8, 12 or 16 bits. This allows easy interface to shift registers and a variety of processors. , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corporation. KEY SPECIFICATIO S s s s Resolution: 12 Bits Fast Conversion Time: 13µs Max Over Temp Low Supply Current: 6.0mA TYPICAL APPLICATI SINGLE-ENDED INPUT 0V TO 5V OR ± 5V ± 15V OVERVOLTAGE RANGE* 12-Bit 8-Channel Sampling Data Acquisition System 1k CH0 CH1 CH2 CH3 DIFFERENTIAL INPUT (+) ± 5V COMMON MODE RANGE (–) CH4 CH5 LTC1290 VCC ACLK SCLK DIN DOUT CS REF + REF – V– AGND 0.1µF 1290 • TA01 • • • + 22µF TANTALUM 1N5817 TO AND FROM MICROPROCESSOR • • • CH6 CH7 COM DGND 4.7µF TANTALUM –5V 1N5817 * FOR OVERVOLTAGE PROTECTION ON ONLY ONE CHANNEL LIMIT THE INPUT CURRENT TO 15mA. FOR OVERVOLTAGE PROTECTION ON MORE THAN ONE CHANNEL LIMIT THE INPUT CURRENT TO 7mA PER CHANNEL AND 28mA FOR ALL CHANNELS. (SEE SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION SECTION.) CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED OR ANY OTHER CHANNEL IS OVERVOLTAGED (VIN < V – OR VIN > VCC). U 5V 1N4148 UO U + LT ®1027 8V TO 40V 1µF 1 LTC1290 ABSOLUTE AXI U RATI GS (Notes 1, 2) Operating Temperature Range LTC1290BC, LTC1290CC, LTC1290DC .... 0°C to 70°C LTC1290BI, LTC1290CI, LTC1290DI .... – 40°C to 85°C LTC1290BM, LTC1290CM, LTC1290DM....................................... – 55°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C Supply Voltage (VCC) to GND or V – ........................ 12V Negative Supply Voltage (V –) .................... – 6V to GND Voltage Analog/Reference Inputs ......... (V –) – 0.3V to VCC + 0.3V Digital Inputs ........................................ – 0.3V to 12V Digital Outputs ........................... – 0.3V to VCC + 0.3V Power Dissipation ............................................. 500mW PACKAGE/ORDER I FOR ATIO TOP VIEW CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 20 VCC 19 ACLK 18 SCLK 17 DIN 16 DOUT 15 CS 14 REF + 13 REF – 12 V – 11 AGND N PACKAGE 20-LEAD PDIP ORDER PART NUMBER LTC1290BMJ LTC1290CMJ LTC1290DMJ LTC1290BIJ LTC1290CIJ LTC1290DIJ LTC1290BIN LTC1290CIN LTC1290DIN LTC1290BCN LTC1290CCN LTC1290DCN CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 COM 9 DGND 10 DGND 10 J PACKAGE 20-LEAD CERAMIC DIP TJMAX = 150°C, θJA = 80°C/W (J) TJMAX = 110°C, θJA = 100°C/W (N) CO VERTER A D PARAMETER Offset Error Linearity Error (INL) Gain Error Minimum Resolution for Which No Missing Codes are Guaranteed Analog and REF Input Range On Channel Leakage Current (Note 8) ULTIPLEXER CHARACTERISTICS MIN q q q q CONDITIONS (Note 4) (Notes 4,5) (Note 4) LTC1290B TYP MAX ± 1.5 ± 0.5 ± 0.5 12 (Note 7) On Channel = 5V Off Channel = 0V On Channel = 0V Off Channel = 5V q q q q (V – ) – 0.05V to VCC + 0.05V (V –) – 0.05V to VCC + 0.05V (V –) – 0.05V to VCC + 0.05V ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 Off Channel Leakage Current (Note 8) On Channel = 5V Off Channel = 0V On Channel = 0V Off Channel = 5V 2 U U W WW U WU W TOP VIEW 20 VCC 19 ACLK 18 SCLK 17 DIN 16 DOUT 15 CS 14 REF + 13 REF – 12 V – 11 AGND ORDER PART NUMBER LTC1290BCSW LTC1290CCSW LTC1290DCSW LTC1290BISW LTC1290CISW LTC1290DISW SW PACKAGE 20-LEAD PLASTIC SO WIDE TJMAX = 110°C, θJA = 130°C/W (SW) U (Note 3) MIN LTC1290D TYP MAX ± 1.5 ± 0.75 ± 4.0 12 UNITS LSB LSB LSB Bits V µA µA µA µA MIN LTC1290C TYP MAX ± 1.5 ± 0.5 ± 1.0 12 LTC1290 AC CHARACTERISTICS SYMBOL fSCLK fACLK tACC tSMPL tCONV tCYC tdDO PARAMETER Shift Clock Frequency A/D Clock Frequency Delay time from CS ↓ to DOUT Data Valid Analog Input Sample Time Conversion Time Total Cycle Time Delay Time, SCLK↓ to DOUT Data Valid (Note 3) CONDITIONS VCC = 5V (Note 6) VCC = 5V (Note 6) (Note 9) See Operating Sequence See Operating Sequence See Operating Sequence (Note 6) See Test Circuits LTC1290BC, LTC1290CC LTC1290DC, LTC1290BI LTC1290CI, LTC1290DI q LTC1290B/LTC1290C/LTC1290D MIN TYP MAX 0 (Note 10) 2 7 52 12 SCLK + 56 ACLK 130 220 2.0 4.0 UNITS MHz MHz ACLK Cycles SCLK Cycles ACLK Cycles Cycles ns LTC1290BM, LTC1290CM q LTC1290DM tdis ten thCS thDI thDO tf tr tsuDI tsuCS tWHCS CIN Delay Time, CS↑ to DOUT Hi-Z Delay Time, 2nd ACLK↓ to DOUT Enabled Hold Time, CS After Last SCLK↓ Hold Time, DIN After SCLK↑ Time Output Data Remains Valid After SCLK↓ DOUT Fall Time DOUT Rise Time Setup Time, DIN Stable Before SCLK↑ Setup Time, CS↓ Before Clocking in First Address Bit CS High Time During Conversion Input Capacitance See Test Circuits See Test Circuits VCC = 5V (Note 6) (Notes 6, 9) VCC = 5V (Note 6) Analog Inputs On Channel Analog Inputs Off Channel Digital Inputs q q 180 70 130 0 50 50 65 25 50 2 ACLK Cycles + 100ns 52 100 5 5 270 100 200 ns ns ns ns ns ns See Test Circuits See Test Circuits VCC = 5V (Note 6) VCC = 5V (Note 6) q q 130 50 ns ns ns ACLK Cycles pF pF pF DIGITAL A D DC ELECTRICAL CHARACTERISTICS SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage High-Z Output Leakage Output Source Current CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V IO = 10µA IO = 360µA VCC = 4.75V IO = 1.6mA VOUT = VCC, CS High VOUT = 0V, CS High VOUT = 0V U (Note 3) LTC1290B/LTC1290C/LTC1290D MIN TYP MAX q q q q q q q q UNITS V V µA µA V V 2.0 0.8 2.5 – 2.5 2.4 4.7 4.0 0.4 3 –3 –20 V µA µA mA 3 LTC1290 DIGITAL A D DC ELECTRICAL CHARACTERISTICS SYMBOL ISINK ICC PARAMETER Output Sink Current Positive Supply Current CONDITIONS VOUT = VCC CS High CS High LTC1290BC, LTC1290CC Power Shutdown LTC1290DC, LTC1290BI ACLK Off LTC1290CI, LTC1290DI q q IREF I– Reference Current Negative Supply Current The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND and REF – wired together (unless otherwise noted). Note 3: VCC = 5V, VREF + = 5V, VREF – = 0V, V – = 0V for unipolar mode and – 5V for bipolar mode, ACLK = 4.0MHz unless otherwise speicfied. Note 4: These specs apply for both unipolar and bipolar modes. In bipolar mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096. For example, when VREF = 5V, 1LSB (bipolar) = 2(5V)/4096 = 2.44mV. Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 26 22 18 14 10 6 2 4 6 8 SUPPLY VOLTAGE, VCC (V) 10 1290 • TPC01 9 OFFSET ERROR (LSB = 1 • VREF) 4096 ACLK = 4MHz TA = 25°C SUPPLY CURRENT, ICC (mA) SUPPLY CURRENT, ICC (mA) 4 UW U (Note 3) LTC1290B/LTC1290C/LTC1290D MIN TYP MAX 20 6 5 12 10 UNITS mA mA µA LTC1290BM, LTC1290CM q LTC1290DM VREF = 5V CS High below V – q q 5 10 1 15 50 50 µA µA µA or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level reference or analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. Note 8: Channel leakage current is measured after the channel selection. Note 9: To minimize errors caused by noise at the chip select input, the internal circuitry waits for two ACLK falling edge after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed. Note 10: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it's recommended that fACLK ≥ 500kHz at 125°C, fACLK ≥ 125kHz at 85°C and fACLK ≥ 15kHz at 25°C. Supply Current vs Temperature 10 ACLK = 4MHz VCC = 5V Unadjusted Offset Voltage vs Reference Voltage 0.9 VCC = 5V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 1 3 2 4 REFERENCE VOLTAGE, VREF (V) 5 VOS = 0.125mV VOS = 0.25mV 8 7 6 5 4 3 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) LT1290 • TPC02 1290 • TPC03 LTC1290 TYPICAL PERFOR A CE CHARACTERISTICS Change in Linearity vs Reference Voltage LINEARITY ERROR (LSB = 1 • VREF) 4096 VCC = 5V 1.00 CHANGE IN GAIN ERROR (LSB = 1 • VREF) 4096 1.25 0 MAGNITUDE OF OFFSET CHANGE ∆OFFSET (LSB) 0.75 0.50 0.25 0 0 1 3 4 2 REFERENCE VOLTAGE, VREF (V) 5 MAGNITUDE OF LINEARITY CHANGE ∆LINEARITY (LSB) Change in Linearity Error vs Temperature MAGNITUDE OF GAIN CHANGE ∆GAIN (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) 1290 • TPC07 ACLK = 4MHz VCC = 5V VREF = 5V Maximum ACLK Frequency vs Source Resistance 5 10k VCC = 5V VREF = 5V TA = 25°C MAXIMUM RFILTER** (Ω) MAXIMUM ACLK FREQUENCY* (MHz) 4 3 2 1 0 100 1k * MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 4MHz VALUE IS FIRST DETECTED. UW Change in Gain vs Reference Voltage 0.5 Change in Offset vs Temperature ACLK = 4MHz VCC = 5V VREF = 5V –0.1 –0.2 0.4 0.3 –0.3 0.2 –0.4 VCC = 5V –0.5 1 3 2 4 REFERENCE VOLTAGE, VREF (V) 5 0.1 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) 1290 • TPC06 1290 • TPC04 1290 • TPC05 Change in Gain Error vs Temperature 0.5 ACLK = 4MHz VCC = 5V VREF = 5V 0.4 0.3 0.2 0.1 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) 1290 • TPC08 Maximum Filter Resistor vs Cycle Time 1k VIN RSOURCE – + INPUT – INPUT 100 RFILTER VIN CFILTER ≥ 1µF + – 10 10 k RSOURCE (Ω) 100k 1290 • TPC09 1.0 10 100 1000 10000 1290 • TPC10 CYCLE TIME, tCYC (µs) ** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL-SCALE ERROR FROM ITS VALUE AT RFILTER = 0 IS FIRST DETECTED. 5 LTC1290 TYPICAL PERFOR A CE CHARACTERISTICS Sample-and-Hold Acquisition Time vs Source Resistance 100 S & H AQUISITION TIME TO 0.02% (µs) SUPPLY CURRENT, ICC (µA) 7 6 5 4 3 2 1 SUPPLY CURRENT, ICC (µA) VREF = 5V VCC = 5V TA = 25°C 0V TO 5V INPUT STEP RSOURCE+ 10 VIN + – 1 100 1k RSOURCE+ (Ω) 10k LTC1290 • TPC11 Input Channel Leakage Current vs Temperature 1000 INPUT CHANNEL LEAKAGE CURRENT (nA) 2.25 800 700 600 500 400 300 200 100 ON CHANNEL OFF CHANNEL PEAK-TO-PEAK NOISE ERROR (LSBs) 900 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) 1290 • TPC14 PI FU CTIO S CH0 to CH7 (Pin 1 to Pin 8): Analog Inputs. The analog inputs must be free of noise with respect to AGND. COM (Pin 9): Common. The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and is usually tied to the analog ground plane. DGND (Pin 10): Digital Ground. This is the ground for the internal logic. Tie to the ground plane. AGND (Pin 11): Analog Ground. AGND should be tied directly to the analog ground plane. V – (Pin 12): Negative Supply. Tie V – to most negative potential in the circuit. (Ground in single supply applications.) REF –, REF + (Pins 13, 14): Reference Inputs. The reference inputs must be kept free of noise with respect to AGND. CS (Pin 15): Chip Select Input. A logic low on this input enables data transfer. DOUT (Pin 16): Digital Data Output. The A/D conversion result is shifted out of this output. 6 UW Supply Current (Power Shutdown) vs Temperature 10 9 8 ACLK OFF DURING POWER SHUTDOWN Supply Current (Power Shutdown) vs ACLK 200 180 160 140 120 100 80 60 40 20 0 3.00 1.00 2.00 ACLK FREQUENCY (MHz) 4.00 1290 • TPC13 VCC = 5V CMOS LEVELS 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE, TA (°C) 1290 • TPC12 Noise Error vs Reference Voltage 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 4 1 3 2 REFERENCE VOLTAGE, VREF (V) 5 LTC1290 NOISE 200µVP-P GUARANTEED 1290 • TPC15 U U U LTC1290 PI FU CTIO S DIN (Pin 17): Digital Data Input. The A/D configuration word is shifted into this input after CS is recognized. SCLK (Pin 18): Shift Clock. This clock synchronizes the serial data transfer. ACLK (Pin 19): A/D Conversion Clock. This clock controls the A/D conversion process. VCC (Pin 20): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. BLOCK DIAGRAM VCC 20 18 SCLK DIN 17 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 19 ACLK 12-BIT CAPACITIVE DAC ANALOG INPUT MUX 12-BIT SAR SAMPLEANDHOLD DGND TEST CIRCUITS On and Off Channel Leakage Current 5V ION A IOFF A DOUT TEST POINT POLARITY LTC1290 • TC01 U U U INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER 16 DOUT COMP 10 11 AGND 12 V– 13 REF – 14 REF+ CONTROL AND TIMING 15 CS LTC1290 • BD Load Circuit for tdis and ten ON CHANNEL 3k 100pF 5V WAVEFORM 2 WAVEFORM 1 • • • • OFF CHANNELS LTC1290 • TC02 7 LTC1290 TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO SCLK 0.8V tdDO 2.4V DOUT 0.4V LTC1290 • TC03 Voltage Waveform for DOUT Rise and Fall Times, tr, tf DOUT 2.4V 0.4V tr tf LTC1290 • TC04 Load Circuit for tdDO, tr and tf 1.4V 3k DOUT 100pF 1290 • TC05 TEST POINT Voltage Waveforms for ten and tdis 1 ACLK 2 CS 2.0V DOUT WAVEFORM 1 (SEE NOTE 1) ten DOUT WAVEFORM 2 (SEE NOTE 2) 2.4V tdis 0.8V 90% 10% LTC1290 • TC06 NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 8 LTC1290 APPLICATI S I FOR ATIO U of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion is delayed by one CS cycle from the input word requesting it. DIN DOUT DIN WORD 1 DOUT WORD 0 DATA TRANSFER tCONV A/D CONVERSION DIN WORD 2 DOUT WORD 1 DATA TRANSFER tCONV A/D CONVERSION LTC1290 • AI01 The LTC1290 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, full duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS Serial Interface The LTC1290 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four-wire serial interface (see Operating Sequence). The shift clock (SCLK) synchronizes the data transfer with each bit being transmitted on the falling SCLK edge and captured on the rising SCLK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). Data transfer is initiated by a falling chip select (CS) signal. After the falling CS is recognized, an 8-bit input word is shifted into the DIN input which configures the LTC1290 for the next conversion. Simultaneously, the result of the previous conversion is output on the DOUT line. At the end Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length) tCYC 1 SCLK tSMPL CS 2 3 4 5 6 7 8 9 10 11 12 DON’T CARE tCONV DIN DOUT SHIFT CONFIGURATION WORD IN W U UO DIN WORD 3 DOUT WORD 2 Input Data Word The LTC1290 8-bit data word is clocked into the DIN input on the first eight rising SCLK edges after chip select is recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The eight bits of the input word are defined as follows: UNIPOLAR/ BIPOLAR SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 WORD LENGTH UNI MSBF WL1 WL0 MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1290 • AI02 DON’T CARE B11 B10 B9 (SB) B8 B7 B6 B5 B4 B3 B2 B1 B0 SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN LTC1290 • AI03 9 LTC1290 APPLICATI MUX Address S I FOR ATIO The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and – signs in the selected row of Table 1. Note that in differential Table 1. Multiplexer Channel Selection MUX ADDRESS SGL/ ODD SELECT DIFF SIGN 1 0 0 0 00 0 0 01 0 0 10 0 0 11 0 1 00 0 1 01 0 1 10 0 1 11 DIFFERENTIAL CHANNEL SELECTION 0 + 1 – + – + – + – + – + – + – + – 2 3 4 5 6 7 4 Differential CHANNEL 0,1 { { { { 2,3 + (– ) – (+ ) + (– ) – (+ ) + (– ) – (+ ) + (– ) – (+ ) 4,5 CHANNEL 0 1 2 3 4 5 6 7 6,7 Changing the MUX Assignment “On the Fly” 4,5 { { 6,7 + – + – COM (UNUSED) 1ST CONVERSION Figure 1. Examples of Multiplexer Options on the LTC1290 10 U mode (SGL/DIFF = 0) measurements are limited to four adjacent input pairs with either polarity. In single-ended mode, all input channels are measured with respect to COM. MUX ADDRESS SGL/ ODD SELECT DIFF SIGN 1 0 1 0 00 1 0 01 1 0 10 1 0 11 1 1 00 1 1 01 1 1 10 1 1 11 SINGLE-ENDED CHANNEL SELECTION 0 + + + + + + + + 1 2 3 4 5 6 7 COM – – – – – – – – W U UO 8 Single-Ended Combinations of Differential and Single-Ended CHANNEL 0,1 + + + + + + + + COM (–) { { 4 5 6 7 + – – + + + + + COM (–) 2,3 5,4 6 7 { { – + + + COM (–) 2ND CONVERSION LTC1290 • F01 LTC1290 APPLICATI S I FOR ATIO U input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for each conversion type are shown in the figures below. Unipolar Transfer Curve (UNI = 1) 111111111111 111111111110 Unipolar/Bipolar (UNI) The fifth input bit (UNI) determines whether the conversion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the selected Unipolar Output Code (UNI = 1) INPUT VOLTAGE (VREF = 5V) 4.9988V 4.9976V • • • 0.0012V 0V LTC1290 • AI04a OUTPUT CODE 111111111111 111111111110 • • • 000000000001 000000000000 INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V OUTPUT CODE 011111111111 011111111110 • • • 000000000001 000000000000 INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V W U UO –VREF • • • 000000000001 000000000000 0V 1LSB VREF VREF – 1LSB VREF – 2LSB VIN LTC1290 AI04b Bipolar Output Code (UNI = 0) INPUT VOLTAGE (VREF = 5V) 4.9976V 4.9851V • • • 0.0024V 0V OUTPUT CODE 111111111111 111111111110 • • • 100000000001 100000000000 INPUT VOLTAGE –1LSB –2LSB • • • –(VREF) + 1LSB – (VREF) INPUT VOLTAGE (VREF = 5V) –0.0024V –0.0048V • • • –4.9976V –5.0000V LTC1290 AI05a Bipolar Transfer Curve (UNI = 0) 011111111111 011111111110 1LSB • • • 000000000001 000000000000 –VREF + 1LSB VIN VREF VREF – 1LSB VREF – 2LSB 111111111111 111111111110 • • • 100000000001 100000000000 –2LSB –1LSB LTC1290 AI05b 11 LTC1290 APPLICATI S I FOR ATIO U resumed once CS goes low or an SCLK is applied, if CS is already low. WL1 0 0 1 1 WL0 0 1 0 1 OUTPUT WORD LENGTH 8-Bits Power Shutdown 12-Bits 16-Bits MSB-First/LSB-First Format (MSBF) The output data of the LTC1290 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. For MSB first output data the input word clocked to the LTC1290 should always contain a logical one in the sixth bit location (MSBF bit). Likewise for LSB-first output data the input word clocked to the LTC1290 should always contain a zero in the MSBF bit location. The MSBF bit affects only the order of the output data word. The order of the input word is unaffected by this bit. MSBF 0 1 OUTPUT FORMAT LSB First MSB First Word Length (WL1, WL0) and Power Shutdown The last two bits of the input word (WL1 and WL0) program the output data word length and the power shutdown feature of the LTC1290. Word lengths of 8, 12 or 16 bits can be selected according to the following table. The WL1 and WL0 bits in a given DIN word control the length of the present, not the next, DOUT word. WL1 and WL0 are never “don’t cares” and must be set for the correct DOUT word length even when a “dummy” DIN word is sent. On any transfer cycle, the word length should be made equal to the number of SCLK cycles sent by the MPU. Power down will occur when WL1 = 0 and WL0 = 1 is selected. The previous conversion result will be clocked out as a 10 bit word so a “dummy”conversion is required before powering down the LTC1290. Conversions are Low CS Recognized Internally ACLK CS DOUT HI-Z 12 W U UO Deglitcher A deglitching circuit has been added to the Chip Select input of the LTC1290 to minimize the effects of errors caused by noise on that input. This circuit ignores changes in state on the CS input that are shorter in duration than one ACLK cycle. After a change of state on the CS input, the LTC1290 waits for two falling edge of the ACLK before recognizing a valid chip select. One indication of CS recognition is the DOUT line becoming active (leaving the Hi-Z state). Note that the deglitching applies to both the rising and falling CS edges. CS Low During Conversion In the normal mode of operation, CS is brought high during the conversion time. The serial port ignores any SCLK activity while CS is high. The LTC1290 will also operate with CS low during the conversion. In this mode, SCLK must remain low during the conversion as shown in the following figure. After the conversion is complete, the DOUT line will become active with the first output bit. Then the data transfer can begin as normal. High CS Recognized Internally ACLK CS VALID OUTPUT LTC1290 • AI06 DOUT VALID OUTPUT HI-Z LTC1290 • AI07 LTC1290 APPLICATI S I FOR ATIO 8-Bit Word Length tSMPL CS tCONV SCLK 1 (SB) DOUT MSB-FIRST B11 B10 B9 B8 B7 DOUT LSB-FIRST B0 B1 B2 B3 B4 12-Bit Word Length tSMPL CS tCONV SCLK 1 (SB) DOUT MSB-FIRST B11 B10 B9 B8 B7 DOUT LSB-FIRST B0 B1 B2 B3 B4 16-Bit Word Length tSMPL CS tCONV SCLK 1 (SB) DOUT MSB-FIRST B11 B10 B9 B8 B7 DOUT LSB-FIRST B0 B1 B2 B3 B4 * IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROS. IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS. Figure 2. Data Output (DOUT) Timing with Different Word Lengths U 8 B6 B5 B4 THE LAST FOUR BITS ARE TRUNCATED B5 B6 B7 10 12 B6 B5 B4 B3 B2 B1 B0 (SB) B5 B6 B7 B8 B9 B10 B11 12 16 B6 B5 B4 B3 B2 B1 B0 (SB) B5 B6 B7 B8 B9 B10 B11 * * * FILL ZEROS LTC1290 F02 W U UO 13 LTC1290 APPLICATI S I FOR ATIO tSMPL SAMPLE ANALOG INPUT SHIFT MUX ADDRESS IN CS SCLK DIN DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 DON’T CARE B1 Figure 3. CS High During Conversion SHIFT MUX ADDRESS IN CS tSMPL SAMPLE ANALOG INPUT SCLK DIN DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 DON’T CARE B1 Figure 4. CS Low During Conversion (CS Must go High to Low Once to Insure Proper Operation in this Mode) Microprocessor Interfaces The LTC1290 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats (see Table 2). If an MPU without a serial interface is used, then four of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1290. Included here are two serial interface examples and one example showing a parallel port programmed to form the serial interface 14 U 48 TO 52 ACLK CYC SHIFT RESULT OUT AND NEW ADDRESS IN B0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LTC1290 F03 W U UO 48 TO 52 ACLK CYC SHIFT RESULT OUT AND NEW ADDRESS IN SCLK MUST REMAIN LOW B0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LTC1290 F04 Serial Port Microprocessors Most synchronous serial formats contain a shift clock (SCLK) and two data lines, one for transmitting and one for receiving. In most cases data bits are transmitted on the falling edge of the clock (SCLK) and captured on the rising edge. However, serial port formats vary among MPU manufactures as to the smallest number of bits that can be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers). They also vary as to the order in which the bits are transmitted (LSB or MSB first). The following examples show how the LTC1290 accommodates these differences. LTC1290 APPLICATI S I FOR ATIO Table 2. Microprocessors with Hardware Serial Interfaces Compatible with the LTC1290** PART NUMBER Motorola MC6805S2, S3 MC68HC11 MC68HC05 RCA CDP68HC05 Hitachi HD6305 HD6301 HD63701 HD6303 HD64180 National Semiconductor COP400 Family COP800 Family NS8050U HPC16000 Family Texas Instruments TMS7002 TMS7042 TMS70C02 TMS70C42 TMS32011* TMS32020 TMS370C050 Serial Port Serial Port Serial Port Serial Port Serial Port Serial Port SPI MICROWIRETM MICROWIRE/PLUSTM MICROWIRE/PLUS MICROWIRE/PLUS SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SPI SPI SPI SPI TYPE OF INTERFACE *Requires external hardware ** Contact factory for interface information for processors not on this list Hardware and Software Interface to COP402 Processor LTC1290 CS • • • • SCLK DIN DOUT GO SK SO SI LTC1290 • AI08 COP402 ANALOG INPUTS DOUT from LTC1290 Stored in COP402 RAM MSB† LOCATION $13 B11 B10 B9 B8 FIRST 4 BITS LOCATION $14 B7 B6 B5 B4 LSB SECOND 4 BITS LOCATION $15 † B3 B2 B1 B0 THIRD 4 BITS MICROWIRE and MICROWIRE PLUS are trademarks of National Semiconductor Corp B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR U National MICROWIRE (COP402) The COP402 transfers data MSB first and in 4-bit increments (nibbles). This is easily accommodated by setting the LTC1290 to MSB-first format and 12-bit word length. The data output word is then received by the COP402 in three 4-bit blocks. COP402 Code MNEMONIC CLRA LBI STII STII STII LEI SC LDD OGI XAS LDD NOP XAS XIS LDD XAS XIS RC CLRA XAS OGI XIS LBI 1,0 8 E 0 C 1,0 0 1,1 COMMENTS Must be First Instruction BR = 1BD = 0 Initialize B Reg. First DIN Nibble in $10 Second DIN Nibble in $11 Null Data in $12, B = $13 Set EN to (1100) BIN Carry Set Load First DIN Nibble In ACC Go (CS) Cleared ACC to Shift Reg. Begin Shift Load Next DIN Nibble in ACC Timing Next Nibble, Shift Continues First Nibble DOUT to $13 Put Null Data in ACC Shift Continues, DOUT to ACC Next Nibble DOUT to $14 Clear Carry Clear ACC Third Nibble DOUT to ACC Go (CS) Set Third Nibble DOUT to $15 Set B Reg. For Next Loop LOOP 0 1,2 0 1 0 1,3 W U UO Motorola SPI (MC68HC05C4) The MC68HC05C4 transfers data MSB first and in 8-bit increments. Programming the LTC1290 for MSB-first format and 16-bit word length allows the 12-bit data output to be received by the MPU as two 8-bit bytes with the final four unused bits filled with zeros by the LTC1290. 15 LTC1290 APPLICATI S I FOR ATIO MC68HC05C4 CS • • • • SCLK DIN DOUT CO SCK MOSI MISO LTC1290 • AI09 Hardware and Software Interface to Motorola MC68HC05C4 Processor LTC1290 ANALOG INPUTS DOUT from LTC1290 Stored in MC68HC05C4 RAM MSB* LOCATION $61 B11 B10 B9 B8 B7 B6 B5 B4 BYTE 1 LSB LOCATION $62 B3 B2 B1 B0 0 0 0 0 BYTE 2 *B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR DOUT P1.1 P1.2 P1.3 P1.4 ALE LTC1290 • AI10 MC68HC05C4 Code MNEMONIC LDA STA LDA STA LDA STA BCLR LDA STA NOP LDA LDA STA STA NOP BSET LDA LDA STA 0,$02 $0B $0C $62 $0B $0C $61 $0C #$50 $0A #$FF $06 #$0F $50 0,$20 $50 $0C COMMENTS Configuration Data for SPCR Load Data Into SPCR ($0A) Config. Data for Port C DDR Load Data Into Port C DDR Load LTC1290 DIN Data Into ACC Load LTC1290 DIN Data Into $50 CO Goes Low (CS Goes Low) Load DIN Into ACC from $50 Load DIN Into SPI, Start SCK 8 NOPs for Timing Check SPI Status Reg Load LTC1290 MSBs Into ACC Store MSBs in $61 Start Next SPI Cycle 6 NOPs for Timing CO Goes High (CS Goes High) Check SPI Status Register Load LTC1290 LSBs Into ACC Store LSBs in $62 ANALOG INPUTS START 16 U Parallel Port Microprocessors When interfacing the LTC1290 to an MPU which has a parallel port, the serial signals are created on the port with software. Three MPU port lines are programmed to create the CS, SCLK and DIN signals for the LTC1290. A fourth port line reads the DOUT line. An example is made of the Intel 8051/8052/80C252 family. Intel 8051 To interface to the 8051, the LTC1290 is programmed for MSB-first format and 12-bit word length. The 8051 generates CS, SCLK and DIN on three port lines and reads DOUT on the fourth. Hardware and Software Interface to Intel 8051 Processor LTC1290 8051 • • • • • • • • DIN SCLK CS ACLK W U UO DOUT from LTC1290 Stored in 8051 RAM MSB* R2 B11 B10 B9 B8 B7 B6 B5 54 LSB R3 B3 B2 B1 B0 0 0 0 0 *B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR LTC1290 APPLICATI 8051 Code MNEMONIC MOV CLR SETB MOV CLR MOV NOP MOV RLC MOV SETB CLR DJNZ MOV MOV CLR RLC SETB CLR MOV RLC SETB CLR MOV RLC SETB CLR MOV RRC RRC RRC RRC MOV SETB CLR SETB P1,#02H P1.3 P1.4 A,#0EH P1.4 R4,#08H C,P1.1 A P1.2,C P1.3 P1.3 R4,LOOP R2,A C,P1.1 A A P1.3 P1.3 C,P1.1 A P1.3 P1.3 C,P1.1 A P1.3 P1.3 C, P1.1 A A A A R3,A P1.3 P1.3 P1.4 COMMENTS Bit 1 Port 1 Set as Input SCLK Goes Low CS Goes High DIN Word for LTC1290 CS Goes Low Load Counter Delay for Deglitcher Read Data Bit Into Carry Rotate Data Bit Into ACC Output DIN Bit to LTC1290 SCLK Goes High SCLK Goes Low Next Bit Store MSBs in R2 Read Data Bit Into Carry Clear ACC Rotate Data Bit Into ACC SCLK Goes High SCLK Goes Low Read Data Bit Into Carry Rotate Data Bit Into ACC SCLK Goes High SCLK Goes Low Read Data Bit Into Carry Rotate Data Bit Into ACC SCLK Goes High SCLK Goes Low Read Data Bit Into Carry Rotate Right Into ACC Rotate Right Into ACC Rotate Right Into ACC Rotate Right Into ACC Store LSBs in R3 SCLK Goes High SCLK Goes Low CS Goes High Load Counter Go to Delay if Not Done S I FOR ATIO CONT LOOP DELAY MOV R5,#0BH DJNZ R5,DELAY 2 1 0 3-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1290s CS LTC1290 8 CHANNELS OUTPUT PORT SERIAL DATA 3 3 CS LTC1290 8 CHANNELS 3 CS LTC1290 8 CHANNELS 3 MPU Figure 5. Several LTC1290s Sharing One 3-Wire Serial Interface U Sharing the Serial Interface The LTC1290 can share the same 3-wire serial interface with other perpheral components or other LTC1290s (see Figure 5). In this case, the CS signals decide which LTC1290 is being addressed by the MPU. ANALOG CONSIDERATIONS 1. Grounding The LTC1290 should be used with an analog ground plane and single point grounding techniques. AGND (Pin 11) should be tied directly to this ground plane. DGND (Pin 10) can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. VCC (Pin 20) should be bypassed to the ground plane with a 22µF tantalum with leads as short as possible. V – (Pin 12) should be bypassed with a 0.1µF ceramic disk. For single supply applications, V – can be tied to the ground plane. It is also recommended that REF – (Pin 13) and COM (Pin 9) be tied directly to the ground plane. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. LTC1290 F05 W U UO 17 LTC1290 APPLICATI S I FOR ATIO VCC 22µF TANTALUM VERTICAL: 0.5mV/DIV 1 20 V– 10 ANALOG GROUND PLANE 0.1µF CERAMIC DISK Figure 6. Example Ground Plane for the LTC1290 Figure 6 shows an example of an ideal ground plane design for a two-sided board. Of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. Bypassing For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. VCC noise and ripple can be kept below 0.5mV by bypassing the VCC pin directly to the analog ground plane with a 22µF tantalum capacitor and leads as short as possible. The lead from the device to the VCC supply should also be kept to a minimum and the VCC supply should have a low output impedance such as that obtained from a voltage regulator (e.g., LT323A). Figures 7 and 8 show the effects of good and poor VCC bypassing. 3. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1290 have capacitive switching input current spikes. These current VERTICAL: 0.5mV/DIV 18 U HORIZONTAL: 10µs/DIV W U UO Figure 7. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors LTC1290 F06 CS VCC HORIZONTAL: 10µs/DIV Figure 8. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. Source Resistance The analog inputs of the LTC1290 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON) as shown in Figure 9. CIN gets switched between the selected “+” and “–” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. LTC1290 APPLICATI RSOURCE + VIN + C1 “–” INPUT 4TH SCLK RON = 500Ω LAST SCLK CIN = 100pF S I FOR ATIO “+” INPUT LTC1290 RSOURCE – VIN – C2 LTC1290 F09 Figure 9. Analog Input Equivalent Circuit “+” Input Settling This input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 10). The sample phase starts at the 4th SCLK cycle and lasts until the falling edge of the last SCLK (the 8th, 12th or 16th SCLK cycle depending on the selected word length). The voltage on the “+” input must settle completely within this sample time. Minimizing RSOURCE+ and C1 will improve the input settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower SCLK frequency or selecting a longer word length. With the minimum possible sample time of 2µs, RSOURCE+ < 1k and C1 < 20pF will provide adequate settling. SAMPLE MUX ADDRESS SHIFTED IN CS “+” INPUT MUST SETTLE DURING THIS TIME tSMPL ••• SCLK 1 2 3 4 ••• ACLK ••• “+” INPUT “–” INPUT 1290 • F10 Figure 10. “+” and “–” Input Settling Windows U “–” Input Settling W U UO At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figure 10). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage be free of noise and settle completely during the first four ACLK cycles of the conversion time. Minimizing RSOURCE– and C2 will improve settling time. If large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower ACLK frequency. At the maximum ACLK rate of 4MHz, RSOURCE– < 250Ω and C2 < 20pF will provide adequate settling. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 10). Again, the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 2µs (“+” input) and 1µs (“–” input) which occur at the maximum HOLD LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORD LENGTH) 1 2 3 4 ••• 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME 19 LTC1290 APPLICATI S I FOR ATIO clock rates (ACLK = 4MHz and SCLK = 2MHz). Figures 11 and 12 show examples of adequate and poor op amp settling. VERTICAL: 5mV/DIV HORIZONTAL: 500ns/DIV Figure 11. Adequate Settling of Op Amps Driving Analog Input VERTICAL: 5mV/DIV HORIZONTAL: 20µs/DIV Figure 12. Poor Op Amp Settling Can Cause A/D Errors RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 13. For large values of CF (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = (100pF)(VIN/tCYC) and is roughly proportional to VIN. When running at the minimum cycle time of 20µs, the input current equals 25µA at VIN = 5V. In this case, a filter resistor of 5Ω will cause 0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve of Maximum Filter Resistor vs Cycle Time. 20 U RFILTER VIN CFILTER IDC "+" LTC1290 "–" LTC1290 F13 W U UO Figure 13. RC Input Filtering Input Leakage Current Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1kΩ will cause a voltage drop of 1mV or 0.8LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see the typical curve of Input Channel Leakage Current vs Temperature). Noise Coupling Into Inputs High source resistance input signals (>500Ω) are more sensitive to coupling from external sources. It is preferable to use channels near the center of the package (i.e., CH2 to CH7) for signals which have the highest output resistance because they are essentially shielded by the pins on the package ends (DGND and CH0). Grounding any unused inputs (especially the end pin, CH0) will also reduce outside coupling into high source resistances. 4. Sample-and-Hold Single-Ended Inputs The LTC1290 provides a built-in sample-and-hold (S&H) function for all signals acquired in the single-ended mode (COM pin grounded). This sample-and-hold allows the LTC1290 to convert rapidly varying signals (see the typical curve of S&H Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 10. The sampling interval begins after the fourth MUX address bit is shifted in and continues during the remainder of the data transfer. On the falling edge of the final SCLK, the S&H goes into hold mode and the conversion begins. The voltage will be held on either the 8th, 12th or 16th falling edge of the SCLK depending on the word length selected. LTC1290 APPLICATI S I FOR ATIO Differential Inputs With differential inputs or when the COM pin is not tied to ground, the A/D no longer converts just a single voltage but rather the difference between two voltages. In these cases, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in singleended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 52 ACLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input this error would be: VERROR (MAX) = (VPEAK)(2π)[ f(“–”)](52/fACLK) Where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fACLK is the frequency of the ACLK. In most cases VERROR will not be significant. For a 60Hz signal on the “–” input to generate a 0.25LSB error (300µV) with the converter running at ACLK = 4MHz, its peak value would have to be 61mV. 5. Reference Inputs The voltage between the reference inputs of the LTC1290 defines the voltage span of the A/D converter. The reference inputs will have transient capacitive switching currents due to the switched capacitor conversion technique (see Figure 14). During each bit test of the conversion (every 4 ACLK cycles), a capacitive current spike will be generated on the reference pins by the A/D. These current spikes settle quickly and do not cause a problem. However, if slow settling circuitry is used to drive the reference inputs, care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion. REF+ 14 ROUT VREF REF– 13 LTC1290 EVERY 4 ACLK CYCLES RON 8pF TO 40pF VERTICAL: 0.5mV/DIV VERTICAL: 0.5mV/DIV LTC 1290 F14 Figure 14. Reference Input Equivalent Circuit U When driving the reference inputs, two things should be kept in mind: 1. Transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each 4 ACLK cycles). Figures 15 and 16 show examples of both adequate and poor settling. Using a slower ACLK will allow more time for the reference to settle. However, even at the maximum ACLK rate of 4MHz most references and op amps can be made to settle within the 1µs bit time. For example the LT1027 will settle adequately or with a 10µF bypass capacitor at REF + the LT1021 can also be used. 2. It is recommended that REF – input be tied directly to the analog ground plane. If REF – is biased at a voltage other than ground, the voltage must not change during a conversion cycle. This voltage must also be free of noise and ripple with respect to analog ground. HORIZONTAL: 1µs/DIV W U UO Figure 15. Adequate Reference Settling HORIZONTAL: 1µs/DIV Figure 16. Poor Reference Settling Can Cause A/D Errors 21 LTC1290 APPLICATI S I FOR ATIO 6. Reduced Reference Operation The effective resolution of the LTC1290 can be increased by reducing the input span of the converter. The LTC1290 exhibits good linearity and gain over a wide range of reference voltages (see the typical curves of Linearity and Gain Error vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: 1. Offset 2. Noise Offset with Reduced VREF The offset of the LTC1290 has a larger effect on the output code when the A/D is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 0.1mV which is 0.1LSB with a 5V reference becomes 0.4LSB with a 1.25V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “–” input to the LTC1290. Noise with Reduced VREF The total input referred noise of the LTC1290 can be reduced to approximately 200µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise. For operation with a 5V reference, the 200µV noise is only 0.16LSB peak-to-peak. In this case, the LTC1290 noise will contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference, this same 200µV noise is 0.64LSB peak-to-peak. This will 22 U reduce the range of input voltages over which a stable output code can be achieved by 0.64LSB. In this case averaging readings may be necessary. This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, VREF, VIN or V –) will add to the internal noise. The lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. 7. LTC1290 AC Characteristics Two commonly used figures of merit for specifying the dynamic performance of the A/D’s in digital signal processing applications are the Signal-to-Noise Ratio (SNR) and the “effective number of bits (ENOB).” SNR is defined as the ratio of the RMS magnitude of the fundamental to the RMS magnitude of all the nonfundamental signals up to the Nyquist frequency (half the sampling frequency). The theoretical maximum SNR for a sine wave input is given by: SNR = (6.02N + 1.76dB) where N is the number of bits. Thus the SNR is a function of the resolution of the A/D. For an ideal 12-bit A/D the SNR is equal to 74dB. A Fast Fourier Transform(FFT) plot of the output spectrum of the LTC1290 is shown in Figures 17a and 17b. The input (fIN) frequencies are 1kHz and 25kHz with the sampling frequency (fS) at 50.6kHz. The SNR obtained from the plot are 73.25dB and 72.54dB. Rewriting the SNR expression it is possible to obtain the equivalent resolution based on the SNR measurement. N = (SNR – 1.76dB)/6.02 This is the so-called effective number of bits (ENOB). For the example shown in Figures 17a and 17b, N = 11.9 bits and 11.8 bits, respectively. Figure 18 shows a plot of ENOB as a function of input frequency. The curve shows the A/D’s ENOB remain in the range of 11.9 to 11.8 for input frequencies up to fS/2. Figure 19 shows an FFT plot of the output spectrum for two tones applied to the input of the A/D. Nonlinearities in the A/D will cause distortion products at the sum and difference frequencies of the fundamentals and products of the W U UO LTC1290 APPLICATI 0 –20 MAGNITUDE (dB) S I FOR ATIO fIN = 1kHz fSAMPLE = 50.6kHz SNR = 73.25dB MAGNITUDE (dB) –40 –60 –80 –100 –120 –140 0 4 8 12 16 20 FREQUENCY (kHz) 24 1290 • F17a Figure 17a. LTC1290 FFT Plot 12 fSAMPLE = 50.6kHz EFFECTIVE NUMBER OF BITS 11.6 MAGNITUDE (dB) 11.2 10.8 10.4 10 9.6 9.2 8.8 0 20 60 40 FREQUENCY (kHz) 80 100 1290 F18 Figure 18. LTC1290 ENOB vs Input Frequency fundamentals. This is classically referred to as intermodulation distortion (IMD). 8. Overvoltage Protection Applying signals to the analog MUX that exceed the positive or negative supply of the device will degrade the accuracy of the A/D and possibly damage the device. For example this condition would occur if a signal is applied to the analog MUX before power is applied to the LTC1290. Another example is the input source is operating from different supplies of larger value than the LTC1290. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. As shown in Figure 20, a 1k resistor is enough to stand off ±15V (15mA for one only channel). If more than one channel exceeds the supplies U 0 –20 –40 –60 –80 –100 –120 –140 0 4 8 12 16 20 FREQUENCY (kHz) 24 1290 • F17b W U UO fIN = 25kHz fSAMPLE = 50.6kHz SNR = 72.54dB Figure 17b. LTC1290 FFT Plot 0 –20 –40 –60 –80 –100 –120 0 4 8 12 16 20 FREQUENCY (kHz) 24 1290 • F19 fIN1 = 5.1kHz fIN2 = 5.6kHz fSAMPLE = 50.6kHz Figure 19. LTC1290 FFT Plot then the following guidelines can be used. Limit the current to 7mA per channel and 28mA for all channels. This means four channels can handle 7mA of input current each. Reducing the ACLK and SCLK frequencies from the maximum of 4MHz and 2MHz, respectively, (see Typical Peformance Characteristics curves Maximum ACLK Frequency vs Source Resistance and Sample-and-Hold Acquisition Time vs Source Resistance) allows the use of VIN 1k CH0 VCC 5V 22µF LTC1290 V– DGND AGND –5V 0.1µF 1290 F20 Figure 20. Overvoltage Protection for MUX 23 LTC1290 APPLICATI S I FOR ATIO U power supply reversal from occuring when an input source is applied to the analog MUX before power is applied to the device. Power supply reversal occurs, for example, if the input is pulled below V – then VCC will pull a diode drop below ground which could cause the device not to power up properly. Likewise, if the input is pulled above VCC then V – will be pulled a diode drop above ground. If no inputs are present on the MUX, the Schottky diodes are not required if V – is applied first, then VCC. Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device. VCC 1N5817 LTC1290 V– –5V 1N5817 0.1µF 1290 F22 larger current limiting resistors. Use 1N4148 diode clamps from the MUX inputs to VCC and V – if the value of the series resistor will not allow the maximum clock speeds to be used or if an unknown source is used to drive the LTC1290 MUX inputs. How the various power supplies to the LTC1290 are applied can also lead to overvoltage conditions. For single supply operation (i.e., unipolar mode), if VCC and REF + are not tied together, then VCC should be turned on first, then REF +. If this sequence cannot be met, connecting a diode from REF + to VCC is recommended (see Figure 21). For dual supplies (bipolar mode) placing two Schottky diodes from VCC and V – to ground (Figure 23) will prevent VCC 20 5V 22µF LTC1290 1N4148 REF + 14 Figure 21 TYPICAL APPLICATI A “Quick Look” Circuit for the LTC1290 Users can get a quick look at the function and timing of the LTC1290 by using the following simple circuit. REF + and DIN are tied to VCC selecting a 5V input span, CH7 as a single-ended input, unipolar mode, MSB-first format and 16-bit word length. ACLK and SCLK are tied together and driven by an external clock. CS is driven at 1/128 the clock rate by the CD4520 and DOUT outputs the data. All other pins are tied to a ground plane. The output data from the DOUT pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of CS. 22µF TO OSCILLOSCOPE 24 { W UO U UO 5V 22µF VREF 1290 F21 DGND AGND Figure 22. Power Supply Reversal S A “Quick Look” Circuit for the LTC1290 5V LTC1290 CHO CH1 CH2 CH3 CH4 CH5 CH6 VIN CH7 COM DGND VCC ACLK SCLK DIN DOUT CS REF + REF – V– AGND CLOCK IN 2MHz MAX 1290 TA02 f/128 0.1µF CLK f EN Q1 Q2 Q3 Q4 RESET VSS CD4520 VDD RESET Q4 Q3 Q2 Q1 EN CLK LTC1290 TYPICAL APPLICATI UO CS REF + REF – V – 1290 TA04 S Scope Trace of LTC1290 “Quick Look” Circuit Showing A/D Output of 010101010101 (555HEX) CS ACLK/ SCLK DOUT DEGLITCHER TIME MSB (B11) LSB (B0) FILLS ZEROS VERTICAL: 5V/DIV HORIZONTAL: 1µs/DIV SNEAK-A-BITTM The LTC1290’s unique ability to software select the polarity of the differential inputs and the output word length is used to achieve one more bit of resolution. Using the circuit below with two conversions and some software, a 2’s complement 12-bit + sign word is returned to memory inside the MPU. The MC68HC05C4 was chosen as an example, however, any processor could be used. SNEAK-A-BIT Circuit 22µF 9V LT1021-5 Two 12-bit unipolar conversions are performed: the first over a 0V to 5V span and the second over a 0V to –5V span (by reversing the polarity of the inputs). The sign of the input is determined by which of the two spans contained it. Then the resulting number (ranging from –4095 to +4095 decimal) is converted to 2’s complement notation and stored in RAM. SNEAK-A-BIT VIN 5V VIN (+) CH6 (–) CH7 1ST CONVERSION 4096 STEPS 0V 0V SOFTWARE 0V 8191 STEPS 5V 2MHz CLOCK CHO CH1 OTHER CHANNELS OR SNEAK-A-BIT INPUTS CH2 CH3 CH4 CH5 VIN –5V TO 5V CH6 CH7 COM DGND LTC1290 VCC ACLK SCLK DIN DOUT MC68HC05C4 SCLK MOSI MISO CO 1ST CONVERSION VIN (–) CH6 (+) CH7 2ND CONVERSION 4096 STEPS –5V –5V 1290 TA05 2ND CONVERSION AGND 0.1µF –5V SNEAK-A-BIT is a trademark of Linear Technology Corp. 25 LTC1290 TYPICAL APPLICATI Sign LOCATION $77 B12 B11 B10 B9 B8 LSB LOCATION $87 B4 B3 B2 B1 B0 Filled with 0s B7 B6 B5 SNEAK-A-BIT Code DOUT from LTC1290 in MC68HC05C4 RAM DIN Words for LTC1290 MSBF MUX Addr. (ODD/SIGN) DIN1 DIN2 DIN3 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 UNI Word Length 1 1 1 1 1 1 1290 TA06 SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4 MNEMONIC LDA STA LDA STA BSET JSR JSR JSR JSR #$50 $0A #$FF $06 0,$02 READ –/+ READ –/+ READ –/+ CHK Sign DESCRIPTION Configuration Data for SPCR Load Configuration Data into $0A Configuration Data for Port C DDR Load Configuration Data into Port C DDR Make Sure CS is High Dummy Read Configures LTC1290 for next read Read CH6 with Respect to CH7 Read CH7 with Respect to CH6 Determines which Reading has Valid Data, Converts to 2’s Complement and Stores in RAM 26 UO S SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4 MNEMONIC LDA JSR LDA STA LDA STA RTS READ +/–: LDA JSR LDA STA LDA STA RTS TRANSFER: BCLR STA LOOP 1: TST BPL LDA STA STA LOOP 2: TST BPL BSET LDA STA RTS CHK SIGN: LDA ORA BEQ CLC ROR ROR LDA STA LDA STA BRA MINUS: CLC ROR ROR COM COM LDA ADD STA CLRA ADC STA STA LDA STA END: RTS READ –/+: #$3F TRANSFER $60 $71 $61 $72 #$7F TRANSFER $60 $73 $61 $74 0,$02 $0C $0B LOOP 1 $0C $0C $60 $0B LOOP 2 0,$02 $0C $61 $73 $74 MINUS $73 $74 $73 $77 $74 $87 END $71 $72 $71 $72 $72 #$01 $72 $71 $71 $77 $72 $87 DESCRIPTION Load DIN Word for LTC1290 into ACC Read LTC1290 Routine Load MSBs from LTC1290 into ACC Store MSBs in $71 Load LSBs from LTC1290 into ACC Store LSBs in $72 Return Load DIN Word for LTC1290 into ACC Read LTC1290 Routine Load MSBs from LTC1290 into ACC Store MSBs in $73 Load LSBs from LTC1290 into ACC Store LSBs in $74 Return CS Goes Low Load DIN into SPI, Start Transfer Test Status of SPIF Loop to Previous Instruction if Not Done Load Contents of SPI Data Reg. into ACC Start Next Cycle Store MSBs in $60 Test Status of SPIF Loop to Previous Instruction if Not Done CS Goes High Load Contents of SPI Data Reg. into ACC Store LSBs in $61 Return Load MSBs of ± Read into ACC Or ACC (MSBs) with LSBs of ± Read If Result is 0 Go to Minus Clear Carry Rotate Right $73 Through Carry Rotate Right $74 Through Carry Load MSBs of ± Read into ACC Store MSBs in RAM Location $77 Load LSBs of ± Read into ACC Store LSBs in RAM Location $87 Go to End of Routine Clear Carry Shift MSBs of ± Read Right Shift LSBs of ± Read Right 1’s Complement of MSBs 1’s Complement of LSBs Load LSBs into ACC Add 1 to LSBs Store ACC in $72 Clear ACC Add with Carry to MSBs. Result in ACC Store ACC in $71 Store MSBs in RAM Location $77 Load LSBs in ACC Store LSBs in RAM Location $87 Return LTC1290 TYPICAL APPLICATI Power Shutdown For battery-powered applications it is desirable to keep power dissipation at a minimum. The LTC1290 can be powered down when not in use reducing the supply current from a nominal value of 5mA to typically 5µA (with ACLK turned off). See the curve for Supply Current (Power Shutdown) vs ACLK if ACLK cannot be turned off when the LTC1290 is powered down. In this case the supply current is proportional to the ACLK frequency and is independent of temperature until it reaches the magnitude of the supply current attained with ACLK turned off. As an example of how to use this feature let’s add this to the previous application, SNEAK-A-BIT. After the CHK SIGN subroutine call insert the following: • • JSR CHK SIGN Determines which reading has valid data, converts to 2’s complement and stores in RAM JSR SHUTDOWN LTC1290 power shutdown routine The actual subroutine is: SHUTDOWN: LDA #$3D Load DIN word for LTC1290 into ACC JSR TRANSFER Read LTC1290 routine RTS Return 1 SCLK POWER SHUTDOWN STARTS DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS POWER UP CS 10 CS 1 SCLK POWER SHUTDOWN STARTS DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS 10 POWER UP CS 1 SCLK POWER SHUTDOWN STARTS DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS 10 POWER UP Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. UO S To place the device in power shutdown the word length bits are set to WL1 = 0 and WL0 = 1. The LTC1290 is powered up on the next request for a conversion and it’s ready to digitize an input signal immediately. Power Shutdown Timing Considerations After power shutdown has been requested, the LTC1290 is powered up on the next request for a conversion. This request can be initiated either by bringing CS low or by starting the next cycle of SCLKs if CS is kept low (see Figures 3 and 4). When the SCLK frequency is much slower than the ACLK frequency a situation can arise where the LTC1290 could power down and then prematurely power back up. Power shutdown begins at the negative going edge of the 10th SCLK once it has been requested. A dummy conversion is executed and the LTC1290 waits for the next request for conversion. If the SCLKs have not finished once the LTC1290 has finished its dummy conversion, it will recognize the next remaining SCLKs as a request to start a conversion and power up the LTC1290 (see Figure 23). To prevent this, bring either CS high at the 10th SCLK (Figure 24) or clock out only 10 SCLKs (Figure 25) when power shutdown is requested. 1290 TAF23 Figure 23. Power Shutdown Timing Problem 1290 TAF24 Figure 24. Power Shutdown Timing 1290 TAF25 Figure 25. Power Shutdown Timing 27 LTC1290 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. J Package 20-Lead CERDIP (Narrow 0.300, Hermetic) (LTC DWG # 05-08-1110) 0.300 BSC (0.762 BSC) CORNER LEADS OPTION (4 PLCS) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.015 – 0.060 (0.381 – 1.524) 0.200 (5.080) MAX 1.060 (26.924) MAX 20 19 0.220 – 0.310 0.025 (5.588 – 7.874) (0.635) RAD TYP 2 1 0.125 (3.175) MIN 0.045 – 0.068 (1.143 – 1.727) 0.014 – 0.026 (0.356 – 0.660) 0.100 ± 0.010 (2.540 ± 0.254) 3 4 5 6 7 8 9 10 J20 1197 11 18 17 16 15 14 13 12 0.008 – 0.018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 0.005 (0.127) MIN N Package 20-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN 0.045 – 0.065 (1.143 – 1.651) 1.040* (26.416) MAX 20 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 5 6 7 8 9 10 N20 1197 19 18 17 16 15 14 13 12 11 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) ) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) SW Package 20-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 (0.254 – 0.737) × 45° 0° – 8° TYP 0.394 – 0.419 (10.007 – 10.643) 0.093 – 0.104 (2.362 – 2.642) 0.037 – 0.045 (0.940 – 1.143) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE * DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE ** 0.050 (1.270) TYP 0.014 – 0.019 (0.356 – 0.482) TYP NOTE 1 0.004 – 0.012 (0.102 – 0.305) 1 2 3 4 5 6 7 8 9 10 S20 (WIDE) 0396 RELATED PARTS PART NUMBER LTC1286/LTC1298 LTC1293/LTC1294/LTC1296 LTC1594/LTC1598 DESCRIPTION 12-Bit, Micropower Serial ADC in SO-8 12-Bit, Multiplexed Serial ADC 12-Bit, Micropower Serial ADC COMMENTS 1- or 2-Channel, Autoshutdown 6-, 8- or 8-Channel with Shutdown Output 4- or 8-Channel, 3V Versions Available 1290fcs, sn1290 LT/GP 1098 2K REV C • PRINTED IN USA 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com © LINEAR TECHNOLOGY CORPORATION 1991