LTC1291BCN8

LTC1291 Single Chip 12-Bit Data Acquisition System FEATURES s s s s DESCRIPTIO s s s Built-In Sample-and-Hold Single Supply 5V Operation Power Shutdown Direct 3- or 4-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports Two-Channel Analog Multiplexer Analog Inputs Common Mode to Supply Rails 8-Pin DIP Package KEY SPECIFICATIO S s s s The LTC1291 is a data acquisition system that contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology to perform a 12-bit unipolar A/D conversion. The input multiplexer can be configured for either single-ended or differential inputs. An on-chip sample-and-hold is included on the “+” input. When the LTC1291 is idle, it can be powered down in applications where low power consumption is desired. An external reference is not required because the LTC1291 takes its reference from the power supply (VCC). All these features are packaged in an 8-pin DIP. The serial I/O is designed to communicate without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing data to be transmitted over three or four wires. Given the accuracy, ease of use and small package size, this device is well suited for digitizing analog signals in remote applications where minimum number of interconnects, small physical size, and low power consumption are important. LTCMOS TM is a trademark of Linear Technology Corporation Resolution: 12 Bits Fast Conversion Time: 12µs Max Over Temp. Low Supply Current: 6.0mA (Typ) Active Mode 10µA (Max) Shutdown Mode TYPICAL APPLICATI 2-Channel 12-Bit Data Acquisition System 22µF TANTALUM +5V 0.5 0.4 0.3 CS CH0 2-CHANNEL MUX* CH1 GND DELTA (LSB) VCC(VREF) 0.1µF CLK LTC1291 DOUT DIN DO SCK MC68HC11 MISO MOSI 1291 TA01 *FOR OVERVOLTAGE PROTECTION LIMIT THE INPUT CURRENT TO 15mA PER PIN OR CLAMP THE INPUTS TO VCC AND GND WITH 1N4148 DIODES. CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED CHANNEL OR THE OTHER CHANNEL IS OVERVOLTAGED (VIN < GND OR VIN > VCC). SEE SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION. U Channel-to-Channel INL Matching 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1291 TA02 UO U + 1 LTC1291 ABSOLUTE (Notes 1 and 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW CS 1 CH0 2 CH1 3 GND 4 8 7 6 5 VCC (VREF) CLK DOUT DIN Supply Voltage (VCC) to GND .................................. 12V Voltage Analog Inputs ............................ –0.3V to VCC + 0.3V Digital Inputs........................................ –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation............................................. 500mW Operating Temperature Range LTC1291BC, LTC1291CC, LTC1291DC ............................................ 0°C to 70°C LTC1291BI, LTC1291CI, LTC1291DI ........................................ –40°C to 85°C LTC1291BM, LTC1291CM, LTC1291DM ................................... –55°C to 125°C Storage Temperature Range ................ –65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C J8 PACKAGE 8-LEAD CERAMIC DIP N8 PACKAGE 8-LEAD PLASTIC DIP LTC1291BMJ8 LTC1291CMJ8 LTC1291DMJ8 LTC1291BIJ8 LTC1291CIJ8 LTC1291DIJ8 LTC1291BIN8 LTC1291CIN8 LTC1291DIN8 LTC1291BCN8 LTC1291CCN8 LTC1291DCN8 CO VERTER A D PARAMETER Offset Error Linearity Error (INL) Gain Error Minimum Resolution for which No Missing Codes are Guaranteed Analog Input Range On Channel Leakage Current (Note 8) ULTIPLEXER CHARACTERISTICS (Note 3) LTC1291B LTC1291C MIN TYP MAX ± 3.0 ± 0.5 ± 2.0 12 – 0.05V to VCC + 0.05V ±1 ±1 ±1 ±1 LTC1291D MIN TYP MAX ± 3.0 ± 0.75 ± 4.0 12 UNITS LSB LSB LSB Bits V ±1 ±1 ±1 ±1 µA µA µA µA CONDITIONS (Note 4) (Note 4 & 5) (Note 4) q q q q MIN TYP MAX ± 3.0 ± 0.5 ± 1.0 12 (Note 7) On Channel = 5V Off Channel = 0V On Channel = 0V Off Channel = 5V q q q q ±1 ±1 ±1 ±1 Off Channel Lekage Current (Note 8) On Channel = 5V Off Channel = 0V On Channel = 0V Off Channel = 5V AC CHARACTERISTICS (Note 3) SYMBOL fCLK tSMPL tCONV tCYC tdDO PARAMETER Clock Frequency Analog Input Sample Time Conversion Time Total Cycle Time Delay Time, CLK↓ to DOUT Data Valid CONDITIONS VCC = 5V (Note 6) See Operating Sequence See Operating Sequence See Operating Sequence (Note 6) See Test Circuits q LTC1291B/LTC1291C/LTC1291D MIN TYP MAX (Note 9) 2.5 12 18 CLK + 500ns 160 300 1.0 UNITS MHz CLK Cycles CLK Cycles Cycles ns 2 U W U U WW WU W U LTC1291 AC CHARACTERISTICS (Note 3) SYMBOL tdis ten thDI thDO tWHCLK tWLCLK tf tr tsuDI tsuCS tWHCS tWLCS CIN PARAMETER Delay Time, CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Hold Time, DIN after CLK↑ Time Output Data Remains Valid after CLK↓ CLK High Time CLK Low Time DOUT Fall Time DOUT Rise Time Setup Time, DIN Stable before CLK↑ Setup Time, CS↓ before CLK↑ CS High Time During Conversion CS Low Time During Data Transfer Input Capacitance VCC = 5V (Note 6) VCC = 5V (Note 6) See Test Circuits See Test Circuits VCC = 5V (Note 6) VCC = 5V (Note 6) VCC = 5V (Note 6) VCC = 5V (Note 6) Analog Inputs On Channel Analog Inputs Off Channel Digital Inputs q q CONDITIONS See Test Circuits See Test Circuits VCC = 5V (Note 6) q q LTC1291B/LTC1291C/LTC1291D MIN TYP MAX 80 80 50 130 300 400 65 25 50 50 500 18 100 5 5 130 50 150 200 UNITS ns ns ns ns ns ns ns ns ns ns ns CLK Cycles pF pF pF DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3) SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK ICC PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage High Z Output Leakage Output Source Current Output Sink Current Positive Supply Current CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IOUT = –10µA VCC = 4.75V, IOUT = – 360µA VCC = 4.75V, IOUT = 1.6mA VOUT = VCC, CS High VOUT = 0V, CS High VOUT = 0V VOUT = VCC CS High CS High Power shutdown CLK Off LTC1291BC, LTC1291CC, LTC1291DC LTC1291BI, LTC1291CI, LTC1291DI, LTC1291BM, LTC1291CM, LTC1291DM q q q q q q q q q q q The q denotes specifications which apply over the operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground (unless otherwise noted). Note 3: VCC = 5V, CLK = 1.0MHz unless otherwise specified. Note 4: One LSB is equal to VCC divided by 4096. For example, when VCC = 5V, 1LSB = 5V/4096 = 1.22mV. Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. U LTC1291B/LTC1291C/LTC1291D MIN TYP MAX 2.0 0.8 2.5 –2.5 2.4 4.7 4.0 0.4 3 –3 – 20 20 6 5 5 12 10 15 UNITS V V µA µA V V V µA µA mA mA mA µA µA Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. Note 8: Channel leakage current is measured after the channel selection. Note 9: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 125kHz at 125°C, fCLK ≥ 30kHz at 85°C and fCLK ≥ 3kHz at 25°C. 3 LTC1291 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 10 CLK = 1MHz TA = 25°C 8 10 9 SUPPLY CURRENT (mA) CLK = 1MHz VCC = 5V CHANGE IN OFFSET (LSB = 1/4096 × VCC (VREF)) SUPPLY CURRENT (mA) 6 4 2 0 4 5 SUPPLY VOLTAGE (V) CHANGE IN GAIN ERROR (LSB = 1/4096 × VCC (VREF)) Change in Linearity vs Supply Voltage CHANGE IN LINEARITY (LSB = 1/4096 × VCC (VREF)) 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) 6.0 1291 G05 MAGNITUDE OF OFFSET CHANGE (LSB) 0.4 0.3 0.2 0.1 0 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) Change in Linearity vs Temperature 0.5 MAGNITUDE OF LINEARITY CHANGE (LSB) MAGNITUDE OF GAIN CHANGE (LSB) MINIMUM CLK FREQUENCY* (MHz) VCC = 5V CLK = 1MHz 0.4 0.3 0.2 0.1 0 50 25 0 75 100 –50 –25 AMBIENT TEMPERATURE (°C) * AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED. 4 UW 6 1291 G01 1291 G04 Supply Current vs Temperature 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 Change in Offset vs Supply Voltage 8 7 6 5 4 3 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) 1291 G02 –0.5 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) 6.0 1291 G03 Change in Gain Error vs Supply Voltage 0.5 0.5 Change in Offset vs Temperature VCC = 5V CLK = 1MHz 0.4 0.3 0.2 0.1 6.0 0 50 25 0 75 100 –50 –25 AMBIENT TEMPERATURE (°C) 125 1291 G06 Change in Gain vs Temperature 0.5 VCC = 5V CLK = 1MHz 0.4 Minimum Clock Rate for 0.1 LSB Error VCC = 5V 0.25 0.20 0.15 0.10 0.05 0.3 0.2 0.1 125 0 50 25 0 75 100 –50 –25 AMBIENT TEMPERATURE (°C) 125 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 1291 G07 1291 G08 1291 G09 LTC1291 TYPICAL PERFOR A CE CHARACTERISTICS DOUT Delay Time vs Temperature 250 VCC = 5V MAXIMUM CLK FREQUENCY* (MHz) 1.0 DOUT DELAY TIME FROM CLK↓ (ns) 200 MAXIMUM RFILTER** (Ω) 150 MSB-FIRST DATA 100 LSB-FIRST DATA 50 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) Sample-and-Hold Acquisition Time vs Source Resistance 100 1000 INPUT CHANNEL LEAKAGE CURRENT (nA) S/H AQUISITION TIME TO 0.02% (µs) VCC = 5V TA = 25°C 0V TO 5V INPUT STEP 10 VIN RSOURCE+ + – 1 100 1k RSOURCE+ (Ω) PI FU CTIO S # 1 2, 3 4 5 6 7 8 PIN CS CH0, CH1 GND DIN DOUT CLK VCC(VREF) FUNCTION Chip Select Input Analog Inputs Analog Ground Digital Data Input Digital Data Output Shift Clock Positive Supply and Reference Voltage UW 1291 G10 1291 G13 Maximum Clock Rate vs Source Resistance 10k VCC = 5V CLK = 1MHz Maximum Filter Resistor vs Cycle Time RFILTER 0.8 +VIN RSOURCE– 1k +VIN CFILTER ≥1µF + – 0.6 + +IN – –IN 100 0.4 10 0.2 125 0 100 1 1k 10k RSOURCE – (Ω) 100k 1291 G11 10 100 1k CYCLE TIME (µs) 10k 1291 G12 Input Channel Leakage Current vs Temperature 900 800 700 600 500 400 300 200 100 ON CHANNEL OFF CHANNEL GUARANTEED * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED. **MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED. 10k 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) 1291 G14 U U U DESCRIPTION A logic low on this input enables the LTC1291. These inputs must be free of noise with respect to GND. GND should be tied directly to an analog ground plane. The multiplexer address is shifted into this input. The A/D conversion result is shifted out of this output. This clock synchronizes the serial data transfer. This pin provides power and defines the span of the A/D converter. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. 5 LTC1291 BLOCK DIAGRA VCC (VREF) 8 DIN 5 CH0 CH1 2 3 ANALOG INPUT MUX GND TEST CIRCUITS Load Circuit for tdDO, tr and tf 1.4V DOUT 100pF On and Off Channel Leakage Current 5V ION A IOFF A OFF CHANNEL ON CHANNEL DOUT WAVEFORM 1 (SEE NOTE 1) CS POLARITY 1291 TC01 6 W 7 CLK INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER 6 DOUT SAMPLE AND HOLD COMP 12-BIT SAR 12-BIT CAPACITIVE DAC 4 CONTROL AND TIMING 1 CS 1291 BD Load Circuit for tdis and ten TEST POINT 3k 3k TEST POINT 5V tdis WAVEFORM 2, ten tdis WAVEFORM 1 1291 TC05 DOUT 100pF 1291 TC02 Voltage Waveforms for tdis 2.0V 90% tdis DOUT WAVEFORM 2 (SEE NOTE 2) 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1291 TC06 LTC1291 TEST CIRCUITS Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 2.4V 0.4V tr CLK 0.8V tdDO 2.4V tf 1291 TC04 Voltage Waveforms for DOUT Delay Time, tdDO DOUT DOUT 0.4V 1291 TC03 Voltage Waveforms for ten CS DIN START CLK 1 2 3 4 5 DOUT 0.8V ten B11 1291 TC07 APPLICATI S I FOR ATIO The LTC1291 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, half duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS Serial Interface The LTC1291 communicates with microprocessors and other external circuitry via a synchronous, half duplex, four-wire serial interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit U being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. CS DIN 1 DOUT 1 DIN 2 DOUT 2 SHIFT MUX 1 NULL SHIFT A/D CONVERSION ADDRESS IN BIT RESULT OUT 1291 F01 W U UO Figure 1 The input data is first received and then the A/D conversion result is transmitted (half duplex). Because of the half duplex operation DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and 7 LTC1291 APPLICATI S I FOR ATIO DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After CS falls the LTC1291 looks for a start bit. After the start bit is received a 4-bit input word is shifted into the DIN input which configures the LTC1291 and starts the conversion. After one null bit, the result of Operating Sequence (Example: Differential Inputs (CH0 +, CH1 –)) MSB-FIRST DATA (MSBF = 1) tCYC CS CLK START DIN SGL/ DIFF MSBF B11 tSMPL tCONV B1 B0 FILLED WITH ZEROES ODD/ SIGN PS DON'T CARE DOUT HI-Z LSB-FIRST DATA (MSBF = 0) tCYC CS CLK START DIN SGL/ DIFF MSBF B11 B1 B0 B1 B11 ODD/ SIGN PS DON'T CARE DOUT HI-Z tSMPL tCONV Power Shutdown Operating Sequence (Example: Differential Inputs (CH0 +, CH1 –) and MSB-First Data) CS REQUEST POWER SHUTDOWN SHUTDOWN* NEW CONVERSION BEGINS CLK START DIN SGL/ DIFF MSBF B11 DATA NOT VALID B0 FILLED WITH ZEROES HI-Z ODD/ SIGN PS DON'T CARE SGL/ DIFF MSBF START ODD/ SIGN PS DOUT HI-Z * STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION CS CAN BE BROUGHT HIGH ONCE DIN HAS BEEN CLOCKED IN 8 U the conversion appears MSB-first on the DOUT line. The conversion result is output, bit by bit, as the conversion is performed. At the end of the data exchange CS should be brought high. This resets the LTC1291 in preparation for the next data exchange. DON'T CARE DON’T CARE FILLED WITH ZEROES 1291 AI03 1291 AI04 W U UO LTC1291 APPLICATI S I FOR ATIO Input Data Word The 4-bit data word is clocked into the DIN pin on the rising edge of the clock after chip select goes low and the start bit has been recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The input word is defined as follows: MSB-FIRST/ LSB-FIRST SGL/ DIFF ODD/ SIGN MSBF START PS POWER SHUTDOWN 1291 F02 MUX ADDRESS Figure 2. Input Data Word Start Bit The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer and all leading zeroes which precede this logical one will be ignored. After the start bit is received the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. MUX Address The bits of the input word following the START BIT assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND. Only the “+” inputs have sample-andholds. Signals applied at the “–” inputs must not change more than the required accuracy during the conversion. U Multiplexer Channel Selection MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 CHANNEL # 0 1 + + + – – + GND – – W U UO MSB-First/LSB-First (MSBF) The output data of the LTC1291 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB-first format. Logical zeroes will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. When the MSBF bit is a logical zero, LSB-first data will follow the normal MSB-first data on the DOUT line (see Operating Sequence). Power Shutdown The power shutdown feature of the LTC1291 is activated by making the PS bit a logical zero. If CS remains low after the PS bit has been received, a 12-bit DOUT word with all logical ones will be shifted out followed by logical zeroes until CS goes high. Then the DOUT line will go into its high impedance state. The LTC1291 will remain in the shutdown mode until the next CS cycle. There is no warm-up or wait period required after coming out of the power shutdown cycle so a conversion can commence after CS goes low (see Power Shutdown Operating Sequence). 9 LTC1291 APPLICATI S I FOR ATIO Output Code The LTC1291 performs a unipolar conversion. The following shows the output code and transfer curve: Unipolar Output Code 111111111111 OUTPUT CODE 111111111111 111111111110 • • • 000000000001 000000000000 INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V INPUT VOLTAGE (VREF = 5V) 4.9988V 4.9976V • • • 0.0012V 0V 1291 AI05a Microprocessor Interfaces The LTC1291 can interface directly (without external hardware) to most popular microprocessors’s (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1291. Included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. Motorola SPI (MC68HC11) The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB -first and in 8-bit increments. The DIN word sent to the data register starts the SPI process. With three 8-bit transfers, the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU. The data is right justified in the two memory locations. ANDing the second byte with 0DHEX clears the four most significant bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed. 10 U Unipolar Transfer Curve 111111111110 W U UO • • • 000000000001 000000000000 0V 1LSB VREF–1LSB VREF VREF–2LSB VIN 1291 AI05b Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1291** PART NUMBER TYPE OF INTERFACE Motorola MC6805S2, S3 SPI MC68HC11 SPI MC68HC05 SPI RCA CDP68HC05 SPI Hitachi HD6305 SCI Synchronous HD6301 SCI Synchronous HD63701 SCI Synchronous HD6303 SCI Synchronous HD64180 SCI Synchronous National Semiconductor COP400 Family MICROWIRE† COP800 Family MCROWIRE/PLUS† NS8050U MICROWIRE/PLUS HPC16000 Family MICROWIRE/PLUS Texas Instruments TMS7002 Serial Port TMS7042 Serial Port TMS70C02 Serial Port TMS70C42 Serial Port TMS32011* Serial Port TMS32020* Serial Port TMS370C050 SPI * Requires external hardware ** Contact factory for interface information for processors not on this list † MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corp. LTC1291 APPLICATI CS S I FOR ATIO Timing Diagram for Interface to the MC68HC11 CLK DIN SGL/ START DIFF ODD/ EVEN DOUT MPU TRANSMIT WORD 0 0 0 0 0 0 1 SGL/ DIFF ODD/ EVEN MSBF BYTE 1 MPU RECEIVED WORD ? ? ? ? ? ? ? ? ? BYTE 1 Hardware and Software Interface to Motorola MC68HC11 DOUT FROM LTC1291 STORED IN MC68HC11 RAM MSB #62 0 0 0 0 B11 B10 B9 B8 BYTE 1 ANALOG INPUTS B3 B2 B1 B0 BYTE 2 CH1 CH0 CS CLK LTC1291 DOUT DIN D0 SCK MC68HC11 MISO MOSI LTC1291 AI07 LSB #63 B7 B6 B5 B4 MC68HC11 CODE In this example the DIN word configures the input MUX for a single-ended input to be applied to CH0. The conversion result is output MSB-first. LABEL MNEMONIC LDAA STAA LDAA STAA LDAA STAA LDAA STAA OPERAND #$50 $1028 #$1B $1009 #$03 $50 #$60 $51 COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG. DATA FOR PORT D DDR LOAD DATA INTO PORT D DDR LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $50 LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $51 LABEL MNEMONIC LDAA STAA LDX LOOP BCLR LDAA STAA OPERAND #$00 COMMENTS LOAD DUMMY DIN WORD INTO ACC A $52 LOAD DUMMY DIN DATA INTO $52 #$1000 LOAD INDEX REGISTER X WITH $1000 $08,X,#$01 D0 GOES LOW (CS GOES LOW) $50 LOAD DIN INTO ACC A FROM $50 $102A LOAD DIN INTO SPI, START SCK U MSBF PS DON'T CARE B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 PS X BYTE 2 X X X X X X X X X X X X BYTE 3 (DUMMY) ? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LTC1291 AI06 W U UO BYTE 2 BYTE 3 11 LTC1291 APPLICATI LABEL MNEMONIC LDAA WAIT1 BPL LDAA STAA WAIT2 LDAA BPL LDAA STAA LDAA S I FOR ATIO OPERAND $1029 WAIT1 $51 $102A $1029 WAIT2 $102A $62 $52 COMMENTS CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD DIN INTO ACC A FROM $51 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD LTC1291 MSBs INTO ACC A STORE MSBs IN $62 LOAD DUMMY DIN INTO ACC A FROM $52 Interfacing to the Parallel Port of the Intel 8051 Family The Intel 8051 has been chosen to show the interface between the LTC1291 and parallel port microprocessors. Usually the signals CS, DIN and CLK are generated on three port lines and the DOUT signal is read on a fourth port line. Timing Diagram for Interface to Intel 8051 PS BIT LATCHED INTO LTC1291 1 CLK 2 3 4 5 CS DATA (DIN/DOUT) ODD/ START SIGN SGL/ DIFF MSBF 8051 P1.2 OUTPUT DATA TO LTC1291 8051 P1.2 RECONFIGURED AS INPUT AFTER THE 5TH RISING CLK BEFORE THE 5TH FALLING CLK Hardware and Software Interface to Intel 8051 DOUT FROM LTC1291 STORED IN 8051 RAM MSB R2 B11 CH0 B10 B9 B8 B7 B6 B5 B4 ANALOG INPUTS 0 0 0 0 CH1 LTC1291 DOUT DIN MUX ADDRESS A/D RESULT LTC1291 AI09 LSB R1 B3 B2 B1 B0 12 U LABEL MNEMONIC STAA WAIT3 LDAA BPL BSET LDAA STAA JMP OPERAND $102A $1029 WAIT3 $08,X#$01 $102A $63 LOOP COMMENTS LOAD DUMMY DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE D0 GOES HIGH (CS GOES HIGH) LOAD LTC1291 LSBs IN ACC STORE LSBs IN $63 START NEXT CONVERSION W U UO This works very well. One can save a line by tying the DIN and DOUT lines together. The 8051 first sends the start bit and MUX Address to the LTC1291 over the line connected to P1.2. Then P1.2 is reconfigured as an input and the 8051 reads back the 12-bit A/D result over the same data line. PS B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LTC1291 SENDS A/D RESULT BACK TO 8051 P1.2 LTC1291 TAKES CONTROL OF DATA LINE ON 5TH FALLING CLK LTC1291 AI08 CS CLK P1.4 P1.3 8051 P1.2 LTC1291 APPLICATI 8051 Code In this example the input MUX is configured to accept a differential input between CH0 and CH1. The result from the conversion is clocked out MSB-first. LABEL MNEMONIC SETB CONT MOV CLR MOV LOOP1 RLC CLR MOV SETB DJNZ MOV CLR MOV LOOP MOV RLC SETB CLR DJNZ MOV MOV SETB OPERAND P1.4 A,#98H P1.4 R4,#05H A P1.3 P1.2,C P1.3 R4,LOOP1 P1,#04H P1.3 R4,#09H C,P1.2 A P1.3 P1.3 R4,LOOP R2,A C,P1.2 P1.3 COMMENTS CS GOES HIGH DIN WORD FOR LTC1291 CS GOES LOW LOAD COUNTER ROTATE DIN BIT INTO CARRY CLK GOES LOW OUTPUT DIN BIT TO LTC1291 CLK GOES HIGH NEXT DIN BIT P1.2 BECOMES AN INPUT CLK GOES LOW LOAD COUNTER READ DATA BIT INTO CARRY ROTATE DATA BIT (B3) INTO ACC CLK GOES HIGH CLK GOES LOW NEXT DOUT BIT STORE MSBS IN R2 READ DATA BIT INTO CARRY CLK GOES HIGH LABEL MNEMONIC CLR CLR RLC MOV RLC SETB CLR MOV RLC SETB CLR MOV SETB RRC RRC RRC RRC MOV AJMP OPERAND P1.3 A A C,P1.2 A P1.3 P1.3 C,P1.2 A P1.3 P1.3 C,P1.2 P1.4 A A A A R3,A CONT COMMENTS CLK GOES LOW CLEAR ACC ROTATE DATA BIT (B3) INTO ACC READ DATA BIT INTO CARRY ROTATE DATA BIT (B2) INTO ACC CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY ROTATE DATA BIT (B1) INTO ACC CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY CS GOES HIGH ROTATE DATA BIT (B0) INTO ACC ROTAGE RIGHT INTO ACC ROTAGE RIGHT INTO ACC ROTAGE RIGHT INTO ACC STORE LSBs IN R3 START NEXT CONVERSION S I FOR ATIO Sharing the Serial Interface The LTC1291 can share the same 3-wire serial interface with other peripheral components or other LTC1291s 2 1 0 3-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1291s CS LTC1291 2 CHANNELS OUTPUT PORT SERIAL DATA MPU 3 3 CS LTC1291 2 CHANNELS 3 CS LTC1291 2 CHANNELS 3 Figure 3. Several LTC1291s Sharing One 3-Wire Serial Interface U (Figure 3). The CS signals decide which LTC1291 is being addressed by MPU. LTC1291 F03 W U UO 13 LTC1291 APPLICATI S I FOR ATIO U VERTICAL: 0.5mV/DIV HORIZONTAL: 10µs/DIV ANALOG CONSIDERATIONS Grounding The LTC1291 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length. Figure 4 shows an example of an ideal LTC1291 ground plane for a two-sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 22µF TANTALUM 0.1µF 1 2 LTC1291 3 ANALOG GROUND PLANE 4 8 7 6 5 VERTICAL: 0.5mV/DIV Figure 4. Example Ground Plane for the LTC1291 Bypassing For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to ground during the conversion cycle can induce error or noise in the output code. VCC noise and ripple can be kept below 0.5mV by bypassing the VCC pin directly to the analog ground plane with a minimum of 22µF tantalum capacitor and with leads as short as possible. A 0.1µF ceramic disk capacitor should also be placed directly across VCC (Pin 8) and GND (Pin 4) as close to the pins as possible. The VCC supply should have a low output impedance such as that obtained from a voltage regulator (e.g., LT323A). Figures 5 and 6 show the effects of good and poor VCC bypassing. 14 W U UO Figure 5. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors VCC CS VCC HORIZONTAL: 10µs/DIV LTC1291 F04 Figure 6. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1291 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. If large source resistances are used or if slow settling op amps drive the inputs, take care to insure the transients caused by the current spikes settle completely before the conversion begins. Minimizing Gain and Offset Error Because the LTC1291’s reference is taken from the power supply pin (VCC) proper PC board layout and supply bypassing is important for attaining the best performance from the A/D converter. Any parasitic resistance in the VCC LTC1291 APPLICATI S I FOR ATIO U and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time. “+” Input Settling The input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 9). The sample period is 2.5 CLK cycles before a conversion starts. The voltage on the “+” input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 2.5µs, RSOURCE+ < 1.0k and C1 < 20pF will provide adequate settle time. “–” Input Settling At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figure 9). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. It is critical that the “–” input voltage be free of noise and settle completely during the first CLK cycle of the conversion. Minimizing RSOURCE – and C2 will improve settling time. If large “–” input source resistance must be used, the time can be extended by using a slower CLK frequency. At the maximum CLK frequency of 1MHz, RSOURCE – < 250Ω and C2 < 20pF will provide adequate settling. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see Figure 9). Again the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 2.5µs (“+” input) and 1µs (“–” input) that occurs at the maximum clock rate of 1MHz. Figures 10 and 11 show examples adequate and poor op amp settling. 5V or GND lead will cause gain errors and offset errors (Figure 7). For the best performance the LTC1291 should be soldered directly to the PC board. If the source can not be placed next to the pin and the gain parameter is important the pin should be Kelvin-sensed to eliminate parasitic resistances due to long PC traces. For example, 0.1Ω of resistance in the VCC lead can typically cause 0.5LSB (ICC × 0.1Ω /VCC) of gain error for VCC = 5V. When the input MUX is selected for single-ended input the minus terminal is connected to GND internally on the die. Any parasitic resistance from the GND pin to the ground plane will lead to an offset voltage (ICC × RP2). VCC RP1 LTC1291 D/A REF + REF – RP2 GND Figure 7. Parasitic Resistance in the VCC and GND Leads Source Resistance The analog inputs of the LTC1291 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON). CIN gets switched between “+” and “–” inputs once during each conversion cycle. Large external source resistors RSOURCE + VIN + C1 “–” INPUT “+” INPUT LTC1291 3RD CLK↑ RON = 500Ω 5TH CLK↓ CIN = 100pF RSOURCE – VIN – C2 LTC1291 F08 Figure 8. Analog Input Equivalent Circuit W U – + UO LTC1291 F07 15 LTC1291 APPLICATI CS S I FOR ATIO CLK DIN START SGL/ DIFF DOUT HI-Z 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT Figure 9. “+” and “–” Input Settling Windows VERTICAL: 5mV/DIV VERTICAL: 5mV/DIV HORIZONTAL: 500ns/DIV Figure 10. Adequate Settling of Op Amp Driving Analog Input 16 U SAMPLE HOLD ODD/ SIGN MSBF PS tSMPL “+” INPUT MUST SETTLE DURING THIS TIME B11 LTC1291 F09 W U UO HORIZONTAL: 20µs/DIV Figure 11. Poor Op Amp Settling Can Cause A/D Errors (Note Horizontal Scale) LTC1291 APPLICATI S I FOR ATIO U allows the LTC1291 to convert rapidly varying signals (see typical performance characteristics curve of S/H Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 9. The sampling interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling edge of the PS bit is received. On this falling edge the S/H goes into the hold mode and the conversion begins. Differential Input With a differential input the A/D no longer converts a single voltage but converts the difference between two voltages. The voltage on the +IN pin is sampled and held and can be rapidly time varying. The voltage on the –IN pin must remain constant and be free of noise and ripple throughout the conversion time. Otherwise the differencing operation will not be done accurately. The conversion time is 12 CLK cycles. Therefore a change in the –IN input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the –IN input this error would be:   VERROR(MAX) = 2πf(−IN)VPEAK  12   fCLK  RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 12. For large values of CF (e.g., 1µF) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and a large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF × VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 18.5µs, the input current equals 27µA at VIN = 5V. Here a filter resistor of 4.5Ω will cause 0.1LSB of full-scale error. If a large filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the typical performance characteristics curve Maximum Filter Resistor vs Cycle Time. RFILTER VIN – CFILTER IDC “+” LTC1291 “–” Figure 12. RC Input Filtering Input Leakage Current Input leakage currents also can create errors if the source resistance gets too large. For example, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1k will cause a voltage drop of 1mV or 0.8LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical performance characteristics curve Input Channel Leakage Current vs Temperature). SAMPLE-AND-HOLD Single-Ended Input The LTC1291 provides a built-in sample-and-hold (S/H) function on the +IN input for signals acquired in the singleended mode (–IN pin grounded). The sample-and-hold W U UO LTC1291 F12 ( ) Where f(–IN) is the frequency of the –IN input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. Usually VERROR will not be significant. For a 60Hz signal on the –IN input to generate a 0.25LSB error (300µV) with the converter running at CLK = 1MHz, its peak value would have to be 66mV. Rearranging the above equation the maximum sinusoidal signal that can be digitized to a given accuracy is given as:  VERROR(MAX)  f(−IN) =    2πVPEAK   fCLK   12    For 0.25LSB error (300µV) the maximum input sinusoid with a 5V peak amplitude that can be digitized is 0.8Hz. 17 LTC1291 APPLICATI S I FOR ATIO U 1N4148 DIODES CS CH0 5V VCC (VREF) CLK LTC1291 CH1 DOUT GND DIN LTC1291 F13 Overvoltage Protection Applying signals to the LTC1291’s analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the A/D and possibly damage the device. For example this condition would occur if a signal is applied to the analog inputs before power is applied to the LTC1291. It can also happen if the input source is operating from supplies of larger value than the LTC1291 supply. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. There are two ways to protect the inputs. In Figure 13 diode clamps from the inputs to VCC and GND are used. The second method is to put resistors in series with the analog inputs for current limiting. Limit the current to 15mA per channel. The +IN input can accept a resistor value of 1k but the –IN input cannot accept more than 250Ω when clocked at its maximum clock frequency of 1MHz. If the LTC1291 is clocked at the maximum clock frequency and 250Ω is not enough to current limit the input source then the clamp diodes are recommended (Figures 14 and 15). The reason for the limit on the resistor value is the MSB bit test is affected by the value of the resistor placed at the –IN input (see discussion on Analog Inputs and the typical performance characteristics Maximum CLK Frequency vs Source Resistance). Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device. 18 W U UO Figure 13. Overvoltage Protection for Inputs CS 1k CH0 250Ω VCC (VREF) CLK 5V LTC1291 CH1 DOUT GND DIN LTC1291 F14 Figure 14. Overvoltage Protection for Inputs 1N4148 DIODES CS 1k CH0 CLK LTC1291 CH1 DOUT GND DIN LTC1291 F15 VCC (VREF) 5V Figure 15. Overvoltage Protection for Inputs LTC1291 APPLICATI S I FOR ATIO U data is output MSB-first. CS is driven at 1/64 the clock frequency by the 74HC393 and DOUT outputs the data. The output data from the DOUT pin can be viewed on a oscilloscope that is set up to trigger on the falling edge of CS (Figure 17). + f/64 CS CH0 VIN VCC (VREF) A1 VCC CLR1 A2 1QA CLR2 1QB 74HC393 2QA 1QC 2QB 1QD 2QC GND 2QD 0.1µF 5V 0.1µF f CLOCK IN 1MHz LTC1291 F16 A “Quick Look” Circuit for the LTC1291 Users can get a quick look at the function and timing of the LTC1291 by using the following simple circuit (Figure 16). DIN is tied to VCC. This requires VIN be applied to CH1 with respect to the ground plane. The 22µF TANTALUM CLK LTC1291 CH1 DOUT GND DIN TO OSCILLOSCOPE CLK CS DOUT Figure 17. Scope Trace of the LTC1291 "Quick Look" Circuit Showing Output 101010101010 (AAAHEX) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. W U UO Figure 16. “Quick Look” Circuit for the LTC1291 NULL BIT MSB (B11) LSB (B0) FILLS WITH ZEROES VERTICAL: 5V/DIV HORIZONTAL: 5µs/DIV 19 LTC1291 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. J8 Package 8-Lead Ceramic DIP 0.005 (0.127) MIN 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0.025 (0.635) RAD TIP 0.405 (10.287) MAX 0.290 – 0.320 (7.37 – 8.13) 8 7 6 5 0.220 – 0.310 (5.588 – 7.874) 0.008 – 0.018 (0.203 – 0.460) 0.385 ± 0.025 (9.779 ± 0.635) 0° – 15° 1 0.014 – 0.026 (0.360 – 0.660) 0.125 3.175 MIN 0.100 ± 0.010 (2.540 ± 0.254) 0.055 (1.397) MAX 2 3 4 0.038 – 0.068 (0.965 – 1.727) TJMAX 150°C θJA 100°C/W N8 Package 8-Lead Plastic DIP 0.400 (10.160) MAX 0.020 (0.508) MIN 0.300 – 0.320 (7.620 – 8.128) 0.065 (1.651) TYP 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 8 7 6 5 0.250 ± 0.010 (6.350 ± 0.254) 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN 1 2 3 4 (8.255 +0.635) –0.381 0.018 ± 0.003 (0.457 ± 0.076) TJMAX 100°C θJA 130°C/W 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 LT/GP 0892 10K REV 0 © LINEAR TECHNOLOGY CORPORATION 1992