LTC1411IG

LTC1411 Single Supply 14-Bit 2.5Msps ADC FEATURES s s s s s s s s s s s DESCRIPTIO Sample Rate: 2.5Msps 80dB S/(N + D) and 90dB THD at 100kHz fIN Single 5V Operation No Pipeline Delay Programmable Input Ranges Low Power Dissipation: 195mW (Typ) True Differential Inputs Reject Common Mode Noise Out-of-Range Indicator Internal or External Reference Sleep (1µA) and Nap (2mA) Shutdown Modes 36-Pin SSOP Package The LTC ®1411 is a 2.5Msps sampling 14-bit A/D converter in a 36-pin SSOP package, which typically dissipates only 195mW from a single 5V supply. This device comes complete with a high bandwidth sample-andhold, a precision reference, programmable input ranges and an internally trimmed clock. The ADC can be powered down with either the Nap or Sleep mode for low power applications. The LTC1411 converts either differential or single-ended inputs and presents data in 2’s complement format. Maximum DC specs include ± 2LSB INL and 14-bit no missing code over temperature. Outstanding dynamic performance includes 80dB S/(N + D) and 90dB THD at 100kHz input frequency. The LTC1411 has four programmable input ranges selected by two digital input pins, PGA0 and PGA1. This provides input spans of ± 1.8V, ± 1.27V, ± 0.9V and ± 0.64V. An out-of-the-range signal together with the D13 (MSB) will indicate whether a signal is over or under the ADC’s input range. A simple conversion start input and a data ready signal ease connections to FIFOs, DSPs and microprocessors. APPLICATIO S s s s s s s Telecommunications High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Spectrum Analysis Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. BLOCK DIAGRA 1 2 AIN+ AIN– REFOUT REFIN 5k 5k 5 REFCOM1 2k 2.5V BANDGAP REFERENCE 10 AVP 30 DVP OVDD 29 86 80 74 68 62 56 50 44 38 32 26 20 14 10 OGND 28 D13 3 4 + – 12 14-BIT ADC 14 OUTPUT DRIVERS INTERNAL CLOCK D0 BUSY OTR 25 27 26 REFCOM2 6 X1.62/ X1.15 CONTROL LOGIC S/(N + D) (dB) • • • 7, 8, 9 AGND 11 AVM 36 SLP 35 NAP 34 PGA0 33 PGA1 32 CONVST 31 DGND 1411 BD U S/(N + D) and Effective Bits vs Input Frequency 14 13 12 11 10 W U EFFECTIVE BITS 100 1000 INPUT FREQUENCY (kHz) 10000 1411 TA02 1411f 1 LTC1411 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW AIN+ AIN– REFOUT REFIN REFCOM1 REFCOM2 AGND1 AGND2 AGND3 1 2 3 4 5 6 7 8 9 36 SLP 35 NAP 34 PGA0 33 PGA1 32 CONVST 31 DGND 30 DVP 29 OVDD 28 OGND 27 BUSY 26 OTR 25 D0 24 D1 23 D2 22 D3 21 D4 20 D5 19 D6 AVP = DVP = OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 6V Analog Input Voltage (Note 3) ... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) .................. – 0.3V to 10V Digital Output Voltage ............... – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1411C ............................................... 0°C to 70°C LTC1411I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1411CG LTC1411IG AVP 10 AVM 11 D13 (MSB) 12 D12 13 D11 14 D10 15 D9 16 D8 17 D7 18 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 7) (Note 8) The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Notes 5, 6) CONDITIONS q q q MIN 14 TYP MAX ±2 ± 16 ± 24 ± 60 UNITS Bits LSB LSB LSB LSB ppm/°C External Reference = 2.5V IOUT(REF) = 0 ± 15 DY A IC ACCURACY SYMBOL PARAMETER TA = 25°C (Note 5) CONDITIONS 100kHz Input Signal 500kHz Input Signal 100kHz Input Signal, Up to 5th Harmonic 500kHz Input Signal, Up to 5th Harmonic 100kHz Input Signal 500kHz Input Signal S/(N + D) ≥ 74dB MIN TYP 80.0 77.5 – 90 – 82 90 82 1.0 0.66 MAX UNITS dB dB dB dB dB dB MHz LSBRMS 1411f S/(N + D) Signal-to-Noise Plus Distortion Ratio THD Total Harmonic Distortion Peak Harmonic or Spurious Noise Full Linear Bandwidth Transition Noise 2 U W U U WW W WU U LTC1411 A ALOG I PUT SYMBOL PARAMETER VIN Analog Input Range (Note 9) Common Mode Input Range CIN tACQ tAP tjitter CMRR Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio Input Leakage Current (Pins 1, 2) I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Load Regulation REFCOM2 Output Voltage REFIN Input Current CONDITIONS IOUT = 0 IOUT = 0 4.75V ≤ VDD ≤ 5.25V 0 ≤ IOUT ≤ 1mA DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current VDD = 4.75V, IO = – 10µA VDD = 4.75V, IO = – 200µA VDD = 4.75V, IO = 160µA VDD = 4.75V, IO = 1.6mA VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.75V The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5) MIN q q q POWER REQUIRE E TS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5) SYMBOL PARAMETER VDD IDD Supply Voltage Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode CONDITIONS (Note 9) q PD UW U U U U U U TA = 25°C (Note 5) CONDITIONS (AIN+) – (AIN–), PGA0 = PGA1 = 5V (AIN+) – (AIN–), PGA0 = 5V, PGA1 = 0V (AIN+) – (AIN–), PGA0 = 0V, PGA1 = 5V (AIN+) – (AIN–), PGA0 = PGA1 = 0V AIN+ or AIN– Between Conversions (Sample Mode) During Conversions (Hold Mode) 0 10 4 100 7 1 0V < (AIN– = AIN+) < VDD 62 0.1 MIN TYP ± 1.8 ± 1.27 ± 0.9 ± 0.64 VDD MAX UNITS V V V V V pF pF ns ns psRMS dB µA U TA = 25°C (Note 5) MIN 2.480 TYP 2.500 ± 15 0.01 2 4.05 250 MAX 2.520 UNITS V ppm/°C LSB/ V LSB/mA V µA IOUT = 0, PGA0 = PGA1 = 5V REFIN = External Reference 2.5V TYP MAX 0.8 ± 10 UNITS V V µA pF V V 2.4 VIN = 0V to VDD, Except SLP, NAP (Note 11) 2 4.75 q q 4.0 0.05 0.10 – 10 10 0.4 V V mA mA MIN 4.75 TYP 39 2 1 195 10 5 MAX 5.25 65 UNITS V mA mA µA mW mW µW 1411f NAP = 0V (Note 11) SLP = 0V q 325 NAP = 0V SLP = 0V 3 LTC1411 TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tCONV tACQ t0 t1 t2 t3 t4 t5 t6 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time SLP↑ to CONVST↓ Wake-Up Time NAP↑ to CONVST↓ Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready After BUSY↑ CONVST High Time Aperture Delay of Sample-and-Hold The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Notes 5) (See Figures 11a, 11b) CONDITIONS (Note 9) q q Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND, AVM and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below AGND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA without latchup. Note 4: When these pin voltages are taken below AGND, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below AGND without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, PGA1 = PGA0 = 5V, fSAMPLE = 2.5MHz at 25°C and t r = t f = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– tied to an external 2.5V reference voltage. TYPICAL PERFOR A CE CHARACTERISTICS S/(N + D) vs Input Frequency 86 80 74 68 62 56 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 G01 S/(N + D) (dB) 62 DISTORTION (dB) SNR (dB) 4 UW UW MIN 2.5 TYP 250 100 210 250 MAX 350 UNITS MHz ns ns ms ns ns ns ns ns ns 10µF Bypass Capacitor at REFCOM2 Pin (Note 10) CL = 25pF (Note 10) q q 20 12 7 20 7 Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Recommended operating conditions. Note 10: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high within 20ns after conversion start of after BUSY rises. Note 11: SLP and NAP have an internal pull-down so the pins will draw approximately 7µA when tied high and less than 1µA when tied low. Signal-to-Noise Ratio vs Input Frequency 86 80 74 68 56 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 G02 Distortion vs Input Frequency 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 G03 2ND THD 3RD 1411f LTC1411 TYPICAL PERFOR A CE CHARACTERISTICS Spurious Free Dynamic Range vs Input Frequency 0 –10 –20 –30 DISTORTION (dB) SINAD (dB) –40 –50 –60 –70 –80 –90 –100 –110 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 G04 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 G05 INL (LSB) Differential Nonlinearity vs Output Code 1.0 0.8 0.6 SUPPLY CURRENT (mA) 0.4 42 41 40 39 38 37 36 SUPPLY CURRENT (mA) DNL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 16384 1411 G08 Histogram for 4096 Conversions 3500 3000 2500 2000 1500 1000 500 0 –1 0 CODE 1 1411 G13 AMPLITUDE (dB) COUNTS UW S/(N + D) vs Input Frequency and Amplitude 86 80 74 68 62 56 –40dB –20dB 0dB 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 Integral Nonlinearity vs Output Code 0 4096 8192 12288 OUTPUT CODE 16384 1411 G07 Supply Current vs Temperature 45 44 43 VDD = 5V 46.5 44.0 41.5 39.0 36.5 34.0 31.5 –25 25 50 0 TEMPERATURE (°C) 75 100 1411 G11 Supply Current vs Supply Voltage TA = 25°C 35 –50 4.5 4.75 5.0 VDD (V) 5.25 5.5 1411 G12 4096 Points FFT Plot (100kHz) 0 –20 –40 –60 –80 –100 –120 –140 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250 1411 G14 SINAD = 78.8dB SFDR = 95dB fSAMPLE = 2.5MHz fIN = 100kHz 1411f 5 LTC1411 TYPICAL PERFOR A CE CHARACTERISTICS 4096 Points FFT Plot (1MHz) 0 –20 –40 –60 –80 –100 –120 –140 0 250 500 750 1000 1250 1411 G15 ACQUISITION TIME (µs) SINAD = 75dB SFDR = 81dB fSAMPLE = 2.5MHz fIN = 1MHz AMPLITUDE (dB) PI FU CTIO S AIN+ (Pin 1): Positive Analog Input. The ADC converts the difference voltage between AIN+ and AIN– with programmable input ranges of ± 1.8V, ±1.27V, ± 0.9V and ± 0.64V depending on PGA selection. AIN+ has common mode range between 0V and VDD. AIN– (Pin 2): Negative Analog Input. This pin can be tied to the REFOUT pin of the ADC or tied to an external DC voltage. This voltage is also the bipolar zero for the ADC. AIN– has common mode range between 0V and VDD. REFOUT (Pin 3): 2.5V Reference Output. Bypass to AGND1 with a 22µF tantalum capacitor if REFOUT is tied to AIN–. No capacitor is needed if the external reference is used to drive AIN–. REFIN (Pin 4): Reference Buffer Input. This pin can be tied to REFOUT or to an external reference if more precision is required. REFCOM1 (Pin 5): Noise Reduction Pin. Put a 10µF bypass capacitor at this pin to reduce the noise going into the reference buffer. REFCOM2 (Pin 6): 4.05V Reference Compensation Pin. Bypass to AGND1 with a 10µF tantalum capacitor in parallel with a 0.1µF ceramic. AGND (Pins 7 to 9): Analog Ground. AGND1 is the ground for the reference. AGND2 is the ground for the comparator and AGND3 is the ground for the remaining analog circuitry. AVP (Pin 10): 5V Analog Power Supply. Bypass to AGND with a 10µF tantalum capacitor. AVM (Pin 11): Analog and Digital Substrate Pin. Tie this pin to AGND. D13 to D0 (Pins 12 to 25): Digital Data Outputs. D13 is the MSB (Most Significant Bit). OTR (Pin 26): Out-of-the-Range Pin. This pin can be used in conjunction with D13 to determine if a signal is less than or greater than the analog input range. If D13 is low and OTR is high, the analog input to the ADC exceeds the maximum voltage of the input range. BUSY (Pin 27): Busy Output. Converter status pin. It is low during conversion. OGND (Pin 28): Digital Ground for Output Drivers (Data Bits, OTR and BUSY). OVDD (Pin 29): 3V or 5V Digital Power Supply for Output Drivers (Data Bits, OTR and BUSY). Bypass to OGND with a 10µF tantalum capacitor. 1411f 6 UW Acquisition Time vs Source Resistance 100 10 1 0.1 0.01 1 FREQUENCY (kHz) 10 1000 10000 100000 100 SOURCE RESISTANCE (Ω) 1411 G16 U U U LTC1411 PI FU CTIO S DVP (Pin 30): 5V Digital Power Supply Pin. Bypass to OGND with a 10µF tantalum capacitor. DGND (Pin 31): Digital Ground. CONVST (Pin 32): Conversion Start Signal. This active low signal starts a conversion on its falling edge. PGA1, PGA0 (Pins 33, 34): Logic Inputs for Programmable Input Range. This ADC has four input ranges (or four REFCOM2 voltages) controlled by these two pins. For the logic inputs applied to PGA0 and PGA1, the following summarizes the gain levels and the analog input range with AIN– tied to 2.5V. Table 1. Input Spans for LTC1411 PGA0 5V 5V 0V 0V PGA1 5V 0V 5V 0V LEVEL 0dB – 3dB – 6dB – 9dB INPUT SPAN ± 1.8V ± 1.28V ± 0.9V ± 0.64V REFCOM2 VOLTAGE 4V 2.9V 2V 1.45V TYPICAL CO ECTIO DIAGRA 1 2 AIN+ AIN– REFOUT REFIN 5k 5k 2k INTERNAL CLOCK 2.5V BANDGAP REFERENCE + 3 22µF* 4 + – 14-BIT ADC + + 10µF 5 REFCOM1 REFCOM2 10µF 6 X1.62/ X1.15 CONTROL LOGIC 7, 8, 9 AGND 11 AVM 36 SLP 35 NAP 34 PGA0 *A 22µF CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE AIN– + W U UU U U U NAP (Pin 35): Nap Input. Driving this pin low will put the ADC in the Nap mode and will reduce the supply current to 2mA and the internal reference will remain active. SLP (Pin 36): Sleep Input. Driving this pin low will put the ADC in the Sleep mode and the ADC draws less than 1µA of supply current. 5V 10 AVP 30 DVP OVDD 29 + 5V OR 3V OGND 28 D13 12 14 OUTPUT DRIVERS • • • D0 BUSY OTR 25 27 26 33 PGA1 32 CONVST 31 DGND 1411 TA01 1411f 7 LTC1411 TEST CIRCUITS Load Circuits for Access Timing 5V 1k DN 1k CL DN CL DN 1k CL DN CL Load Circuits for Output Float Delay 5V 1k (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL 1411 TC01 (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1411 TC02 APPLICATIO S I FOR ATIO CONVERSION DETAILS The LTC1411 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference, internal clock and a programmable input range. The device is easy to interface with microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversions are started by a falling edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, the ADC acquires the analog input in preparation for the next conversion. In the acquire phase, a minimum time of 100ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. 10 1 2 AIN+ AIN – AVP 30 DVP + – INTERNAL CLOCK 14-BIT ADC 14 OUTPUT DRIVERS CONTROL LOGIC 36 SLP 35 NAP 34 PGA0 33 PGA1 32 CONVST 31 DGND 1411 F01 Figure 1. Simplified Block Diagram 8 U During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a high speed comparator. At the end of a conversion, the DAC output balances the analog input (AIN+ – AIN–). The SAR contents (a 14-bit data word) which represents the difference of AIN+ and AIN– are loaded into the 14-bit output latches. DYNAMIC PERFORMANCE The LTC1411 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2a shows a typical LTC1411 FFT plot. Signal-to-Noise The signal-to-(noise + distortion) ratio [S/N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from the above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 2.5MHz sampling rate and a 100kHz input. The dynamic performance holds well to higher input frequencies (see Figure 2b). 1411f W UU OVDD 29 OGND 28 D13 12 • • • D0 BUSY OTR 25 27 26 LTC1411 APPLICATIO S I FOR ATIO 0 –20 –40 –60 –80 –100 –120 –140 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250 1411 G14 SINAD = 78.8dB SFDR = 95dB fSAMPLE = 2.5MHz fIN = 100kHz AMPLITUDE (dB) S/(N + D) (dB) Figure 2a. LTC1411 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz 0 –20 –40 –60 –80 –100 –120 –140 0 250 500 750 1000 1250 1411 G15 SINAD = 75dB SFDR = 81dB fSAMPLE = 2.5MHz fIN = 1MHz AMPLITUDE (dB) DISTORTION (dB) FREQUENCY (kHz) Figure 2b. LTC1411 4096 Point FFT, Input Frequency = 1MHz Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOBS = [S/(N + D) – 1.76]/6.02 where S/(N + D) is expressed in dB. At the maximum sampling rate of 2.5MHz the LTC1411 maintains good ENOBs up to the Nyquist input frequency of 1.25MHz. Refer to Figure 3. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental U 86 80 74 68 62 56 50 44 38 32 26 20 14 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 TA02 W UU 14 13 12 11 10 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 10 100 1000 INPUT FREQUENCY (kHz) 10000 1411 G03 EFFECTIVE BITS 2ND THD 3RD Figure 4. Distortion vs Input Frequency itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V + V3 + V4 + … VN THD = 20 log 2 V1 2 2 2 2 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1411 has good distortion performance up to the Nyquist frequency and beyond. 1411f 9 LTC1411 APPLICATIO S I FOR ATIO Peak Harmonic or Spurious Noise ACQUISITION TIME (µs) The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dB relative to the RMS value of a fullscale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 74dB (12 effective bits). The LTC1411 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1411 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is tied to a fixed DC voltage such as the REFOUT pin of the LTC1411 or an external source). Figure 1 shows a simplified block diagram for the analog inputs of the LTC1411. The AIN+ and AIN– are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuits is low, then the LTC1411 inputs can be driven directly. More acquisition time should be allowed for a higher impedance source. Figure 5 shows the acquisition time versus source resistance. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging 10 U 100 10 1 0.1 0.01 1 10 1000 10000 100000 100 SOURCE RESISTANCE (Ω) 1411 G16 W UU Figure 5. Acquisition Time vs Source Resistance the sampling capacitor, choose an amplifier that has a low output impedance (