LTC1412C

LTC1412 12-Bit, 3Msps, Sampling A/D Converter FEATURES s s s s s s s s s s DESCRIPTION The LTC ®1412 is a 12-bit, 3Msps, sampling A/D converter. This high performance device includes a high dynamic range sample-and-hold and a precision reference. Operating from ± 5V supplies it draws only 150mW. The ± 2.5V input range is optimized for low noise and low distortion. Most high performance op amps also perform best over this range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Outstanding AC performance includes 72dB S/(N + D) and 82dB SFDR at the Nyquist input frequency of 1.5MHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 40MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a high speed 12-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and converter status signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. A digital output driver power supply pin allows direct connection to 3V logic. Sample Rate: 3Msps 72dB S/(N + D) and 82dB SFDR at Nyquist ± 0.35LSB INL and ± 0.25LSB DNL (Typ) Power Dissipation: 150mW External or Internal Reference Operation True Differential Inputs Reject Common Mode Noise 40MHz Full Power Bandwidth Sampling ± 2.5V Bipolar Input Range No Pipeline Delay 28-Pin SSOP Package APPLICATIONS s s s s s s Telecommunications Digital Signal Processing Mulitplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION 5V 10µF AVDD LTC1412 EFFECTIVE NUMBER OF BITS AIN+ S/H AIN– 4.0625V COMP 10µF VREF BUFFER 2k BUSY CS CONVST OGND 1412 TA01 OPTIONAL 3V LOGIC SUPPLY DVDD OVDD Effective Bits and Signal-to-Noise + Distortion vs Input Frequency 12 10 8 6 4 2 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1412 G01 12 12-BIT ADC OUTPUT BUFFERS • • • D11 (MSB) D0 (LSB) 2.5V REFERENCE AGND TIMING AND LOGIC DGND VSS 10µF – 5V U U U 74 68 62 56 S/(N + D) (dB) 1 LTC1412 ABSOLUTE MAXIMUM RATINGS AVDD = DVDD = VDD (Notes 1, 2) PACKAGE/ORDER INFORMATION TOP VIEW AIN+ AIN– VREF REFCOMP AGND D11 (MSB) D10 D9 D8 1 2 3 4 5 6 7 8 9 28 AVDD 27 DVDD 26 VSS 25 BUSY 24 CS 23 CONVST 22 DGND 21 DVDD 20 OVDD 19 OGND 18 D0 17 D1 16 D2 15 D3 Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS)................................. – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1412C................................................ 0°C to 70°C LTC1412I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1412CG LTC1412IG D7 10 D6 11 D5 12 D4 13 DGND 14 G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 110°C, θJA = 95°C/ W Consult factory for Military grade parts. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) (Note 7) With internal reference (Notes 5, 6) MIN q q q q CONDITIONS TYP ± 0.35 ± 0.25 ±2 MAX ±1 ±1 ±6 ±8 ± 15 UNITS Bits LSB LSB LSB LSB LSB ppm/°C 12 IOUT(REF) = 0 q ± 15 A ALOG I PUT SYMBOL PARAMETER VIN IIN CIN tACQ tAP tjitter CMRR (Note 5) CONDITIONS 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V CS = High Between Conversions During Conversions q q q MIN TYP ± 2.5 MAX ±1 UNITS V µA pF pF Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio 10 4 20 – 0.5 1 50 psRMS dB – 2.5V < (AIN = AIN) < 2.5V – 63 2 U W U U WW W U U U ns ns LTC1412 DY A IC ACCURACY SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion Ratio THD SFDR IMD Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.1mA ≤ IOUT ≤ 0.1mA IOUT = 0 DIGITAL I PUTS AND OUTPUTS SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D11 to D0 Hi-Z Output Capacitance D11 to D0 Output Source Current VDD = 5.25V POWER REQUIRE E TS SYMBOL PARAMETER VDD VSS IDD ISS PD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation UW U U U WU (Note 5) CONDITIONS 100kHz Input Signal 1.465MHz Input Signal 100kHz Input Signal, First 5 Harmonics 1.465MHz Input Signal, First 5 Harmonics 1.465MHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz S/(N + D) ≥ 68dB MIN 70 TYP 72.5 72 – 90 – 80 82 – 84 40 4 MAX UNITS dB dB dB dB dB dB MHz MHz U U (Note 5) MIN 2.480 TYP 2.500 ± 15 0.01 0.01 2 4.06 MAX 2.520 UNITS V ppm/°C LSB/ V LSB/ V kΩ V (Note 5) MIN q q q CONDITIONS VDD = 4.75V VIN = 0V to VDD VDD = 4.75V, IO = – 10µA VDD = 4.75V, IO = – 200µA VDD = 4.75V, IO = 160µA VDD = 4.75V, IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V TYP MAX 0.8 ± 10 UNITS V V µA pF V V 2.4 1.4 q q q 4.0 4.75 4.71 0.05 0.10 7 – 10 0.4 ± 10 V V µA pF mA (Note 5) CONDITIONS (Note 10) (Note 10) CS High CS High q q q MIN 4.75 – 4.75 TYP MAX 5.25 – 5.25 UNITS V V mA mA mW 12 18 150 16 28 220 3 LTC1412 TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tTHROUGHPUT tCONV tACQ t1 t2 t3 t4 t5 t6 t7 PARAMETER Maximum Sampling Frequency t8 t9 The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. TI I G DIAGRA CS CONVST t3 BUSY t6 DATA DATA (N – 1) DB11 TO DB0 t4 DATA N DB11 TO DB0 t7 DATA (N + 1) DB11 TO DB0 t5 4 W UW UW (Note 5) CONDITIONS q q q q MIN 3 TYP MAX 333 UNITS MHz ns ns ns ns ns Throughput Time (Acquisition + Conversion) Conversion Time Acquisition Time CS↓ to CONVST↓ Setup Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY↑ (Notes 9, 10) (Note 10) CL = 25pF 240 20 5 20 5 283 50 q q q q 20 – 20 – 25 50 10 35 45 30 35 40 0 20 25 ns ns ns ns ns ns ns ns ns ns ns ns Delay Between Conversions Data Access Time After CS↓ Bus Relinquish Time (Note 10) CL = 25pF q q 8 LTC1412C LTC1412I q q q CONVST High Time Aperture Delay of Sample-and-Hold 20 –1 Note 5: VDD = 5V, fSAMPLE = 3MHz and tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN input with AIN– grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. t1 tCONV t2 1412 TD LTC1412 TYPICAL PERFOR A CE CHARACTERISTICS S/(N + D) and Effective Number of Bits vs Input Frequency 12 10 8 6 4 2 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1412 G01 SIGNAL-TO-NOISE RATIO (dB) EFFECTIVE NUMBER OF BITS DISTORTION (dB) Spurious-Free Dynamic Range vs Input Frequency 0 0 –20 AMPLITUDE (dB) – 40 – 60 – 80 SPURIOUS-FREE DYNAMIC RANGE (dB) –10 – 20 – 30 – 40 – 50 – 60 – 70 – 80 – 90 –100 10K –120 100K 1M FREQUENCY (Hz) 10M 1412 G04 AMPLITUDE (dB) Intermodulation Distortion Plot 0 –10 –20 – 30 AMPLITUDE (dB) DNL (LSBs) fSMPL = 3MHz fIN1 = 85.693359kHz fIN2 = 114.990234kHz – 50 – 60 – 70 – 80 – 90 0 INL (LSBs) – 40 –100 –110 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) 1412 G05 UW Signal-to-Noise Ratio vs Input Frequency 74 68 62 56 S/(N + D) (dB) Distortion vs Input Frequency 0 – 20 – 40 – 60 – 80 THD –100 –120 3RD 2ND 80 70 60 50 40 30 20 10 0 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1412 G02 10 100 1k INPUT FREQUENCY (Hz) 10k 1412 G03 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz 0 fSMPL = 3Msps fIN = 97.412kHz SFDR = 93.3dB SINAD = 73dB –20 – 40 – 60 – 80 Nonaveraged, 4096 Point FFT, Input Frequency = 1.45kHz fSMPL = 3Msps fIN = 1.419kHz SFDR = 83dB SINAD = 72.5dB SNR = 73db –100 –100 –120 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) 1412 F02a 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) 1412 F02B Differential Nonlinearity vs Output Code 1.0 1.0 Integral Nonlinearity vs Output Code 0.5 0.5 0 – 0.5 – 0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 1412 G06 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 1412 G07 5 LTC1412 TYPICAL PERFOR A CE CHARACTERISTICS AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) Power Supply Feedthrough vs Ripple Frequency 0 COMMON MODE REJECTION (dB) 10M 1412 G08 – 20 – 40 – 60 VSS – 80 –100 –120 1k 10k 100k 1M RIPPLE FREQUENCY (Hz) VDD DGND PIN FUNCTIONS AIN+ (Pin 1): Positive Analog Input. ± 2.5V input range when AIN– is grounded. ± 2.5V differential if AIN– is driven. AIN– (Pin 2): Negative Analog Input. Can be grounded or driven differentially with AIN+. VREF (Pin 3): 2.5V Reference Output. REFCOMP (Pin 4): 4.06V Reference Bypass Pin. Bypass to AGND with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic). AGND (Pin 5): Analog Ground. D11 to D4 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground for Internal Logic. D3 to D0 (Pins 15 to 18): Three-State Data Outputs. OGND (Pin 19): Digital Ground for the Output Drivers. OVDD (Pin 20): Positive Supply for the Output Drivers. Tie to Pin 28 when driving 5V logic. Tie to 3V when driving 3V logic. DVDD (Pin 21): 5V Positive Supply. Tie to Pin 28. Bypass to AGND with 0.1µF ceramic. DGND (Pin 22): Digital Ground for Internal Logic. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): Chip Select. This input must be low for the ADC to recognize the CONVST inputs. BUSY (Pin 25): The BUSY Output Shows the Converter Status. It is low when a conversion is in progress. VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic). DVDD (Pin 27): 5V Positive Supply. Tie to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF ceramic (or 10µF tantalum in parallel with 0.1µF ceramic). 6 UW Input Common Mode Rejection vs Input Frequency 80 70 60 50 40 30 20 10 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1412 G09 U U U LTC1412 FUNCTIONAL BLOCK DIAGRA AIN+ AIN– 2k VREF 2.5V REF ZEROING SWITCHES REF AMP REFCOMP (4.06V) AGND DGND INTERNAL CLOCK TEST CIRCUITS Load Circuits for Access Timing 5V 1k DBN 1k CL DBN CL A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL 1412 TC01 APPLICATIONS INFORMATION Conversion Details The LTC1412 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 50ns will provide enough time for the W CSAMPLE CSAMPLE AVDD DVDD U W U U U U + 12-BIT CAPACITIVE DAC COMP – 12 SUCCESSIVE APPROXIMATION REGISTER OUTPUT LATCHES • • • D11 D0 OVDD CONTROL LOGIC OGND 1412 BD CONVST CS BUSY Load Circuits for Output Float Delay 5V 1k DBN 1k 100pF DBN 100pF A) VOH TO HI-Z B) VOL TO HI-Z 1412 TC02 7 LTC1412 APPLICATIONS INFORMATION AIN+ SAMPLE HOLD AIN– SAMPLE HOLD CDAC+ CSAMPLE– CSAMPLE+ 0 –20 fSMPL = 3Msps fIN = 97.412kHz SFDR = 93.3dB SINAD = 73dB ZEROING SWITCHES HOLD AMPLITUDE (dB) HOLD + VDAC+ CDAC– COMP – 12 SAR VDAC– OUTPUT LATCHES 1412 F01 Figure 1. Simplified Block Diagram sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 12-bit data word) which represents the difference of AIN+ and AIN– are loaded into the 12-bit output latches. Dynamic Performance The LTC1412 has excellent high speed sampling capability. FFT (Fast Four Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1412 FFT plot. Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited AMPLITUDE (dB) 8 U W U U – 40 – 60 – 80 –100 –120 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) 1412 F02a • D11 • • D0 Figure 2a. LTC1412 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz 0 –20 – 40 – 60 – 80 fSMPL = 3Msps fIN = 1.419kHz SFDR = 83dB SINAD = 72.5dB SNR = 73db –100 –120 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) 1412 F02B Figure 2b. LTC1412 Nonaveraged, 4096 Point FFT, Input Frequency = 1.45MHz to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 3MHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 1.5MHz. Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 3MHz the LTC1412 maintains near ideal ENOBs up to the Nyquist input frequency of 1.5MHz. Refer to Figure 3. LTC1412 APPLICATIONS INFORMATION 12 10 8 6 4 2 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1412 G01 74 68 62 56 EFFECTIVE NUMBER OF BITS Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20 log 2 2 2 2 V2 + V3 + V4 + . . .Vn AMPLITUDE (dB) V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through Nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1412 has good distortion performance up to the Nyquist frequency and beyond. 0 – 20 DISTORTION (dB) – 40 – 60 – 80 THD 3RD 2ND –100 –120 10 100 1k INPUT FREQUENCY (Hz) 10k 1412 G03 Figure 4. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can U W U U produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: S/(N + D) (dB) IMD fa + fb = 20 log 0 –10 –20 – 30 – 40 – 50 – 60 – 70 – 80 – 90 –100 –110 0 200 ( ) Amplitude at fa ± fb Amplitude at f a fSMPL = 3MHz fIN1 = 85.693359kHz fIN2 = 114.990234kHz ( ) 400 600 800 1000 1200 1400 FREQUENCY (kHz) 1412 G05 Figure 5. Intermodulation Distortion Plot Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full Power and Full Linear Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1412 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with fre- 9 LTC1412 APPLICATIONS INFORMATION quencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1412 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and AIN– inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1412 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 50ns for full throughput rate). 10 ACQUISITION TIME (µs) 1 0.1 0.01 10 100 1k 10k SOURCE RESISTANCE (Ω) 100k 1412 F06 Figure 6. Acquisition Time vs Source Resistance Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (