LTC1417IGN

LTC1417 Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O FEATURES s s s s s s s s s s s s DESCRIPTIO 16-Pin Narrow SSOP Package (SO-8 Footprint) Sample Rate: 400ksps ±1.25LSB INL and ±1LSB DNL Max Power Dissipation: 20mW (Typ) Single Supply 5V or ± 5V Operation Serial Data Output No Missing Codes Over Temperature Power Shutdown: Nap and Sleep External or Internal Reference Differential High Impedance Analog Input Input Range: 0V to 4.096V or ± 2.048V 81dB S/(N + D) and – 95dB THD at Nyquist The LTC ®1417 is a low power, 400ksps, 14-bit A/D converter. This versatile device can operate from a single 5V or ± 5V supplies. An onboard high performance sample-andhold, a precision reference and internal trimming minimize external circuitry requirements. The low 20mW power dissipation is made even more attractive with two userselectable power shutdown modes. The LTC1417 converts 0V to 4.096V unipolar inputs when using a 5V supply and ± 2.048V bipolar inputs when using ± 5V supplies. DC specs include ± 1.25LSB INL, ± 1LSB DNL and no missing codes over temperature. Outstanding AC performance includes 81dB S/(N + D) and 95dB THD at a Nyquist input frequency of 200kHz. The internal clock is trimmed for 2µs maximum conversion time. A separate convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s High Speed Data Acquisition Digital Signal Processing Isolated Data Acquisition Systems Audio and Telecom Processing Spectrum Instrumentation EQUIVALE T BLOCK DIAGRA 5V 10µF 16 LTC1417 AIN+ AIN– 1 2 S/H 14-BIT ADC 14 VDD A 400kHz, 14-Bit Sampling A/D Converter in a Narrow 16-Lead SSOP Package Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency 14 12 86 80 74 68 EFFECTIVE BITS 6 SERIAL PORT 7 8 9 REFCOMP 10µF 4 4.096V BUFFER EXTCLKIN SCLK CLKOUT DOUT VREF 1µF 3 8k 2.5V REFERENCE TIMING AND LOGIC 14 BUSY 12 RD 13 CONVST 11 SHDN 1417 TA01 5 AGND 15 VSS 10 (0V OR – 5V) DGND U 10 8 6 4 2 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1417 TA02 W U U 62 1 S/(N + D) (dB) LTC1417 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW AIN+ AIN– VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT 1 2 3 4 5 6 7 8 16 VDD 15 VSS 14 BUSY 13 CONVST 12 RD 11 SHDN 10 DGND 9 DOUT Positive Supply Voltage (VDD) .................................. 6V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... – 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation .................. – 0.3V to (VDD + 0.3V) Bipolar Operation............ (VSS – 0.3) to (VDD + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ............................... – 0.3V to 10V Bipolar Operation.........................(VSS – 0.3V) to 10V Digital Output Voltage Unipolar Operation ................... – 0.3 to (VDD + 0.3V) Bipolar Operation........... (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1417C .............................................. 0°C to 70°C LTC1417I ............................................ – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1417ACGN LTC1417CGN LTC1417AIGN LTC1417IGN GN PART MARKING 1417A 1417 1417AI 1417I GN PACKAGE 16-LEAD (NARROW) PLASTIC SSOP TJMAX = 110°C, θJA = 95°C/W Consult factory for Military grade parts. CO VERTER CHARACTERISTICS PARAMETER Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Full-Scale Error Full-Scale Tempco (Note 12) External Reference (Note 8) Internal Reference External Reference = 2.5V (Note 7) CONDITIONS The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are measured while using the internal reference unless otherwise noted. (Notes 5, 6) MIN q q q q LTC1417 TYP MAX LTC1417A MIN TYP MAX 14 14 UNITS Bits Bits 14 13 ± 0.8 0.33 ±2 ± 0.7 ±1.5 ±5 ±15 ±5 ±15 ±5 ± 20 ± 60 ± 30 ± 0.5 ±1.25 ± 0.35 0.33 ±2 ± 15 ±5 ±10 ± 20 ±1 ± 10 ± 60 ± 15 ±1 LSBRMS LSB LSB LSB ppm/°C ppm/°C ppm/°C q IOUT(REF) = 0, Internal Reference, 0°C ≤ TA ≤ 70°C IOUT(REF) = 0, Internal Reference, – 40°C ≤ TA ≤ 85°C IOUT(REF) = 0, External Reference A ALOG I PUT SYMBOL PARAMETER VIN IIN The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS 4.75V ≤ VDD ≤ 5.25V (Unipolar) 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V (Bipolar) CONVST = High q q q MIN TYP 0 to 4.096 ± 2.048 MAX UNITS V V Analog Input Range (Note 9) Analog Input Leakage Current ±1 2 U LSB LSB µA W U U WW W U U U LTC1417 A ALOG I PUT SYMBOL PARAMETER CIN tACQ tAP tjitter CMRR The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS Between Conversions (Sample Mode) During Conversions (Hold Mode) q Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Time Sample-and-Hold Aperture Time Jitter Analog Input Common Mode Rejection Ratio DY A IC ACCURACY The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL S/(N + D) THD SFDR IMD PARAMETER Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth S/(N + D) ≥ 77dB CONDITIONS 100kHz Input Signal 100kHz Input Signal, First Five Harmonics 200kHz Input Signal fIN1 = 97.3kHz, fIN2 = 104.6kHz q q I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance CONDITIONS IOUT = 0 IOUT = 0, 0°C ≤ TA ≤ 70°C IOUT = 0, – 40°C ≤ TA ≤ 85°C 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.1mA ≤ |IOUT| ≤ 0.1mA The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN q DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage High-Z Output Leakage DOUT, CLKOUT High-Z Output Capacitance DOUT, CLKOUT Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN q q q U U U U WU U U MIN TYP 14 3 150 –1.5 5 MAX UNITS pF pF 500 ns ns psRMS dB dB 0V < (AIN+ = AIN–) < 4.096V (Unipolar) – 2.048V < (AIN+ = AIN–) < 2.048V (Bipolar) 65 65 MIN 79 – 85 TYP 81 – 95 – 98 – 97 10 0.8 MAX UNITS dB dB dB dB MHz MHz U TYP 2.500 ± 10 ± 20 0.05 0.05 8 MAX 2.520 UNITS V ppm/°C ppm/°C LSB/V LSB/V kΩ 2.480 TYP MAX 0.8 ± 10 UNITS V V µA pF V V 2.4 1.4 VDD = 4.75V, IO = – 10µA VDD = 4.75V, IO = – 200µA VDD = 4.75V, IO = 160µA VDD = 4.75V, IO = – 1.6mA VOUT = 0V to VDD, RD High RD High (Note 9) VOUT = 0V VOUT = VDD 4.74 q q q q 4.0 0.05 0.10 0.4 ± 10 15 – 10 10 V V µA pF mA mA 3 LTC1417 POWER REQUIRE E TS SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage (Notes 10, 11) Negative Supply Voltage (Note 10) Positive Supply Current Nap Mode Sleep Mode ISS Negative Supply Current Nap Mode Sleep Mode Power Dissipation The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS Bipolar Only (VSS = 0V for Unipolar) Unipolar, RD High (Note 5) Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V Unipolar Bipolar q q PDIS The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ + tCONV t1 t2 t3 t4 t5 t6 t7 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Plus Conversion Time SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY↑ Delay Between Conversions Wait Time RD↓ After BUSY↑ Data Access Time After RD↓ CL = 25pF q TI I G CHARACTERISTICS t8 t9 t10 t11 t12 fSCLK fEXTCLKIN tdEXTCLKIN Bus Relinquish Time RD Low Time CONVST High Time Delay Time, SCLK↓ to DOUT Valid Time from Previous Data Remain Valid After SCLK↓ Shift Clock Frequency External Conversion Clock Frequency Delay Time, CONVST↓ to External Conversion Clock Input (Note 9) CL = 25pF CL = 25pF (Note 13) 4 UW MIN 4.75 – 4.75 TYP MAX 5.25 – 5.25 UNITS V V mA mA µA µA mA µA nA mW mW 4.0 4.3 750 0.1 2.0 0.7 1.5 20.0 31.5 5.5 6.0 q 2.8 q q 27.5 44 UW CONDITIONS q q q q MIN 400 TYP 1.8 150 2.1 500 MAX 2.25 500 2.5 UNITS kHz µs ns µs ns ns (Note 10) (Notes 10, 11) CL = 25pF CL = 25pF (Note 10) q q q q q 40 35 7 250 –5 15 20 30 40 40 55 35 t7 40 15 5 0 0.05 10 20 9 20 40 12 70 ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz µs CL = 100pF q q q q q q q q q LTC1417 The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL tH SCLK tL SCLK tH EXTCLKIN tL EXTCLKIN PARAMETER SCLK High Time SCLK Low Time EXTCLKIN High Time EXTCLKIN Low Time CONDITIONS (Note 9) (Note 9) q q q q TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA without latchup if the pin is driven below VSS (ground for unipolar mode) or above VDD. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded. TYPICAL PERFOR A CE CHARACTERISTICS Typical INL Curve 1.0 1.0 SIGNAL/(NOISE + DISTORTION) (dB) 0.5 DNL ERROR (LSBs) INL (LSBs) 0 –0.5 –1.0 0 4096 8192 OUTPUT CODE 1417 G01 12288 UW UW MIN 10 10 0.04 0.04 TYP MAX UNITS ns ns 20 20 µs µs Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 625ns after conversion start or after BUSY rises. Note 12: Typical RMS noise at the code transitions. See Figure 2 for histogram. Note 13: t11 of 40ns maximum allows fSCLK up to 10MHz for rising capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with 5ns setup time. (TA = 25°C) S/(N + D) vs Input Frequency and Amplitude 90 80 70 60 50 40 30 20 10 0 1k 100k 10k INPUT FREQUENCY (Hz) 1M 1417 G03 Differential Nonlinearity vs Output Code VIN = 0dB 0.5 VIN = – 20dB 0 VIN = – 60dB – 0.5 –1.0 16384 0 4096 12288 8192 OUTPUT CODE 16384 1417 G02 5 LTC1417 TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C) Signal-to-Noise Ratio vs Input Frequency AMPLITUDE (dB BELOW THE FUNDAMENTAL) 90 80 SIGNAL-TO-NOISE RATIO (dB) SPURIOUS FREE DYNAMIC RANGE (dB) 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1417 G04 Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz 0 –20 fSAMPLE = 400kHz fIN = 10.05859375kHz SFDR = –97.44dB SINAD = 81.71dB 0 AMPLITUDE (dB) AMPLITUDE (dB) –40 –60 –80 AMPLITUDE (dB) –40 –60 –80 –100 –120 0 50 100 150 FREQUENCY (kHz) Power Supply Feedthrough vs Ripple Frequency 0 COMMON MODE REJECTION (dB) 60 50 40 30 20 10 0 CHANGE IN OFFSET VOTLAGE (LSB) VRIPPLE = 60mV fSAMPLE = 400kHz 20 fIN = 200kHz FEEDTHROUGH (dB) 40 60 80 VSS 100 120 1k 10k 100k 1M RIPPLE FREQUENCY (Hz) 10M 1417 G10 VDD DGND 6 UW Distortion vs Input Frequency 0 – 20 – 40 – 60 – 80 THD –100 3RD –120 2ND 1 10 100 INPUT FREQUENCY (kHz) 1000 1417 G05 Spurious-Free Dynamic Range vs Input Frequency 0 –20 –40 –60 –80 –100 –120 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1417 G06 Nonaveraged, 4096 Point FFT, Input Frequency = 200kHz fSAMPLE = 400kHz fIN = 197.949188kHz –20 SFDR = –98dB SINAD = 81.1dB 0 Intermodulation Distortion Plot fSAMPLE = 400kHz fIN1 = 97.303466kHz – 20 fIN2 = 104.632568kHz VIN = 4.096VP-P – 40 – 60 – 80 –100 –120 –100 –120 0 50 100 150 FREQUENCY (kHz) 200 1417 G08 200 1417 G07 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) 1417 G09 Input Common Mode Rejection vs Input Frequency 70 10 9 8 7 6 5 4 3 2 1 0 1 100 10 INPUT FREQUENCY (kHz) 1000 1417 G11 Input Offset Voltage Shift vs Source Resistance 1 100 1k 10k 100k 10 INPUT SOURCE RESISTANCE (Ω) 1M 1417 G12 LTC1417 TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C) VDD Supply Current vs Temperature (Unipolar Mode) 6 5 4 3 2 1 0 –75 –50 –25 6 5 4 3 2 1 0 –75 –50 –25 VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA) VSS SUPPLY CURRENT (mA) 0 25 50 75 100 125 150 TEMPERATURE (°C) 1417 G14 0 25 50 75 100 125 150 TEMPERATURE (°C) 1417 G13 VDD Supply Current vs Sampling Frequency (Unipolar Mode) 5.0 4.5 VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA) 5.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 SAMPLING FREQUENCY (kHz) 1417 G16 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 SAMPLING FREQUENCY (kHz) 1417 G17 VSS SUPPLY CURRENT (mA) 4.0 PIN FUNCTIONS AIN+ (Pin 1): Positive Analog Input. AIN– (Pin 2): Negative Analog Input. VREF (Pin 3): 2.50V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.096V Reference Output. Bypass to AGND using 10µF tantalum in parallel with 0.1µF ceramic. AGND (Pin 5): Analog Ground. EXTCLKIN (Pin 6): External Conversion Clock Input. A 5V input will enable the internal conversion clock. SCLK (Pin 7): Data Clock Input. CLKOUT (Pin 8): Conversion Clock Output. DOUT (Pin 9): Serial Data Output. DGND (Pin 10): Digital Ground. SHDN (Pin 11): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by RD. RD = 0V for Nap mode and RD = 5V for Sleep mode. RD (Pin 12): Read Input. This enables the output drivers. RD also sets the shutdown mode when SHDN goes low. RD and SHDN low selects the quick wake-up Nap mode, RD high and SHDN low selects Sleep mode. UW VDD Supply Current vs Temperature (Bipolar Mode) 3.0 2.5 2.0 1.5 1.0 0.5 VSS Supply Current vs Temperature (Bipolar Mode) 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1417 G15 VDD Supply Current vs Sampling Frequency (Bipolar Mode) 2.5 VSS Supply Current vs Sampling Frequency (Bipolar Mode) 4.0 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 SAMPLING FREQUENCY (kHz) 1417 G18 U U U 7 LTC1417 PIN FUNCTIONS CONVST (Pin 13): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 14): The BUSY output shows the converter status. It is low when a conversion is in progress. VSS (Pin 15): Negative Supply, –5V for Bipolar Operation. Bypass to AGND using 10µF tantalum in parallel with 0.1µF ceramic. Analog ground for unipolar operation. VDD (Pin 16): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. TEST CIRCUITS Load Circuits for Access Timing 5V 1k DOUT 1k DGND A) HI-Z TO VOH AND VOL TO VOH CL DOUT CL DGND B) HI-Z TO VOL AND VOH TO VOL 1417 TC01 FUNCTIONAL BLOCK DIAGRA AIN+ 1 CSAMPLE 16 CSAMPLE AIN– VREF 2 3 8k 2.5V REF ZEROING SWITCHES 15 REF AMP 14-BIT CAPACITIVE DAC REFCOMP (4.096V) AGND DGND 4 5 10 INTERNAL CLOCK MUX SUCCESSIVE APPROXIMATION REGISTER 14 SHIFT REGISTER 9 7 CONTROL LOGIC DOUT SCLK 6 EXTCLKIN 11 SHDN 8 W U U U U U Load Circuits for Output Float Delay 5V 1k DOUT 1k 30pF DOUT 30pF A) VOH TO HI-Z B) VOL TO HI-Z 1417 TC02 VDD VSS (0V FOR UNIPOLAR MODE –5V FOR BIPOLAR MODE) + COMP – 13 CONVST 12 RD 8 14 1417 BD CLKOUT BUSY LTC1417 APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1417 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CONVST input. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 500ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, placing the comparator in compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 14-bit data word) that represent the difference of AIN+ and AIN– are output through the serial pin DOUT. DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 2, the distribution of output code is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition is about 0.33LSB. 4000 3500 3000 2500 COUNTS AIN+ SAMPLE CSAMPLE HOLD + ZEROING SWITCHES HOLD AIN– SAMPLE CSAMPLE– HOLD CDAC+ HOLD + VDAC+ CDAC– COMP – VDAC– 14 SAR SHIFT REGISTER Figure 1. Simplified Block Diagram U W U U 2000 1500 1000 500 0 –2 –1 0 CODE 1417 F02 1 2 Figure 2. Histogram for 4096 Conversions DYNAMIC PERFORMANCE The LTC1417 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise performance at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies beyond the fundamental. Figure 3 shows a typical LTC1417 FFT plot. DOUT 1417 F01 9 LTC1417 APPLICATIONS INFORMATION 0 –20 fSAMPLE = 400kHz fIN = 10.05859375kHz SFDR = –97.44dB SINAD = 81.71dB AMPLITUDE (dB) –40 –60 –80 –100 –120 0 50 100 150 FREQUENCY (kHz) 200 1417 G07 Figure 3a. LTC1417 Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz EFFECTIVE BITS fSAMPLE = 400kHz fIN = 197.949188kHz –20 SFDR = –98dB SINAD = 81.1dB 0 AMPLITUDE (dB) –40 –60 –80 –100 –120 0 50 100 150 FREQUENCY (kHz) 200 1417 G08 Figure 3b. LTC1417 Nonaveraged, 4096 Point FFT, Input Frequency = 200kHz Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 3b shows a typical spectral content with a 400kHz sampling rate and a 200kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 200kHz. 10 U W U U Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB (N) = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1417 maintains near ideal ENOBs up to the Nyquist input frequency of 200kHz (refer to Figure 4). 14 12 10 8 6 4 2 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1417 TA02 86 80 74 68 62 S/(N + D) (dB) Figure 4. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V22 + V32 + V42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 5. The LTC1417 has good distortion performance up to the Nyquist frequency and beyond. THD = 20Log LTC1417 APPLICATIONS INFORMATION AMPLITUDE (dB BELOW THE FUNDAMENTAL) 0 – 20 – 40 – 60 – 80 THD –100 3RD –120 2ND 1 10 100 INPUT FREQUENCY (kHz) 1000 1417 G05 Figure 5. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd-order IMD products can be expressed by the following formula: fSAMPLE = 400kHz fIN1 = 97.303466kHz – 20 fIN2 = 104.632568kHz VIN = 4.096VP-P AMPLITUDE (dB) 0 – 40 – 60 – 80 –100 –120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) 1417 G09 Figure 6. Intermodulation Distortion Plot U W U U IMD fa + fb = 20Log ( ) Amplitude at fa ± fb Amplitude at fa ( ) Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB from a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1417 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1417 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and AIN– inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1417 inputs can be driven directly. As source impedance increases, so will acquisition time (see Figure 7). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts — 500ns for full throughput rate. 11 LTC1417 APPLICATIONS INFORMATION 100 ACQUISITION TIME (µs) 10 1 0.1 0.01 1 10 100 1k 10k SOURCE RESISTANCE (Ω) 100k 1417 F07 Figure 7. tACQ vs Source Resistance Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, choose an amplifier that has a low output impedance (