LTC1418IG

LTC1418 Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O FEATURES s s s s s s s s s s s s DESCRIPTION The LTC ®1418 is a low power, 200ksps, 14-bit A/D converter. Data output is selectable for 14-bit parallel or serial format. This versatile device can operate from a single 5V or ± 5V supply. An onboard high performance sample-and-hold, a precision reference and internal timing minimize external circuitry requirements. The low 15mW power dissipation is made even more attractive with two user selectable power shutdown modes. The LTC1418 converts 0V to 4.096V unipolar inputs from a single 5V supply and ± 2.048V bipolar inputs from ± 5V supplies. DC specs include ± 1.25LSB INL, ± 1LSB DNL and no missing codes over temperature. Outstanding AC performance includes 82dB S/(N + D) and 94dB THD at the Nyquist input frequency of 100kHz. The flexible output format allows either parallel or serial I/O. The SPI/MICROWIRETM compatible serial I/O port can operate as either master or slave and can support clock frequencies from DC to 10MHz. A separate convert start input and a data ready signal (BUSY) allow easy control of conversion start and data transfer. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. Single Supply 5V or ± 5V Operation Sample Rate: 200ksps ± 1.25LSB INL and ± 1LSB DNL Max Power Dissipation: 15mW (Typ) Parallel or Serial Data Output No Missing Codes Over Temperature Power Shutdown: Nap and Sleep External or Internal Reference Differential High Impedance Analog Input Input Range: 0V to 4.096V or ± 2.048V 81.5dB S/(N + D) and – 94dB THD at Nyquist 28-Pin Narrow PDIP and SSOP Packages APPLICATIONS s s s s s s Remote Data Acquisition Battery Operated Systems Digital Signal Processing Isolated Data Acquisition Systems Audio and Telecom Processing Medical Instrumentation TYPICAL APPLICATION Low Power, 200kHz, 14-Bit Sampling A/D Converter 5V 10µF VDD LTC1418 AIN+ S/H AIN– 4.096V REFCOMP 10µF BUFFER 14-BIT ADC 14 SELECTABLE SERIAL/ PARALLEL PORT D5 D4 (EXTCLKIN) D3 (SCLK) D2 (CLKOUT) D1 (DOUT) D0 (EXT/INT) BUSY CS RD CONVST SHDN SER/PAR D13 1.0 0.5 INL (LSBs) –0.5 8k VREF 1µF 2.5V REFERENCE TIMING AND LOGIC –1.0 0 4096 8192 OUTPUT CODE 12288 16384 AGND VSS (0V OR – 5V) DGND 1418 TA02 1418 TA01 U 0 U U Typical INL Curve 1 LTC1418 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PACKAGE/ORDER INFORMATION TOP VIEW AIN+ AIN – VREF REFCOMP AGND D13 (MSB) D12 D11 D10 1 2 3 4 5 6 7 8 9 28 VDD 27 VSS 26 BUSY 25 CS 24 CONVST 23 RD 22 SHDN 21 SER/PAR 20 D0 (EXT/INT) 19 D1 (DOUT) 18 D2 (CLKOUT) 17 D3 (SCLK) 16 D4 (EXTCLKIN) 15 D5 N PACKAGE 28-LEAD NARROW PDIP Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) Bipolar Operation Only ........................... – 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation .................. – 0.3V to (VDD + 0.3V) Bipolar Operation........... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ................................– 0.3V to 10V Bipolar Operation.........................(VSS – 0.3V) to 10V Digital Output Voltage Unipolar Operation .................. – 0.3V to (VDD + 0.3V) Bipolar Operation........... (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation.............................................. 500mW Operation Temperature Range LTC1418C................................................ 0°C to 70°C LTC1418I............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1418ACG LTC1418ACN LTC1418AIG LTC1418AIN LTC1418CG LTC1418CN LTC1418IG LTC1418IN D9 10 D8 11 D7 12 D6 13 DGND 14 G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 110°C, θJA = 95°C/ W (G) TJMAX = 110°C, θJA = 100°C/ W (N) Consult factory for Military grade parts. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) Internal Reference External Reference = 2.5V (Note 7) CONDITIONS With internal reference (Notes 5, 6) unless otherwise noted. MIN q q q q LTC1418 TYP MAX ± 0.8 ± 0.7 ±5 ± 10 ±5 ±2 ± 1.5 ± 20 ± 60 ± 30 MIN 14 LTC1418A TYP MAX ± 0.5 ± 0.35 ±2 ± 20 ±5 ± 10 ± 20 ±1 ± 1.25 ±1 ± 10 ± 60 ± 15 ± 45 UNITS Bits LSB LSB LSB LSB LSB ppm/°C ppm/°C ppm/°C 13 IOUT(REF) = 0, Internal Reference, Commercial IOUT(REF) = 0, Internal Reference, Industrial IOUT(REF) = 0, External Reference q ± 15 ±5 A ALOG I PUT SYMBOL PARAMETER VIN IIN CIN tACQ (Note 5) CONDITIONS 4.75V ≤ VDD ≤ 5.25V (Unipolar) 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V (Bipolar) CS = High Between Conversions (Sample Mode) During Conversions (Hold Mode) Commercial Industrial q q q q q MIN TYP 0 to 4.096 ± 2.048 MAX UNITS V V Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time ±1 25 5 300 300 1000 1000 2 U W U U WW W U U U µA pF pF ns ns LTC1418 DY A IC ACCURACY SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion Ratio THD SFDR IMD Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance CONDITIONS IOUT = 0 IOUT = 0, Commercial IOUT = 0, Industrial 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.1mA ≤ IOUT ≤ 0.1mA DIGITAL I PUTS AND OUTPUTS SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D13 to D0 Hi-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V POWER REQUIRE E TS SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage (Notes 10, 11) Negative Supply Voltage (Note 10) Positive Supply Current ISS Negative Supply Current Nap Mode Sleep Mode PDIS Power Dissipation UW U U U WU U (Note 5) CONDITIONS 97.5kHz Input Signal 100kHz Input Signal, First 5 Harmonics 100kHz Input Signal fIN1 = 97.7kHz, fIN2 = 104.2kHz S/(N + D) ≥ 77dB q q q MIN 79 86 TYP 81.5 – 94 95 – 90 5 0.5 MAX – 86 UNITS dB dB dB dB MHz MHz U (Note 5) MIN 2.480 q TYP 2.500 ± 10 ± 20 0.05 0.05 8 MAX 2.520 ± 45 UNITS V ppm/°C ppm/°C LSB/ V LSB/ V kΩ (Note 5) MIN q q q TYP MAX 0.8 ± 10 UNITS V V µA pF V V 2.4 VIN = 0V to VDD VDD = 4.75V, IO = – 10µA VDD = 4.75V, IO = – 200µA VDD = 4.75V, IO = 160µA VDD = 4.75V, IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V VOUT = VDD 1.4 4.74 q q q q 4.0 0.05 0.10 0.4 ± 10 15 – 10 10 V V µA pF mA mA (Note 5) CONDITIONS Bipolar Only (VSS = 0V for Unipolar) Unipolar, RD High (Note 5) Bipolar, RD High (Note 5) SHDN = 0V, CS = 0V (Note 12) SHDN = 0V, CS = 5V (Note 12) Bipolar, RD High (Note 5) SHDN = 0V, CS = 0V (Note 12) SHDN = 0V, CS = 5V (Note 12) Unipolar Bipolar q q MIN 4.75 – 4.75 TYP MAX 5.25 – 5.25 UNITS V V mA mA µA µA mA µA µA mW mW Nap Mode Sleep Mode 3.0 3.9 570 2 1.4 0.1 0.1 15.0 26.5 4.3 4.5 q 1.8 q q 21.5 31.5 3 LTC1418 TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ + tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Plus Conversion Time CS to RD Setup Time CS↓ to CONVST↓ Setup Time CS↓ to SHDN↓ Setup Time to Ensure Nap Mode SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY↑ q t11 t12 t13 t14 t15 fSCLK fEXTCLKIN tdEXTCLKIN tH SCLK tL SCLK tH EXTCLKIN tL EXTCLKIN The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VCC without latchup. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = 0V or – 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended input with AIN– grounded. 4 UW (Note 5) CONDITIONS q q q q MIN 200 TYP 3.4 0.3 3.7 MAX 4 1 5 UNITS kHz µs µs µs ns ns ns (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Note 10) (Notes 10, 11) CL = 25pF q q q 0 40 40 500 40 35 20 15 500 –5 15 30 40 40 55 20 25 30 35 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns q q Delay Between Conversions Wait Time RD↓ After BUSY↑ Data Access Time After RD↓ (Note 10) CL = 25pF q q q CL = 100pF q 20 8 Bus Relinquish Time Commercial Industrial RD Low Time CONVST High Time Delay Time, SCLK↓ to DOUT Valid Time from Previous Data Remain Valid After SCLK↓ Shift Clock Frequency External Conversion Clock Frequency Delay Time, CONVST↓ to External Conversion Clock Input SCLK High Time SCLK Low Time EXTCLKIN High Time EXTCLKIN Low Time CL = 25pF (Note 9) CL = 25pF (Note 9) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) 10 20 q q q q q t10 40 35 15 0 0.03 25 12.5 4.5 533 70 ns ns MHz MHz µs ns ns 250 250 ns ns Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion, it can create small errors. For best performance ensure that CONVST returns high either within 2.1µs after the conversion starts or after BUSY rises. Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at 0V or 5V. See Power Shutdown. LTC1418 TYPICAL PERFORMANCE CHARACTERISTICS Typical INL Curve 1.0 SIGNAL/(NOISE + DISTORTION) (dB) 0.5 DNL ERROR (LSBs) INL (LSBs) 0 –0.5 –1.0 0 4096 8192 OUTPUT CODE 1418 TA02 12288 Signal-to-Noise Ratio vs Input Frequency AMPLITUDE (dB BELOW THE FUNDAMENTAL) 90 80 SIGNAL-TO -NOISE RATIO (dB) SPURIOUS-FREE DYNAMIC RANGE (dB) 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1418 G02 Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz 0 –20 AMPLITUDE (dB) fSAMPLE = 200kHz fIN = 9.9609375kHz SFDR = 99.32 SINAD = 82.4 AMPLITUDE (dB) –40 –60 –80 –40 –60 –80 AMPLITUDE (dB) –100 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 F02a UW Differential Nonlinearity vs Output Code 1.0 90 80 70 60 50 40 30 20 10 0 S/(N + D) vs Input Frequency and Amplitude VIN = 0dB VIN = – 20dB 0.5 0 – 0.5 VIN = – 60dB –1.0 16384 0 4096 12288 8192 OUTPUT CODE 16384 1418 G06 1k 100k 10k INPUT FREQUENCY (Hz) 1M 1418 G01 Distortion vs Input Frequency 0 –20 –40 –60 –80 –100 –120 3RD THD 2ND 0 –20 –40 –60 –80 –100 Spurious-Free Dynamic Range vs Input Frequency 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1418 G03 –120 10k 100k INPUT FREQUENCY (Hz) 1M 1418 G04 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz 0 –20 fSAMPLE = 200kHz fIN = 97.509765kHz SFDR = 94.29 SINAD = 81.4 0 – 20 – 40 – 60 – 80 Intermodulation Distortion Plot fSAMPLE = 200kHz fIN1 = 97.65625kHz fIN2 = 104.248046kHz –100 –120 –100 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 F02b 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 G05 5 LTC1418 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Feedthrough vs Ripple Frequency 0 90 CHANGE IN OFFSET VOLTAGE (LSB) 80 COMMON MODE REJECTION (dB) –20 DISTORTION (dB) –40 –60 –80 VSS VDD DGND –100 –120 1k 10k 100k 1M FREQUENCY (Hz) VDD Supply Current vs Temperature (Unipolar Mode) 5 VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA) VSS SUPPLY CURRENT (mA) 4 3 2 1 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1418 G11 VDD Supply Current vs Sampling Frequency (Unipolar Mode) 5 5 VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA) VSS SUPPLY CURRENT (mA) 4 3 2 1 0 0 100 150 200 250 50 SAMPLING FREQUENCY (kHz) 300 6 UW 1418 G08 Input Common Mode Rejection vs Input Frequency 10 9 8 7 6 5 4 3 2 1 0 1 10 100 1k 10k 100k INPUT FREQUENCY (Hz) 1M Input Offset Voltage Shift vs Source Resistance 70 60 50 40 30 20 10 10M 0 10 100 100k 1k 10k INPUT SOURCE RESISTANCE (Ω) 1M 1418 G10 1418 G09 VDD Supply Current vs Temperature (Bipolar Mode) 5 2.0 1.8 VSS Supply Current vs Temperature (Bipolar Mode) 4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 3 2 1 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1418 G12 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1418 G13 VDD Supply Current vs Sampling Frequency (Bipolar Mode) 2.0 1.8 4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 150 200 250 100 SAMPLING FREQUENCY (kHz) 300 0 VSS Supply Current vs Sampling Frequency (Bipolar Mode) 3 2 1 0 50 150 200 250 100 SAMPLING FREQUENCY (kHz) 300 1418 G14 1418 G15 1418 G16 LTC1418 PIN FUNCTIONS AIN+ (Pin 1): Positive Analog Input. AIN– (Pin 2): Negative Analog Input. VREF (Pin 3): 2.50V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.096V Reference Bypass Pin. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs (Parallel). D13 is the most significant bit. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 (Pin 15): Three-State Data Output (Parallel). D4 (EXTCLKIN) (Pin 16): Three-State Data Output (Parallel). Conversion clock input (serial) when Pin 20 (EXT/INT) is tied high. D3 (SCLK) (Pin 17): Three-State Data Output (Parallel). Data clock input (serial). D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel). Conversion clock output (serial). D1 (DOUT) (Pin 19): Three-State Data Output (Parallel). Serial data output (serial). D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel). Conversion clock selector (serial). An input low enables the internal conversion clock. An input high indicates an external conversion clock will be assigned to Pin 16 (EXTCLKIN). SER/PAR (Pin 21): Data Output Mode. SHDN (Pin 22): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = 0 for nap mode and CS = 1 for sleep mode. RD (Pin 23): Read Input. This enables the output drivers when CS is low. CONVST (Pin 24): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 25): Chip Select. This input must be low for the ADC to recognize the CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BUSY (Pin 26): The BUSY Output Shows the Converter Status. It is low when a conversion is in progress. VSS (Pin 27): Negative Supply, – 5V for Bipolar Operation. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. Analog ground for unipolar operation. VDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. TEST CIRCUITS Load Circuits for Access Timing 5V 1k DBN 1k DGND A) HI-Z TO VOH AND VOL TO VOH CL DBN CL DGND B) HI-Z TO VOL AND VOH TO VOL 1418 TC01 U U U Load Circuits for Output Float Delay 5V 1k DBN 1k 30pF DBN 30pF A) VOH TO HI-Z B) VOL TO HI-Z 1418 TC02 7 LTC1418 FUNCTIONAL BLOCK DIAGRA CSAMPLE AIN+ CSAMPLE AIN– VREF 2.5V 8k 2.5V REF ZEROING SWITCHES VDD: 5V VSS: 0V FOR UNIPOLAR MODE – 5V FOR BIPOLAR MODE REF AMP 14-BIT CAPACITIVE DAC REFCOMP AGND DGND 4.096V SUCCESSIVE APPROXIMATION REGISTER INTERNAL CLOCK 14 SHIFT REGISTER • • • D13 D0 D3/(SCLK) MUX CONTROL LOGIC D1/(DOUT) 1418 BD D4 (EXTCLKIN) D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY NOTE: PIN NAMES IN PARENTHESES REFER TO SERIAL MODE APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1418 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel or serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). AIN+ SAMPLE CSAMPLE+ HOLD SAMPLE CSAMPLE HOLD CDAC+ – 8 W + COMP U W U U U U – ZEROING SWITCHES HOLD HOLD AIN – + VDAC+ CDAC– COMP – VDAC– 14 SAR OUTPUT LATCH D13 D0 1418 F01 Figure 1. Simplified Block Diagram LTC1418 APPLICATIONS INFORMATION Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 1µs will provide enough time for the sample-andhold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 14-bit data word) which represent the difference of AIN+ and AIN– are loaded into the 14-bit output latches. DYNAMIC PERFORMANCE The LTC1418 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1418 FFT plot. Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 200kHz sampling rate and a 10kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 100kHz. Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 200kHz the LTC1418 maintains near ideal ENOBs up to the Nyquist input frequency of 100kHz (refer to Figure 3). 0 –20 fSAMPLE = 200kHz fIN = 9.9609375kHz SFDR = 99.32 SINAD = 82.4 AMPLITUDE (dB) AMPLITUDE (dB) U W U U –40 –60 –80 –100 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 F02a Figure 2a. LTC1418 Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz 0 –20 –40 –60 –80 fSAMPLE = 200kHz fIN = 97.509765kHz SFDR = 94.29 SINAD = 81.4 –100 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 F02b Figure 2b. LTC1418 Nonaveraged, 4096 Point FFT, Input Frequency = 97.5kHz 9 LTC1418 APPLICATIONS INFORMATION 14 13 12 11 EFECTIVE BITS 10 9 8 7 6 5 4 3 2 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1418 F03 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: AMPLITUDE (dB) V22 + V32 + V42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is THD = 20Log 0 –20 –40 –60 –80 –100 –120 3RD THD 2ND AMPLITUDE (dB BELOW THE FUNDAMENTAL) 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1418 G03 Figure 4. Distortion vs Input Frequency 10 U W U U shown in Figure 4. The LTC1418 has good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD fa + fb = 20Log 0 – 20 – 40 – 60 – 80 fSAMPLE = 200kHz fIN1 = 97.65625kHz fIN2 = 104.248046kHz ( ) Amplitude at fa + fb Amplitude at fa ( ) –100 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 G05 Figure 5. Intermodulation Distortion Plot Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. LTC1418 APPLICATIONS INFORMATION Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1418 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1418 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and A IN– inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1418 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts — 1µs for full throughput rate. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, choose an amplifier that has a low output impedance (