LTC1419ACSW

LTC1419 14-Bit, 800ksps Sampling A/D Converter with Shutdown FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Sample Rate: 800ksps Power Dissipation: 150mW 81.5dB S/(N + D) and 93dB THD No Missing Codes No Pipeline Delay Nap and Sleep Shutdown Modes Operates with 2.5V Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 20MHz Full-Power Bandwidth Sampling Bipolar Input Range: ± 2.5V 28-Pin SSOP and SO Packages The LTC ®1419 is a 1µs, 800ksps, 14-bit sampling A/D converter that draws only 150mW from ± 5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low power systems. The LTC1419 has a full-scale input range of ± 2.5V. Outstanding AC performance includes 81.5dB S/(N + D) and 93dB THD with a 100kHz input; 80dB S/(N + D) and 86dB THD at the Nyquist input frequency of 400kHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 20MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a µP compatible, 14-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5581252. APPLICATIO S ■ ■ ■ ■ ■ ■ Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems TYPICAL APPLICATIO 800kHz, 14-Bit Sampling A/D Converter LTC1419 DIFFERENTIAL 1 AVDD +AIN ANALOG INPUT (–2.5V TO 2.5V) 2 –AIN DVDD 3 VREF VSS 4 REFCOMP BUSY 5 10µF AGND CS 6 D13(MSB) CONVST 7 D12 RD 8 D11 SHDN 9 D10 D0 10 D9 D1 11 14-BIT D8 D2 PARALLEL 12 D7 D3 BUS 13 D6 D4 14 DGND D5 5V 28 27 26 25 24 23 22 21 20 19 18 17 16 15 µP CONTROL LINES 10µF –5V 10µF Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency 14 13 12 11 EFFECTIVE BITS VREF OUTPUT 2.50V 1µF 10 9 8 7 6 5 4 3 2 fSAMPLE = 800kHz 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1419 TA01 U 86 80 74 68 62 SIGNAL/(NOISE + DISTORTION) (dB) U U 2M 1419 TA02 1419fb 1 LTC1419 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW +AIN 1 –AIN 2 VREF 3 REFCOMP 4 AGND 5 D13(MSB) 6 D12 7 D11 8 D10 9 D9 10 D8 11 D7 12 D6 13 DGND 14 G PACKAGE 28-LEAD PLASTIC SSOP 28 AVDD 27 DVDD 26 VSS 25 BUSY 24 CS 23 CONVST 22 RD 21 SHDN 20 D0 19 D1 18 D2 17 D3 16 D4 15 D5 SW PACKAGE 28-LEAD PLASTIC SO AVDD = VDD = DVDD (Notes 1, 2) Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3).............................(VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ......... (VSS – 0.3V) to 10V Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1419C .............................................. 0°C to 70°C LTC1419I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1419ACG LTC1419ACSW LTC1419AIG LTC1419AISW LTC1419CG LTC1419CSW LTC1419IG LTC1419ISW TJMAX = 125°C, θJA = 95°C/W (G) TJMAX = 125°C, θJA = 130°C/W (SW) Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult factory for Military grade parts. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) Internal Reference External Reference = 2.5V IOUT(REF) = 0 (Note 7) CONDITIONS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6) MIN ● ● ● ● LTC1419 TYP ± 0.8 ± 0.7 ±5 ± 10 ±5 ± 15 MAX ±2 ± 1.5 ± 20 ± 60 MIN 14 LTC1419A TYP MAX ± 0.6 ± 0.5 ±5 ± 10 ±5 ±15 ± 1.25 ±1 ± 20 ± 60 UNITS Bits LSB LSB LSB LSB LSB ppm/°C 13 A ALOG I PUT The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER VIN IIN CIN tACQ t AP t jitter CMRR Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio – 2.5V < (– AIN = AIN) < 2.5V CONDITIONS 4.75V ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ – 4.75V CS = High Between Conversions During Conversions ● ● ● MIN TYP ± 2.5 MAX ±1 UNITS V µA pF pF 15 5 90 –1.5 2 60 300 psRMS dB 1419fb 2 U ns ns W U U WW W U U U LTC1419 DY A IC ACCURACY The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth S/(N + D) ≥ 77dB SYMBOL S/(N + D) THD SFDR IMD CONDITIONS 100kHz Input Signal 390kHz Input Signal 100kHz Input Signal, First 5 Harmonics 390kHz Input Signal, First 5 Harmonics 100kHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz ● ● ● I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER VIH VIL IIN CIN VOH High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage VDD = 4.75V IO = – 10µA IO = – 200µA VDD = 4.75V IO = 160µA IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9 ) VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN ● ● ● VOL Low Level Output Voltage IOZ COZ ISOURCE ISINK Hi-Z Output Leakage D13 to D0 Hi-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current POWER REQUIRE E TS SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Nap Mode Sleep Mode Negative Supply Current Nap Mode Sleep Mode The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS (Note 10) (Note 10) ● ISS UW U U U WU MIN 78 TYP 81.5 80.0 – 93 – 86 – 95 – 86 20 1 MAX UNITS dB dB – 86 – 86 dB dB dB dB MHz MHz U U (Note 5) MIN 2.480 TYP 2.500 ± 15 0.05 2 4.06 MAX 2.520 UNITS V ppm/°C LSB/V kΩ V 4.75V ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V – 0.1mA ≤ ⏐IOUT⏐ ≤ 0.1mA IOUT = 0 TYP MAX 0.8 ± 10 UNITS V V µA pF V V V V µA pF mA mA 2.4 5 4.5 ● 4.0 0.05 0.10 ● ● ● 0.4 ± 10 15 – 10 10 MIN 4.75 – 4.75 TYP MAX 5.25 – 5.25 UNITS V V mA mA µA mA µA µA 1419fb SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V ● 11 1.5 250 19 100 1 20 30 SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V 3 LTC1419 POWER REQUIRE E TS SYMBOL PARAMETER PDIS Power Dissipation Nap Mode Sleep Mode The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS ● TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ + CONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition + Conversion Time CS to RD Setup Time CS↓ to CONVST↓ Setup Time CS↓ to SHDN↓ Setup Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY↑ The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS ● ● ● ● SHDN↑ to CONVST↓ Wake-Up Time (Note 10) (Notes 10, 11) CL = 25pF ● ● ● Delay Between Conversions Wait Time RD↓ After BUSY↑ Data Access Time After RD↓ t11 Bus Relinquish Time 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C RD Low Time CONVST High Time ● ● ● ● t12 t13 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime. Note 2: All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise specified. 4 UW MIN TYP 150 7.5 1.2 MAX 240 12 UNITS mW mW mW SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V UW MIN 800 TYP 950 90 1040 MAX 1150 300 1250 UNITS kHz ns ns ns ns ns ns (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) ● ● 0 40 40 400 40 20 50 20 15 40 –5 15 25 35 35 50 20 25 30 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 10) (Note 9) CL = 25pF ● ● ● CL = 100pF ● 20 10 t 10 40 Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with – AIN grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 650ns after the start of the conversion or after BUSY rises. 1419fb LTC1419 TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude 90 AMPLITUDE (dB BELOW THE FUNDAMENTAL) SIGNAL/(NOISE + DISTORTION) (dB) 80 70 60 50 40 30 20 10 0 1k SIGNAL-TO -NOISE RATIO (dB) VIN = 0dB VIN = – 20dB VIN = – 60dB 100k 10k INPUT FREQUENCY (Hz) Spurious-Free Dynamic Range vs Input Frequency 0 0 – 20 SPURIOUS-FREE DYNAMIC RANGE (dB) –10 –20 –30 –40 –50 –60 –70 –80 – 90 –100 –110 10k –120 100k INPUT FREQUENCY (Hz) 1M 2M 0 50 –100 AMPLITUDE (dB) – 40 – 60 – 80 DNL ERROR (LSBs) AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) Integral Nonlinearity vs Output Code 1.0 –20 –30 –40 –50 –60 –70 –80 –90 –100 1k DGND 100k 10k RIPPLE FREQUENCY (Hz) 1M 2M VDD VSS 0.5 COMMON MODE REJECTION (dB) INL ERROR (LSBs) 0 – 0.5 –1.0 0 4096 12288 8192 OUTPUT CODE 16384 1419 G07 UW 1419 G01 1419 G04 Signal-to-Noise Ratio vs Input Frequency 90 80 70 60 50 40 30 20 10 0 1M 2M 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – 110 Distortion vs Input Frequency THD 2ND 3RD 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1419 G03 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1419 G02 Intermodulation Distortion Plot fSAMPLE = 800kHz fIN1 = 95.8984375kHz fIN2 = 104.1015625kHz Differential Nonlinearity vs Output Code 1.0 0.5 0 – 0.5 –1.0 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 G05 0 4096 12288 8192 OUTPUT CODE 16384 1419 G06 Power Supply Feedthrough vs Ripple Frequency 0 –10 80 70 60 50 40 30 20 10 0 Input Common Mode Rejection vs Input Frequency 1 1000 10 100 INPUT FREQUENCY (Hz) 10000 1419 G09 1419 G08 1419fb 5 LTC1419 PI FU CTIO S + AIN (Pin 1): ± 2.5V Positive Analog Input. – AIN (Pin 2): ± 2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The output format is 2’s complement. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The output format is 2’s complement. SHDN (Pin 21): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = 0 for nap mode and CS = 1 for sleep mode. RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): Chip Select. The input must be low for the ADC to recognize CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. FU CTIO AL BLOCK DIAGRA +AIN – AIN 2k VREF 2.5V REF ZEROING SWITCHES REF AMP REFCOMP (4.096V) AGND DGND INTERNAL CLOCK CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER 14 OUTPUT LATCHES • • • D13 D0 6 W U U U U U CSAMPLE CSAMPLE AVDD DVDD VSS + 14-BIT CAPACITIVE DAC COMP – 1419 BD SHDN CONVST RD CS BUSY 1419fb LTC1419 TEST CIRCUITS Load Circuits for Access Timing 5V 1k DBN 1k CL DBN CL DBN 1k 100pF DBN 100pF Load Circuits for Output Float Delay 5V 1k (A) Hi-Z TO VOH (B) Hi-Z TO VO 1419 TC01 (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1419 TC02 APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1419 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. +CSAMPLE +AIN SAMPLE HOLD SAMPLE –CSAMPLE HOLD +CDAC ZEROING SWITCHES HOLD –AIN HOLD + +VDAC –CDAC COMP – 14 SAR –VDAC OUTPUT LATCHES 1419 F01 Figure 1. Simplified Block Diagram U W U U During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the + AIN and – AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 200ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, putting the comparator into compare mode. The input switches the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the + AIN and – AIN input charges. The SAR contents (a 14-bit data word) which represents the difference of + AIN and – AIN are loaded into the 14-bit output latches. DYNAMIC PERFORMANCE The LTC1419 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for 1419fb • D13 • • D0 7 LTC1419 APPLICATIONS INFORMATION frequencies outside the fundamental. Figure 2 shows a typical LTC1419 FFT plot. 0 – 20 – 40 – 60 – 80 –100 –120 –140 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 F02a fSAMPLE = 800kHz fIN = 99.804687kHz SFDR = 98dB THD = –93.3dB AMPLITUDE (dB) Figure 2a. LTC1419 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz 0 – 20 – 40 – 60 – 80 –100 –120 –140 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 F02b EFFECTIVE BITS fSAMPLE = 800kHz fIN = 375kHz SFDR = 88.3dB SINAD = 80.1 AMPLITUDE (dB) Figure 2b. LTC1419 Nonaveraged, 4096 Point FFT, Input Frequency = 375kHz Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 800kHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 400kHz. 8 U W U U Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 800kHz, the LTC1419 maintains near ideal ENOBs up to the Nyquist input frequency of 400kHz (refer to Figure 3). 14 13 12 11 10 9 8 7 6 5 4 3 2 fSAMPLE = 800kHz 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M 86 80 74 68 62 SIGNAL/(NOISE + DISTORTION) (dB) 1419 TA02 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V22 + V32 + V 42 + … Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 4. The LTC1419 has good distortion performance up to the Nyquist frequency and beyond. THD = 20Log 1419fb LTC1419 APPLICATIONS INFORMATION AMPLITUDE (dB BELOW THE FUNDAMENTAL) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – 110 1k 3RD 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1419 G03 THD 2ND Figure 4. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include 0 – 20 AMPLITUDE (dB) fSAMPLE = 800kHz fIN1 = 95.8984375kHz fIN2 = 104.1015625kHz – 40 – 60 – 80 –100 –120 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 G05 Figure 5. Intermodulation Distortion Plot U W U U (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD fa + fb = 20 Log ( ) Amplitude at (fa + fb) Amplitude at fa Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1419 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1419 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the – AIN input is grounded). The + AIN and – AIN inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1419 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is 1419fb 9 LTC1419 APPLICATIONS INFORMATION that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 200ns for full throughput rate). 10 ACQUISITION TIME (µs) 1 0.1 0.01 0.01 1 10 0.1 SOURCE RESISTANCE (kΩ) 100 1419 F06 Figure 6. tACQ vs Source Resistance Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 20MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1419 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1419. More detailed information is available in the Linear Technology databooks, the LinearViewTM CD-ROM and on our web site at www.lineartech. com. LinearView is a trademark of Linear Technology Corporation. 10 U W U U LT ® 1220: 30MHz unity-gain bandwidth voltage feedback amplifier. ± 5V to ± 15V supplies. Excellent DC specifications. LT1223: 100MHz video current feedback amplifier. ± 5V to ± 15V supplies, 6mA supply current. Low distortion at frequencies above 400kHz. Low noise. Good for AC applications. LT1227: 140MHz video current feedback amplifier. ± 5V to ± 15V supplies, 10mA supply current. Lowest distortion at frequencies above 400kHz. Low noise. Best for AC applications. LT1229/LT1230: Dual/quad 100MHz current feedback amplifiers. ± 2V to ± 15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1360: 50MHz voltage feedback amplifier. ± 5V to ± 15V supplies, 3.8mA supply current. Good AC and DC specs. LT1363: 70MHz, 1000V/µs op amps, 6.3mA supply current. Good AC and DC specs. LT1364/LT1365: Dual and quad 70MHz, 1000V/µs op amps. 6.3mA supply current per amplifier. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1419 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 20MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for ANALOG INPUT 50Ω 1000pF 2 –AIN LTC1419 3 VREF 1 +AIN 4 10µF 5 REFCOMP AGND 1419 F07 Figure 7. RC Input Filter 1419fb LTC1419 APPLICATIONS INFORMATION many applications. For example, Figure 7 shows a 1000pF capacitor from + AIN to ground and a 100Ω source resistor to limit the input bandwidth to 1.6MHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Input Range The ± 2.5V input range of the LTC1419 is optimized for low noise and low distortion. Most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1419 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1419 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3) see Figure 8a. A 3 VREF R1 2k BANDGAP REFERENCE 5V VIN LT1019A-2.5 VOUT ANALOG INPUT 1 2 3 +AIN –AIN VREF LTC1419 4 2.500V 4.0625V 4 REFCOMP REFERENCE AMP R2 40k R3 64k LTC1419 1419 F08a 10µF 5 AGND Figure 8a. LTC1419 Reference Circuit U W U U + REFCOMP 10µF 0.1µF 5 AGND 1419 F08b Figure 8b. Using the LT1019-2.5 as an External Reference 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry, see Figure 8b. The reference amplifier gains the voltage at the VREF pin by 1.625 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or 10µF tantalum in parallel with a 0.1µF ceramic is recommended. The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1419 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment. 1 ANALOG INPUT 1.25V TO 3V DIFFERENTIAL +AIN 2 –AIN LTC1419 LTC1450 1.25V TO 3V 3 VREF 4 10µF 5 REFCOMP AGND 1419 F09 Figure 9. Driving VREF with a DAC 1419fb 11 LTC1419 APPLICATIONS INFORMATION Differential Inputs The LTC1419 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of + AIN – (– AIN) independent of the common mode voltage (see Figure 11a). The common mode rejection holds up to extremely high frequencies, see Figure 10a. The only requirement is that both inputs can not exceed the AVDD or AVSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from 86dB with a common mode of 0V to 76dB with a common mode of 2.5V or – 2.5V. 80 COMMON MODE REJECTION (dB) 70 60 OUTPUT CODE 1 1000 10 100 INPUT FREQUENCY (Hz) 10000 50 40 30 20 10 0 1419 G09 Figure 10a. CMRR vs Input Frequency 1 2 ±2.5V 0V TO 5V ANALOG INPUT +AIN –AIN R8 50k + – 3 VREF LTC1419 R5 R7 47k 50k R6 24k 4 10µF 5 REFCOMP AGND 1419 F10 Figure 10b. Selectable 0V to 5V or ± 2.5V Input Range 12 U W U U Differential inputs allow greater flexibility for accepting different input ranges. Figure 10b shows a circuit that converts a 0V to 5V analog input signal with only an additional buffer that is not in the signal path. Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the LTC1419. The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is two’s complement binary with 1LSB = FS – (– FS)/16384 = 5V/16384 = 305.2µV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 11b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 – (FS – 1LSB) FS – 1LSB 1419 F11a INPUT VOLTAGE [+AIN – (–AIN)] Figure 11a. LTC1419 Transfer Characteristics 5V R3 24k ANALOG INPUT 1 2 3 4 5 +AIN –AIN LTC1419 VREF REFCOMP AGND 1419 F11b R4 100Ω + 10µF 0.1µF Figure 11b. Offset and Full-Scale Adjust Circuit 1419fb LTC1419 APPLICATIONS INFORMATION applied to the – AIN input. For zero offset error, apply – 152µV (i.e., – 0.5LSB) at + AIN and adjust the offset at the – AIN input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.499544V (FS/2 – 1.5LSBs) is applied to + A IN a nd R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. BOARD LAYOUT AND GROUNDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1419, a printed circuit board with ground plane is required. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.The analog input should be screened by AGND. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1419 has differential inputs to minimize noise coupling. Common mode noise on the + AIN and – AIN leads will be rejected by the input CMRR. The – AIN input can be used as a ground sense for the + AIN input; the LTC1419 will hold and convert the difference voltage between + AIN and – AIN. The leads to + AIN (Pin 1) and – AIN (Pin 2) should be kept as short as possible. In applications where this is not possible, the + AIN and – AIN traces should be run side by side to equalize coupling. SUPPLY BYPASSING High quality, low series resistance ceramic, 10µF bypass capacitors should be used at the VDD and REFCOMP pins as shown in the Typical Application on the fist page of this data sheet. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively, 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Example Layout Figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. 1 +AIN –AIN REFCOMP AGND 5 10µF 2 ANALOG INPUT CIRCUITRY + – 4 ANALOG GROUND PLANE 1419 F12 Figure 12. Power Supply Grounding Practice 1419fb U W U U LTC1419 VSS 26 10µF AVDD DVDD 28 27 10µF DGND 14 DIGITAL SYSTEM 13 LTC1419 C2 22µF 10V D00 D0 D1 D2 D3 D4 D5 R6 R7 D07 U5 74HC574 1 B[00:13] B00 B01 C3 VSS 0.1µF B02 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 20 B00 19 B01 18 B02 17 B03 16 B04 B12 B11 B10 B09 B08 B07 B06 15 B05 13 B06 12 B07 1 11 2 3 4 5 6 7 8 9 DATA READY VLOGIC 5 14 U7F 13 HC14 7 VCC U7G HC14 GND 12 C15 0.1µF HC14 U7C 6 R21 1k U7D 9 HC14 C16 15pF 8 11 B08 10 B09 9 D7 9 D6 B10 B13 8 8 D5 B11 B05 Q5 Q6 Q7 U6 74HC574 0E D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 D12 D11 D10 D09 D08 D07 D06 11 HC14 U7E 10 D13 7 7 D4 Q4 B12 B04 14 13 12 6 15 6 D3 Q3 B13 B03 5 16 D2 Q2 D03 D04 D05 D13 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D13 RDY J6-13 J6-14 J6-11 J6-12 J6-9 J6-10 J6-7 J6-8 J6-5 J6-6 J6-3 J6-4 J6-1 J6-2 J6-15 J6-16 J6-17 J6-18 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D13 RDY DGND DGND HEADER 18-PIN 4 17 D02 D12 D13 1 2 3 4 25 24 23 22 21 28 27 26 VCC VSS 14 DGND AGND 5 VSS DVDD AVDD SHDN RD CONVST CS BUSY REFCOMP VREF –AIN +AIN D1 Q1 U4 LTC1419 3 18 D01 D0 Q0 2 19 D00 11 0E D08 D09 D10 D11 R8 R9 R10 R11 R12 R13 D6 D7 D8 D9 D10 D11 D12 D13 D01 D02 D03 VCC C4 0.1µF D04 D05 VOUT D06 R5 R4 R3 R2 R1 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 LED JP1 GND C6 1000pF JP3 AGND DGND A+ R17 10k C11 1000pF U3 V+ LT1363 27 – 6 3+ 8 1 V– 4 APPLICATIONS INFORMATION R18 10k A– R16 51Ω J5 C7 1000pF C8 1µF 16V C13 10µF 16V J7 U7A U7B CLK 1 2 3 4 R19 51Ω HC14 HC14 VLOGIC C9 10µF 16V C5 10µF 16V JP5C CS JP5B RD JP5A SHDN R20 1M NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5% 2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10% DC124 SCHEM Figure 13a. Suggested Evaluation Circuit Schematic U JP4 W J4 JP2 R15 51Ω U J2 U C10 10µF 10V + 14 VCC VCC R14 20Ω –VIN D[00:13] R0 1.2k C1 22µF 10V D00 D01 C12 0.1µF C14 0.1µF VLOGIC VSS J1 –7V TO –15V 2 U2 LT1121-5 +VIN J3 7V TO 15V 1 VIN VOUT 3 GND TABGND 2 4 D15 SS12 + + U1 79L05 1 IN OUT GND 5 D14 SS12 1419fb LTC1419 APPLICATIONS INFORMATION Figure 13b. Suggested Evaluation Circuit Board—Component Side Silkscreen Figure 13c. Suggested Evaluation Circuit Board—Component Side Layout 1419fb U W U U 15 LTC1419 APPLICATIONS INFORMATION Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 0.95µs and a maximum conversion time over the full operating temperature range of 1.15µs. No external adjustments are required. The guaranteed maximum acquisition time is 300ns. In addition, a throughput time of 1.25µs and a minimum sampling rate of 800ksps are guaranteed. Power Shutdown The LTC1419 provides two power shutdown modes, nap and sleep, to save power during inactive periods. The nap 16 U W U U mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from nap to active is 400ns. In sleep mode, the reference is shut down and only a small current remains, about 250µA. Wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 10ms with the recommended 10µF capacitor. Shutdown is controlled by Pin 21 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (CS); low selects nap. CS t3 SHDN 1419 F14a Figure 14a. CS to SHDN Timing 1419fb LTC1419 APPLICATIONS INFORMATION SHDN t3 CONVST 1419 F14b Figure 14b. SHDN to CONVST Wake-Up Timing Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic “0” applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. Figures 16 through 20 show several different modes of operation. In modes 1a and 1b (Figures 16 and 17), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 18), CS is tied low. The falling edge of the CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. CS = RD = 0 (SAMPLE N) t5 CONVST t6 BUSY t7 DATA DATA (N – 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F16 Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) U W U U In slow memory and ROM modes (Figures 19 and 20), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a WAIT state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. CS t1 RD 1419 F15 Figure 15. CS to CONVST Set-Up Timing t CONV t8 1419fb 17 LTC1419 APPLICATIONS INFORMATION CS = RD = 0 t13 CONVST t6 BUSY t7 DATA DATA (N – 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F17 tCONV t5 Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) CS = 0 (SAMPLE N) tCONV t5 CONVST t6 BUSY t9 t 12 RD t 10 DATA DATA N DB13 TO DB0 1419 F18 Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD CS = 0 (SAMPLE N) RD = CONVST t6 BUSY t 10 DATA t CONV DATA (N – 1) DB13 TO DB0 Figure 19. Slow Memory Mode Timing 18 U W U U t8 t6 t6 t13 t8 t 11 t8 t 11 t7 DATA N DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F19 1419fb LTC1419 APPLICATI S I FOR ATIO t CONV (SAMPLE N) CS = 0 RD = CONVST t6 BUSY t 10 DATA t 11 DATA (N – 1) DB13 TO DB0 Figure 20. ROM Mode Timing PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 5.20 – 5.38** (0.205 – 0.212) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U t8 DATA N DB13 TO DB0 1419 F20 W U U UO 10.07 – 10.33* (0.397 – 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.73 – 1.99 (0.068 – 0.078) 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) 0.05 – 0.21 (0.002 – 0.008) G28 SSOP 1098 1419fb 19 LTC1419 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NOTE 1 0.394 – 0.419 (10.007 – 10.643) 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 0° – 8° TYP 1 0.093 – 0.104 (2.362 – 2.642) 2 3 4 5 6 7 8 9 10 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) S28 (WIDE) 1098 RELATED PARTS PART NUMBER LTC1278/79 LTC1400 LTC1409 LTC1410 LTC1415 LTC1604 LTC1605 LTC1606 LTC1608 DESCRIPTION Single Supply, 500ksps/600ksps ADCs High Speed, Serial 12-Bit ADC Low Power, 12-Bit, 800ksps Sampling ADC 12-Bit, 1.25Msps Sampling ADC with Shutdown Single 5V, 12-Bit 1.25Msps ADC 16-Bit 333ksps ADC Single 5V, 16-Bit 100ksps ADC 16-Bit 250ksps ADC 16-Bit 500ksps ADC COMMENTS Low Power, 5V or ± 5V Supply 400ksps, Complete with Internal Reference, SO-8 Package Best Dynamic Performance, fSAMPLE ≤ 800ksps, 80mW Dissipation Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist Single Supply, 55mW Dissipation ±2.5V Inputs, Pin Compatible with the LTC1608 Low Power, ±10V Inputs ±10V Inputs, Pin Compatible with the LTC1605 ±2.5V Inputs, Pin Compatible with the LTC1604 1419fb LT 0506 REV B • PRINTED IN USA 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com © LINEAR TECHNOLOGY CORPORATION 1997